Applications for Mapper technology Bert Jan Kampherbeek

Transcription

1 Applications for Mapper technology Bert Jan Kampherbeek Co-founder & CEO

2 Today s agenda Mapper technology Principles of operation Development status and performance Specification summary Mapper applications Fab lifetime extension (technology innovation in an existing fab) Truly unique chips Photonics Unlimited field size Maskless lithography / cost advantage Applications for Mapper technology 2

3 Today s agenda Mapper technology Principles of operation Development status and performance Specification summary Mapper applications Fab lifetime extension (technology innovation in an existing fab) Truly unique chips Photonics Unlimited field size Maskless lithography / cost advantage Applications for Mapper technology 3

4 Mapper makes e-beam direct write for volume manufacturing possible Traditional e-beam Mapper FLX FLX extension 1 electron beam per system No scaling with 50keV No optical alignment 65,000 beamlets per unit Scaling with 5keV Compatible, optical, alignment 650,000 beamlets per unit Evolution on the same platform Unit clustering for >40 wph No full wafer placement accuracy Matching to DUV and 193i < 25 full 300 mm wafers per month wafers per month (300 mm) >5,000 wafers per month/unit Throughput proportional to pattern density and resolution Lab use only Throughput independent of pattern density and resolution nm - 28nm logic node It takes minutes only to expose a wafer at <50nm 28nm logic node and below Applications for Mapper technology 4

5 FLX is Mapper s 3 rd generation EBDW platform, currently entering the market Demonstrator kev 110 beams 0.6µm blanker 45 nm half-pitch Small field, no positioning No metrology Pre-alpha kev 110 beams 0.6µm blanker nm half-pitch Wafer stage Advanced metrology and dose control FLX-series now 5 kev 65,000 beams N65 blanker 42 nm half-pitch Full field and full wafer Compatible, optical, alignment and matching Manual wafer handling 100 wafers exposed FOUP handling >2,500 wafers exposed wafers per month/unit (300mm) system built R&D tool shipped to customers Production tool 5 systems built N40 N28 nodes Applications for Mapper technology Track integration 5

6 Basic operation Beam generator Blanker detail: one of many thousands of apertures, made in 65nm TSMC e Condenser lens and blanker Wafer Projection optics Pixel on The electron optics have no central crossovers making them intrinsically insensitive to Coulomb forces (electron repulsion) Pixel off The electron optics are modular and much cheaper than high-na DUV optics, and can be replaced or upgraded in the field Alignment targets in scribe lanes Wafer exposure happens one column at a time and always in the same direction no need to meander Focus / leveling is performed during stage fly-back to reduce metrology overhead Exposure scan 1 Exposure scan 2 Exposure scan 3 Exposure scan 4 Each column is aligned separately, with dedicated alignment targets Applications for Mapper technology 6

7 Optical fiber bundle for data transfer to beam blanker More than 800 fibers connected to first blanker chip 3,000,000 megapixels per second streaming rate Final configuration will have 30 x 10 6 megapixels per second transfer rate Electrons Beam blanker chip (behind shield) Applications for Mapper technology 7

8 Development status: full column operational at CEA-LETI as of August k beams in 13x2 mm 2 slit. First exposures after upgrade to fully programmable blanker: 60 nm HP (N40) Good for market entry Getting close to covering a full 300 mm wafer in 60 minutes Applications for Mapper technology 40 nm HP (sub N28) Some improvements still needed 8

9 FLX imaging results: 60 nm VIA process window, unbiased Applications for Mapper technology 9

10 Demonstration of resolution extendibility with 5 kev SRAM M1, 38 nm half-pitch Lines M2, 36 nm half-pitch Dense logic M1, 32 nm half-pitch Pre-alpha tool 32nm 28nm 24nm 22nm 20nm 18nm 16nm Applications for Mapper technology 10

11 Today s agenda Mapper technology Principles of operation Development status and performance Specification summary Mapper applications Fab lifetime extension (technology innovation in an existing fab) Truly unique chips Photonics Unlimited field size Maskless lithography / cost advantage Applications for Mapper technology 11

12 FLX is designed for high-volume specialties and low-volume advanced logic 1. Wafer fab extension Extend resolution or density below 100 nm in 200 mm fabs NVRAM capacity increase in existing processes RF, mmwave and 5G applications 2. Truly unique chips 3. Large field size 4. Maskless lithography Logic level per-chip diversification in volume manufacturing Data security Identification and traceability Anti-counterfeiting Mapper has no true field size limitation Large field image sensors MEMS FLX supports the full product life-cycle: from R&D and rapid prototyping, to full-fledged manufacturing 10M to 100M OPEX savings per fab by eliminating costly critical masks N45 and below for volumes up to 1,000 wafers per design Specialized low volume applications Long tail extension and Industry 4.0 applications 5. Full 2D patterning E-beam has no low-k 1 restrictions at the highest resolutions Layer reduction in N28 and below Photonics Applications for Mapper technology 12

13 Wafer fab technology extension There are very few good options for upgrading lithography capability in existing 200 mm fabs using optical lithography Conversion to 300 mm is prohibitively expensive Using 300 mm litho tools in 200 mm mode is also expensive and inefficient Mapper can boost lithographic performance from ~100 nm to 45 nm and below No need for expensive OPC masks or multiple patterning techniques Can be used for the critical FEOL layers only, while continuing to use existing optical litho tools for non critical FEOL and BEOL layers The investment in Mapper is relatively modest, and can be recovered in the elimination of expensive FEOL reticles Source: Global 200mm Fab Outlook, SEMI October 2015 Applications for Mapper technology 13

14 Mapper can break barriers between technology nodes Technology node Optical lithography Mapper / maskless 110 KrF ArF dry FLX series ArF immersion Multiple patterning Next gen Ref: More than Moore / TSMC Applications for Mapper technology 14

15 Fab lifetime extension with selected features Mapper feature Application Increased resolution Shrink SiGe transistor base for increased f T and bandwidth (5G) Increased density Increase NVRAM capacity in existing design Large focus range Mixed applications on chip Improve transistor performance 28 nm node compatible CDu Image sensors No geometry restrictions Full-2D patterning: any pitch, any orientation, any CD, in any combination Photonics applications, wave guides X-routing in metal layers (45, 33, etc..) Layer count reduction Virtual node shrink, esp. at 28 nm Wide spectrum imaging Resolution and density shrink True node shrink for logic in Cu-enabled fab, without ArF/ArF-i Applications for Mapper technology 15

16 Technology migration Example <90nm SiGe technology on 8 Basic SiGe transistor (and M1) using Mapper for small feature size and (much) higher f T Improved lateral control Baseline CMOS and M2-M6 stack keeps using conventional M130 flow 60 nm bipolar transistor incl. Ge implant (e-beam) Mapper layers Applications for Mapper technology 16

17 Technology migration: ROM and structured ASIC M28 old ROM Mask ROM via (1 expensive OPC mask) M28 Back End M2-M11 (20 mask) M28 new with Mapper ROM via layer (1 Mask-free Mapper) M28 CMOS Front End up to M1 Dual oxide for LV (0.9V) and MV (1.3V) transistors (30 immersion mask with OPC) Mapper layers Mapper layer replaces very expensive ROM-via programming layer in nodes where Flash is not available Classical optical mask very expensive due to closely spaced repetitive via pattern Mapper has no problem with these patterns and could even allow smaller ROM dimensions Mapper layer has a much faster turn-around time due to 100% software; one day cycles possible Eliminate need to add external memory simpler and lower cost devices Applications for Mapper technology 17

18 Mapper tool can generate unique pattern for every chip Data security Industrial infrastructure IoT gadgets Digital rights management Mobile storage Smart cards Traceability Anti-counterfeiting Automotive Aviation Medical Postal Retail Defense spare IC s for 20+ year old equipment Luxury goods Bank bills, coins Wafer IC design Unique block Applications for Mapper technology 18

19 Applications of truly unique chips Individualized chip feature Benefit using Mapper Unchangeable codes per chip Extremely small area No need for one-time memory cells, circuitry and fuses Hard to read through side-channels Unique logic modules per chip Added layer of security. Not possible with masks Embedded visual chip ID Anti-counterfeiting. Not possible with masks Randomized metal patterns Added layer of security. Not possible with masks Maskless ROM per IC or product Affordable in advanced nodes where masks are expensive and flash not available. Eliminate external boot ROM. Hard to read through side-channels. Applications for Mapper technology 19

20 Example application, chip individualization in via layer 2 mm 2 chip (not to scale) One unique sub-block Unique area Common area / Metal-N Metal-(N+1) Via-N / Missing via Per-chip uniquely wired area Applications for Mapper technology 20

21 Technology migration: Every chip unique M40 old ROM Mask M40 Back End M3-M9 (14 mask) M40 new with Mapper Secure block layers (1 via layer) M40 CMOS Front End up to M2 Dual oxide for LV (0.9V) and MV (1.3V) transistors (28 immersion mask with OPC) Mapper layers Mapper allows hard-wired, per chip unique IP E.g. security code generator Leaves all other parts off technology mask stack unchanged No additional mask costs, only additional processing time This example assumes secure IP on top of GO1+M1+M2 fixed block structure One via layer with Mapper Many variations possible Applications for Mapper technology 21

22 Multiple process options for unique via layers per chip Source: Mapper customer case study for a 130nm IoT device Option 1. Minimal change to existing flow Option 2: Single CVD & CMP using hard-mask Option 3: Lowest cost per layer Applications for Mapper technology 22

23 Multi e-beam is ideal for bringing photonics devices to volume production High throughput and high resolution Absence of Rayleigh limits gives unrestricted freedom of patterning: - Curved and non-gridded designs - Combining different feature sizes - Combining different orientations - Combining different pitches Large writing area with accurate pattern placement Si and III-V substrates Applications Multi-spectral light filters Bragg gratings Any sub-wavelength features Applications for Mapper technology 23

24 Unlimited field size The Mapper exposure area is limited only by the wafer size and by memory capacity of the write-file storage. Mapper can eliminate costly and technically challenging stitching protocols used for large area devices Eliminates intra-die CD and registration errors Eliminates very costly multiple reticle sets for each patterning layer Mapper Can be expanded to full wafer size with memory upgrades Application examples: High-end photography Next generation automotive sensors Template manufacturing Medical Wafer Stepper, 22 x 22 mm Scanner, 33 x 26 mm Applications for Mapper technology 24

25 TCO savings for long tail products in typical 65-28nm fabs Benefits of maskless lithography in the tail Offloading of high capacity systems Process split approach Lowers the threshold for customized products in advanced technology Potential to extend the tail with new products / business Mask cost savings in existing tail Maximize utilization of FLX system in combination with segment 1-3, payback in <2 years De-risking of development for new products 5 wph/unit 2 wph/unit 1 wph/unit Applications for Mapper technology 25

26 Technology migration: small series Mapper layer replaces a limited number of most expensive optical masks In 65nm the (4) most expensive masks make up 20% of total mask set cost Percentage goes up for smaller nodes due to double or quadruple patterning; 16 mask for 1M$+ cost Using Mapper for the most critical masks of (initially) low volume products substantially lowers introduction costs for customers Mapper layers Applications for Mapper technology 26

27 Thank you Applications for Mapper technology 27