Physical stuff (20 mins) C2S2 Workshop 7/28/06

Transcription

1 Physical stuff (20 mins) C2S2 Workshop 7/28/06 Clive Bittlestone TI Fellow Nagaraj NS DMTS, Roger Griesmer SMTS Carl Vickery SMTS Gopalarao Kadamati MGTS Texas Instruments Texas Instruments 2004,2005,2006

2 Introduction There has been a lot of interesting DFM discussion over the last few years. EDA vendors are delivering and developing tools/flows Academia is participating.. Designers are working out methodology. Fabs ( physics/equipment vendors) are driving changes in rules and models to design. Fabs are working very hard on material science. System level designers are starting to wake up as well. Long distance interconnect on die is struggling to scale Full synchronous chips are going to be a thing of the past. Everyone seems to be lending a hand 2

3 Overview Includes TI material from previous DAC, ISSCC, IEDM, ESSDERC Thickness Shapes Rules and layout styles Stress Overlay 3

4 Why Fill? Manufacturing issues without fill CMP uniformity open, shorts, flakes. Trench fill, seam formation density issues. Mask Chip temp Design Issues without fill Thickness variation within die can be the full process range and beyond (open/shorts) Design will have to run CMP model flow and Thickness aware parasitic extracts. Realistic design will have to use fill. need to minimize electrical impact Need to minimize parametric yield impact. Need to minimize data volume/runtime. 4

5 Many needs come together FA R ET /F ib -OPC /SRA F FAB Electrical impact Fill Methodology Runtime explosion Modeling ita g i D Data explosion ign s e ld al n A o F R / g 5

6 How should we Fill? Array styles, multi-pass/size Density map, lookup, multi pass. Fill shape/size variants Model based CMP only may not be enough. Cmp, Etch, Fill, Trench depth? ILD, IMD?, do we need Multi-layer film models? Hybrid styles of fill. Via fill variants., array, common area, pre defined, power connected.. Timing aware ( critical path or sensitive & close to critical) SSTA / VA extract engine inputs. Power aware ( activity/load aware) OPC friendly.. Layer to layer cumulative aware 6

7 45nm Metal4 thickness examples No fill = full fab range within die! PCD range (Thickness) Fill methodology 1 Timing impact Density clean Fill method 14 Low impact Not D-clean 7

8 Timing Impact (non-stat) Ref A Type 1 Type 3 Type 7 Overkill Density map 8

9 SO..? Model based fill may not be needed.yet. Hybrid fill can meet needs. Design may not need to run CPM sim an thickness aware parasitic extraction. yet. Cmp/etch/fill simulation needs to be used to calibrate hybrid fill. Analog designers need to own their own fill and become fill aware. Cell context is critical for thickness analysis. (sparse fill) Nightmare for chip level (which timing model to use..? Better to control context range from day 1. 9

10 FEOL items 10

11 Poly Flare & Active Flare Active Poly 11

12 Poly Flare 12

13 Active Flare 13

14 90nm Poly/Active example Unstructured layout Wrong way gate No pitch restrictions Routing in Active and poly Many Active jogs Poly flare Active flare No 45 gates. 14

15 65nm Poly/Active example Weak structure No pitch control No routing in Active Flare control rules Vertical orientation Jog control 15

16 Alternate style 3 Active/Poly example Semi structured layout No wrong way gate Pitch restrictions No Routing in Active Significant jogs control Big flare rules Line end rules clear. Semi structured layout Context becoming more predictable. Some chip level DFM may be avoided Cell level DFM still useful? Can we still compose/place without consideration? 16

17 90nm Metal Unstructured layout Low impact Line end rules Low impact Wide metal rules Low impact min area rules 17

18 65 nm Metal/cont Unstructured Line end rules Min area rules worse Metal bin rules worse. 2 directions Model based drc, hotspot and fixups Contour based parasitic extraction? Process corner extraction? Nom, +-DOF/ -+Dose (9) Don t double count in spice models. 18

19 Another alternate style Metal/cont Unstructured Extensive use in both directions Large line end rules expensive Wide metal rules expensive Some pitch control? Min area rules expensive Shape control rules. Cut density. Difficult to manufacture.. OPC Ambit is +- several rows of cells.. Gate level abstraction/compose is in question here 19

20 Metal Pinch/bridge sensitivity must be identified during technology setup Pushing beyond process window to fail points can indicate margin to fail Context is important How to be context insensitive? Change layout for DFM robust Modify process? Make cells robust without growing them. Avoid/minimize need to fix at chip level. 20

21 Scary metal -CMU brick style Extreme structure Unidirectional metal Restricted pitch. Line end rules very expensive Wide metal rules very expensive Grid cont, via1 Grid via2 Process entitlement scale very difficult 21

22 STRESS 22

23 Active Overlap of Gate (AOG,LOD) stress What : Idrive for a fixed gate L varies as a function of active overlap of gate. Why: Physical stress changes mobility in the channel. This type of stress is a function of active overlap of gate.. There are other types of stress to consider as well that are sensitive to gate pitch, poly turns, orthogonal poly, contact type/location, tensile../compressive..etc PMOS NMOS IDSAT IDSAT AOG AOG 23

24 Process Misalignment Modeling Overlay/misalignment is struggling to scale. Misalignment between layers in any direction.( stat distribution) Cells are more sensitive to alignment in certain directions. Impacts several important parameters. Rcont, Cgd, AS, AD, Cgs, Compound this with LOD, contact stress, liner stress damage as well. Internal nodes (light load) in asymmetric layout common in ASIC libraries can be sensitive to this. Also compounds metal pull back (R via) 24

25 Contact misalignment impact on timing. (90nm) Cell Delay vs Contact Misalignment SR50; FanOut=5; Interconnect Load=5SL; Not including stressw_125_1.17_maxc or active misalignment much worse for small loads, think inside a flop % 2.50% Asymmetric Symmetric Delta Delay (%) 2.00% 1.50% IV110 IV170 IV1W0 NA % 0.50% 0.00% % -1.00% Contact Misalignment in X direction (nm) 25

26 General alignment Mirrored cell L-R misalign = asymmetric skew Single cell Mirrored And flipped cells L-R/U-D misalign = asymmetric skew 26