Nanometer Era Design For Manufacturability

Transcription

1 Carnegie Mellon Nanometer Era Design For Manufacturability Andrzej J. Strojwas PDF Solutions Inc., San Jose, CA & Carnegie Mellon University, Pittsburgh, PA IEEE Wescon D2M, Santa Clara, CA April 13, 2005

2 Overview of Presentation DFM/DFY Yield Loss Mechanism Evolution Classification of DFM Approaches True DFM: Defining Proactive DFM Necessary Conditions for Proactive DFM Process Characterization Design Flows that Provide Proactive DFM DFM Results Looking into the Future: Extreme Layout Regularity

3 What is DFM/DFY Yield: Percentage of manufactured products that meet all performance and functionality specifications Yield Loss Mechanisms: Process defects Failure due to void Functional Yield: Chip does not work at all Environmental/Process Variations Out of spec Parametric Yield: Chip works but not within specification

4 Yield is now a Designer Issue Logic DFM Floorplan optimization RTL2GDS design pdfx manufacturability optimization Routing resource analysis and DFM optimization Memory Optimization Bitcell & periphery optimization Redundancy and bitcell allocation Analog DFM Realistic worst-case modeling PLL, ADC/DAC design centering Core (hard macro) Optimization Custom logic DFM optimization Custom routing DFM optimization Full Chip Yield Verification Full chip yield entitlement Hot spot analysis and verification Layout finishing (OPC/MDP) analysis and optimization

5 What is DFM/DFY How can we improve yield? Alleviate yield loss mechanisms Process engineering EDA methodologies to produce more manufacturable features (RET) Make the design more robust to yield loss mechanisms EDA methodologies to improve yield EDA methodologies to design more manufacturable circuits Design For Yield and Manufacturability (DFM/DFY) Yield improvement requires both design and manufacturing solutions

6 The Evolution of Product Yields 100% 90% Yield Limiters by Technology Node Yield 80% 70% 60% 50% 40% Random Defect Limited Yield Design Feature Limited Yield Total Yield 0.8um 0.5um 0.35um 0.25um 0.18um Technology 0.13um Random defects are no longer the dominant yield loss mechanism Yields are limited by design features, systematic and parametric effects 90nm

7 Random Yield Loss Mechanisms Al Interconnect Material opens Material shorts Type Random Yield Loss Mechanisms Active, poly and metal shorts and opens due to particle defects Contact and via opens due to formation defectivity

8 Systematic Yield Loss Mechanisms - Cu Interconnect Failure Rate Sparse neighborhood Via Failure Rate (fpb) Pitch (um) Type Systematic Yield Loss Mechanisms Impact of micro/macro loading design rule marginalities Leakage from STI related stress Contact/via opens due to local neighborhood effects (e.g. pitch/hole size) Misalignment, line-ends/borders

9 Systematic Yield Loss: Printability Nanometer Era Type Systematic Yield Loss Mechanisms Poor contact coverage due to misalignment and defocus/pull back Poly/Metal shorts Material opens

10 Parametric Yield Loss Mechanisms Nanometer Era Environment dependent poly CD variation ACLV / CD Variation Ioff Env I Env II Env III Idrive Type Parametric Yield Loss Mechanisms Performance variation from lithography effects e.g., contact/via coverage, active/poly flaring, CD variation Dummy fill parasitic effects Device mismatch Non-physical corner modeling

11 Technology Challenges: Implications for Manufacturability 90nm Back-end integration issues Low k: stress and reliability CMP - multi-layer topography issues Product ramp issues Variability Yield-performance tradeoffs 65nm Litho: OPC/PSM integration issues w/photo window (DOF) Front-end/Transistor Layout dependent performance Product ramp issues Parametric variations - > yield loss 45nm Litho: Layout pattern dependence, Scanner NA, Immersion litho, OPC/PSM integration, issues w/photo window (DOF) Front end/transistor New transistor architectures (UTB, DG SOI) Product ramp issues Reliability assurance

12 DFM is a Business Opportunity "Seamless" DFM Can Contribute 5% More Good Die What's 5% more good die worth? $50M over the life of a cell phone $80M over the life of a game chip $100M per year per fab at 90nm

13 A Brief History of DFM Functional Yield means Rules Performance Yield is Covered by Corners Idsat Distribution ASIC Corners PIdsat Realistic Corners -450 Design rules guarantee yield! well, not really then recommended rules and opportunistic design data base post-processing to enforce them -500 NIdsat The corners represent the process The corners don t represent the process but they are conservative Within chip variations are important so.. Restrict transistor layouts? Statistical timing simulation?

14 Design IP lib. Design Proactive DFM Physical SP&R Verification and Yield Opt. Timing and SI Analyses Physical Verification Post-GDS Yield Opt. pre-mdp Dummy Fill and Cheesing OPC/ RET Manufacturing MDP and Mask Making Yield Ramp Volume Production Designer access to the process is limited Most DFM today is Reactive Increase in design cycle time Misaligned mask GDSII and design database Risky design feature changes DFM needs to be Proactive Occurring early in the design flow Up-front accurate process characterization Yield modeling to characterize IP and drive EDA tools Design IP lib. Design Physical SP&R Verification and Yield Opt. Timing and SI Analyses Physical Verification Post-GDS Yield Opt. pre-mdp Dummy Fill and Cheesing OPC/ RET Manufacturing MDP and Mask Making Yield Ramp Volume Production Process Characterization + Yield Modeling

15 Necessary Conditions for Pro-Active DFM Accurate characterization of design-interactions at target fab(s) Effects modeled across the whole process window Quantification of alternatives that allow EDA tools to make millions of DFM trade-offs Integration early in the design flow where there are more degrees of freedom Floor planning SP&R Modifications made prior to verification

16 Yield Simulation is Core to Proactive DFM Yield Simulation allows for better understanding of the DFM universe A yield model for DFM: Model of failure rate of a design element (e.g., transistor, contact, via) as a function of the layout design Example: What is the failure rate of a single via vs. double? What is the probability of a short in two metal lines if there are lots of vias underneath them To do this, we need process characterization

17 Process Yield Loss Mechanisms Mx V2 V2 M2 V1 M1 C Poly Active M2 V1 M1 C Poly Yield Loss Mechanisms Layer defect densities Attribute dependent failure rates Lithography / CMP driven interactions Yield Loss Mechanisms (YLM s( YLM s) Root causes of process related yield loss Each YLM must be characterized in the process with a specific test structure Characterization Vehicle (CV)

18 Typical Die Yield Estimation Die Yield 100% 80% 60% 40% Die Yield Model Area = 2 cm^2 Area = 1.5 cm^2 Area = 1 cm^2 Area = 0.5 cm^2 D A Y = e 0 where, Y = die yield D 0 = mean defects (1/cm 2 ) 20% A = die area (cm 2 ) 0% Mean Defectivity (1/cm^2) Model implies that for a given die size, yield is based only upon process maturity this is not correct Yield is different for different IP content Process defectivity is different for each module

19 Process-Design Interaction Yield 55% 45% 35% 25% Die Content Impact on Yield (~40mm^2 Die Size) Total Yield (130nm) Total Yield (90nm) Ratio << 1.0 Ratio >> 1.0 Memory Logic Memory Logic 15% 5% Memory/Logic Ratio Y = Y MEMORY Y LOGIC Chip Yield is a strong function of design content Physical design features interact with specific module weakness

20 Accurate Process Characterization Metal Opens/Shorts Characterization Vehicle Defect Size Distribution by Process Module Poly and Active Opens/Shorts Characterization Vehicle Defect Density [Defects/cm^2] Defect Size [um] DSD(x) = defect size/count distribution

21 Critical Area/DSD Model Crtical Area (microns^2) 2.00E E E E E E E E E E E+00 Layout Attribute: Critical Area Y Defect Size (microns) Yield Model: = e CA x= 0 () () x DSD x dx Process Model: Defect size Distribution Custom: (Inspection data based) P, D0, x0 based: Defect Density X 0 DSD D0*Ac(p) x k DSD 0 x k = ( x) = D p ( ) ( p p 1 x 1) CA(x) 0

22 Product Design Attributes I/O SRAM ASIC Logic ROM Custom Logic Analog Design Attributes Widths, lengths and spacing Counts Densities Overlaps/enclosures Design Attributes: Physical design properties that interact with specific module marginalities Each attribute can be extracted from physical layout Design attribute extraction (DAE) enables quantification of design content specific YLM models

23 Design Attribute Extraction Contacts/Via Counts N/P Active Poly V1-Vx Critical Area Shorts Sensitivities AA Poly M1-Mx Contact/Via Count Design Attribute Extraction Critical Area Shorts Design Attribute Extraction Count Critical Area [um^2] Contacts and Vias A C (x) = Defect Diameter [um] design attribute sensitivity to x

24 Accurate Process Characterization Layout Metric DOE on litho parameters RSM of layout metric Mask Error Exposure Defocus Misalignment Misalignment Exposure Process Margin Defocus 3.0 σ 0.0 σ 0.5 σ 1.0 σ 1.5 σ 2.0 σ 2.5 σ 0.5 σ 1.0 σ 1.5 σ 2.0 σ 2.5 σ 3.0 σ Yield p(spacing) INPUT: Characterization of litho process statistics Yield Loss Spacing

25 Implicit YLM model: process window effects PSD Analysis Process Margin data from CV layer = NAA doe PSD: condition 1 PSD: condition2 Yield (conf.level = 0.95) NAA_0.11/0.16 NAA_0.115/0.155 NAA_0.12/0.15 NAA_0.125/0.145 NAA_0.13/0.14 NAA_0.135/0.135 PAA_0

26 Yield Simulation Results: Yield Impact Matrix I/O YIMP Matrix Limited Yield SRAM ASIC Logic ROM Custom Logic Analog Design Attributes Widths, lengths and spacing Counts Densities Overlaps/enclosures Random Defects Systematic Failure Mode Full Chip SRAM Active Random 98% 99% 99% Pattern Dependent 99% 99% 100% Total 97% 98% 99% Poly Random 97% 98% 99% Pattern dependent 94% 95% 99% Total 91% 95% 96% Metal Random 97% 98% 99% Pattern dependent 97% 98% 99% Total 94% 95% 99% Holes 97% 98% 99% Total 81% 82% 99% Metal Islands 87% 89% 90% Pattern Density 91% 93% 94% Narrow Space Wide Neighbor 97% 99% 100% Via induced Metal Shorts 77% 78% 79% Total 62% 64% 64% Physical design properties that interact with specific module defectivities Each attribute can be extracted from GDSII Design attribute extraction (DAE) enables quantification of die content specific yield models LOGIC

27 Yield Simulation Accuracy 100% Accuracy of Yield Prediction 4% Yield 80% 60% 40% 20% 2% 0% -2% -4% -6% -8% Absolute Error 0% A B C D E F Product -10% Predicted Actual Abs. Error Yield modeling accuracy is excellent when you characterize right Error represents unidentified yield loss mechanisms or lack of yield model

28 Overview of Layout Design for Manufacturability Critical Area Based Wire Spreading Most useful in Al interconnect era (random metal shorts dominant yield loss mechanism) Contact/via Doubling Effective in reduction yield losses due to random hole opens (Al & Cu) Systematic Yield Model Based Local and Global P&R Layout Modifications Essential for 3-D topography effects due to Cu CMP and low-k interconnect Printability and Performance Variability Driven Layout Generation Absolute must in the Nanometer Era Pro-active (not afterthought in RET)

29 Trade Off Among Yield Loss Mechanisms Layout A Layout B Trade Offs Contact Contact redundancy Poly Poly corner corner rounding rounding Poly Poly contact contact redundancy Poly Poly spacing spacing

30 Parametric Yield Optimization Product Product Blocks Blocks Statistical Statistical Device Device Models Models Parametric Yield Verification Response Surface Modeling (RSM) for accurate parametric yield estimation Circuit Surfer Surfer Process/Design Sensitivity YIELD (% ) OPAMP DIFFERENTIAL PAIR AREA VS. PARAMETRIC YIELD AREA FACTOR Parametric Yield Modeling Design parameter optimization Design Optimization Circuit Surfer maps process and design effects to circuit performances Design or process parameter changes to optimize yield Process window characterization Y Optimized Design Optimized Design Parameters Parameters Verified Parametric Verified Parametric Yield Yield

31 Limited Yield Optimization LY(SRAM) LY(ASIC) LY(I/O) LY(ROM) LY(Custom) LY(Analog) LY GAIN v v ( Yj ) ( Y ) where, j = Random, Systematic, Parametric 1 2 = j j = optimized variant = original variant v v 1 2 Product yields must be optimized by improving LY s LY GAIN ratio of improvement for any specific optimization Prioritizing which LY s to improve requires an understanding of the specific Design Manufacturability Objectives

32 Design Manufacturability Objectives Best Yield Variability Best Average Yield Objectives Average Yield Products DVD, STB, Cell Phone, Digital Cameras # of lots Yield Variability Networking, Graphics, DSP 10 Performance Variability Microprocessors 0 40% 60% 80% 100% Yield Custom Tailored specifically for a process and product Customization of DFM objectives High volume parts in mature process Lower volume parts during ramp

33 Enabling Proactive DFM For Designers Design Flow RTL Design VERIFICATION Hierarchical Floorplan Physical Synthesis DFM Software Yield Simulation and optimization Yield View (.pdfm) Yield Models DFM Optimized Library Module Chip Assembly Sign-off Standard IP Platform Three components to enable Proactive DFM DFM library module Layout attribute dependent yield models (DFM library view) Yield simulation and optimization software

34 DFM Variant Generation Flow DFM Architecture Specifications Average Yield Yield Yield Yield Variability Performance Variability Netlist Netlist Constraint generation Layout Design Cell Cell Layouts Manufacturability Hot Hot Spot Spot Localization MFG MFG Characterization Pruning DFM Library No Hot Hot Spots Spots Minimized? Yes

35 Yield Variants Example High Density Random/Systematic Yield Variant +20% area -50% FR (ppb) Litho hot spots M1 opens +40% area -50% FR (ppb) Yield/Speed Consistency Variant -85% YV (std.dev) M1 shorts

36 Standard Cell Optimization Flow Original Netlist MOS1 d g s b nmos L=0.13u W=1u MOS2 d g s b pmos L=0.13u W=0.8u MOS3 d g s b nmos L=0.13u W=0.7u MOS4 d g s b pmos L=0.13u W=1.2u MOS5 d g s b nmos L=0.13u W=1.3u MOS6 d g s b pmos L=0.13u W=1u 0.2u Cell Architecture Contact redundancy definition Spacing rules definition Transitions rules definition Metal islands definition Taps Hot Spot Analysis Optimized Layout 0.14u 0.16u 0.18u Synthesized Layout Litho Environment Litho Simulated Layout Optimized Layout

37 DFM Library View for EDA DFM Library Module Core Libraries Process Characterization.pdfm view includes relevant data to enable EDA tools to make yield tradeoffs Process Defectivities Design Attributes Yield and Manufacturability Models Design Attribute Extractions Defectivities.pdfm data also enables BEOL routing optimzation Compiler DFM Library View Characteristic Layout Schematic P&R Footprint Performance Logic Function Manufacturability Library View GDSII SPICE Netlist LEF.lib Verilog.pdfm

38 pdfx enabled P&R.PDFM STD.CELL YLM models STD.CELL YLM models BEOL YLM models BEOL YLM models Stat. Gate Models CMP/Litho Models Logic/Physical Synthesis Clock routing Global/ Detailed Routing Timing Sign-off Post-Routing Optimization Include yield in the cost function Take advantage of design slacks Timing convergence properties unchanged

39 And the Silicon Says Fabless Graphics chip Early process lifecycle IDM Graphics Mature process GDPW Improvement (%) IDM Controller chip Mid-process lifecycle Percentage GDPW Improvement 12% 10% 8% 6% 4% 2% 0% A (0.15um) B (0.13um) C (0.13um) D (0.13um) Chip / Technology IDM Cell phone chip Mid process lifecycle E (0.13um) IDM Set top box Mid-process lifecycle Silicon shows up to 12% GDPW improvement by applying our Proactive DFM methodology

40 Looking Into the Future: Extreme Layout Regularity RETs are time-consuming and difficult to optimize for large process windows Defocus, Illumination conditions, Pattern neighborhood Sensitive to grow due to defocus Sensitive to shrink due to defocus Sensitive to exposure variation Sensitive to resist effects Conventional design rules are becoming insufficient to guarantee design s adherence to RETs Increasing need for more geometry regularity by design

41 Regular Logic Bricks Arrays offer advantages for silicon characterization and even inventory, but at a high area penalty Regular Logic Bricks can offer more efficient use of area, and still provide the required regularity Map a simple set of logic primitives onto regular fabric patterns to form logic bricks

42 Some Experimental Results Little area benefit for using more than 10 unique bricks Few unique bricks allows for macro regularity and silicon validation analogous to CLBs and bit cells Trade-off between number of geometry patterns and area/performance Ideally, regular fabric synthesis tool would determine this for each design in an applicationspecific manner Area Estimate Area Estimate Firewire Controller Number of Bricks Koggstone Area Area No. of vias No. of vias Avg. no. of Vias per Brick Avg. no. of Vias per Brick Number of Bricks

43 Ultimate Goal From synthesis we define the set of regular logic bricks that cover the extracted logic modules From the fabrics level, perform shapes-level physicalsynthesis to construct configurable bricks Nano-scale constraints allow us to simplify this shapes-level physical synthesis problem Can be optimized with simulationbased printability modeling Automated layout

44 Full SOC Solution Global effects and system-level issues Memory and logic compatibility Regular BEOL structured routing Analog components Cu thickness distribution Required length, on-grid metal tracks WLAN WCDMA GPS Filler metal tracks