Chapter 5. Address. data. Z80 Computer System Design. Simplified Z80 System Architecture. Memory. program. data. Minimum Z80 Computer System

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Simplified System Architecture I/O Port Address Addr 00 Addr Chapter Computer System Design FF I/O Port Decoder IORQ data MEMRQ Address Decoder program data FFFF Minimum Computer System Minimum

1 Simplified System Architecture I/O Port Address Addr 00 Addr Chapter Computer System Design FF I/O Port Decoder IORQ data MEMRQ Address Decoder program data FFFF Minimum Computer System Minimum Computer System Consisting of, Oscillator,, I/O Additional is preferred Total starting cost for DIY ~00 THB Complete and ready to use board ~,000 THB + + (Socket) + I/O Controller + Oscillator System extension via system bus connector

2 Main memory Stores programs Provides data to the MPU Accepts result from the MPU for storage Main memory Types : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) : random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values Read-Only () µp can read instructions from quickly Cannot write new data to stores data, even after power cycled When power is turned on, the microprocessor will start fetching instructions from (bootstrap ) Available s Masked or just P or programmable (one-time programmable) EP (Erasable/Programmable ) Ultra Violet (UV) light is used in erasing process Flash re-writable about,000 times usually must write a whole block not just or bytes, slow writing fast reading EEP (electrically erasable ) fast writing slow reading can program millions of times useless for storing a program good for save configuration information. Capacity : m+ m+ bit Address : Output Enable connect to of µp () Am : Enable to Address decoder m+ ( n+ ) P EEP D0 D D Dn n+ bit Data

3 Read Timing EP U -Am D0-Dn 0 U A A A A A A VPP O0 O O O O O O O 0 U A A A A A A /VPP O0 O O O O O O O 0 A A A A A A PGM VPP O0 O O O O O O O it kbyte kbit kbyte kbit kbyte falls to data valid * Defined by manufacturer * Addr valid to data valid PGM and VPP are used to programming EP (Random Access ) 0 U A A A A A A PGM VPP D0 D D D D D D D 0 U A A A A A A VPP D0 D D D D D D D 0 U A A A A A A /VPP VCC O0 O O O O O O O U A A A A A A PGM VPP D0 D D D D D D D 0 µp can read the data from quickly µp can write new data to quickly is unable to store data if power is turned off Two type is available : Static (S): FF base, fast, expensive, low cap/vol, applied for cache, no refresh Dynamic (D): capacitor base, slow, low cost high capacity/volume, applied for main memory(pc) need refresh. kbit yte kbit kbyte kbit kbyte 0 kbit kbyte

Capacity : m+ m+ bit Address (Static) Am : Read signal connect to Mem of µp : Write signal connect to Mem of µp : Select to Address decoder m+ ( n+ ) D0 D D Dn n+ bit Data Data bus is Bidirectional

4 Capacity : m+ m+ bit Address (Static) Am : Read signal connect to Mem of µp : Write signal connect to Mem of µp : Select to Address decoder m+ ( n+ ) D0 D D Dn n+ bit Data Data bus is Bidirectional Static Dynamic Dynamic Write : Charge bit line HIGH or LOW and set word line HIGH Read : Bit line is precharged to a voltage halfway between HIGH and LOW and then the word line is set HIGH. Sense Amp Detects change Reads are destructive (Must follow with a write) Address Buffer

5 connection connection (cont.) bit address bus k memory(max) bit data bus bit data width Generally should be connected Data to data Address to address to wr to rd to cs If only one chip with Full size ( kb capacity) ~ ~ kb connection (cont.) If capacity is kb is combined with address is from h to ~ ~ kb connection (cont.) Given two K chips, how to obtain full K address? Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution: Use address line as an arbiter. If outputs a logic the upper memory is enabled (and the lower memory is disabled) and vice-versa.

6 connection (cont.) There are two K applied to select one chip Two area is from h to and 000h to connection (cont.) K and K doesn t have signal ~ ~ kb ~ kb ~ ~ kb ~ kb connection (cont.) Address Bit Map There are memory chip and are applied to chip selection # # # to (HE) Selects chip AA AA Selects location within chips h h 0 00 En S0 S 00

7 Map Map Represents the memory type Address area of each memory chip Empty area En S0 S # # # h 000h k k k k Empty area is neither writable nor readable Read op. returns FFh value (usualy) Write op. can t store any value on it En S0 S # # h 000h Empty Map Full and Partial Decoding Empty area is neither writable nor readable Read op. returns FFh value (usualy) h Write op. can t store any value on it En S0 S # 000h Empty Empty Full (exhaust) Decoding All of the address lines are connected to any memory/device to perform selection Absolute address : any memory location has one address Partial Decoding When some of the address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses (fold back or shading). roll-over address : any memory location has more than one address

8 Partial Decoding Partial Decoding ~ are not connected What is the memory map? ~ ~ kb Every memory location has more than one address For example first location has addresses: h 00h 000h 000h Roll-over Address.. F000h h 0FFFh 00h FFFh 000h FFFh 000h F000h ~ to (HE) 000h FFFh xxxx xxxx ~ ~ kb ~ Partial Decoding Partial Decoding only connected to has no connection What is the memory map? roll-over address for roll-over address for ~ kb kb kb ~ kb 0x0 0x Memor y

9 Partial Decoding k 0x0 0x k E000h DFFFh 00h F000h 000h FFFh 000h 000h FFFh 000h 000h FFFh FFFh FFFh 000h 000h FFFh 000h 00h FFFh h 0FFFh h FFFh kb ~ kb Conflict Partial Decoding k x0 x k E000h DFFFh 00h F000h 000h FFFh 000h 000h FFFh 000h 000h FFFh FFFh FFFh 000h 000h FFFh 000h 00h FFFh h 0FFFh h FFFh kb ~ kb Conflict Full (exhaustive) decoding Y0 Y Y Y Y Y Y Y C B A GA GB G EP k RWM k A~ A~ h-0ffh 000h-0FFFh 00h-FFh 00h-FFFh 000h-FFh Partial decoding Y0 Y Y Y Y Y Y Y C B A GA GB G EP k RWM k A~ A~ h-fffh 000h- x000 x 00x 00x 000 GND VCC

10 Timing (revisited) The executes instructions by stepping through a precise set of basic operations. These include: Read or Write I/O Device Read or Write Interrupt Acknowledge Three to six clock periods are required to complete each operations Number of clocks used in each operation can be extended to synchronize the to the speed of external devices. Timing (revisited) Opcode Fetch WAIT signal can be asserted to extend the M cycle Timing (revisited) Wait State WAIT signal is sampled at the falling edge of T If it is asserted, wait state (Tw) is inserted until WAIT signal is removed Timing (revisited) Read T W * is inserted if WAIT is asserted

11 Timing (revisited) Write * T W is inserted if WAIT is asserted Adding One Wait State to an M Cycle is a way of holding onto the things you love, the things you are, the things you never want to lose. ~From the television show The Wonder Years

University of Kashan Faculty of Electrical and Computer Engineering Department of Computer Engineering. Lecture note 2

University of Kashan Faculty of Electrical and Computer Engineering Department of Computer Engineering Lecture note 2 Memory and IO Interfacing to & An Introduction to AVR Microcontrollers Hossein Sabaghian-Bidgoli