Exploring the Viability of the Cell Broadband Engine for Bioinformatics Applications

Size: px
Start display at page:

Download "Exploring the Viability of the Cell Broadband Engine for Bioinformatics Applications"

Transcription

1 Explring the Viability f the Cell Bradband Engine fr Biinfrmatics Applicatins Authrs: Vipin Sachdeva, Michael Kistler, Evan Speight and Tzy-Hwa Kathy Tzeng Presentatin by: Keyur Malaviya Dept f Cmputer & Infrmatin Sciences University f Delaware

2 Overview Prblem: Genmic data/cmputatinal requirements grwing General-purpse prcessrs cannt handle this Apprach: Parallelize & prt existing applicatins t multicre Use multicre architecture like Cell (PS3) Steps: Pick applicatins, Perfrm prfiling Make necessary cde changes fr prting Publish results Gal: Validate perfrmance gain n PS3

3 Biinfrmatics Quick Intr Terminlgy: Gemnes DNA strand Prteins A typical prblem: Machine learning, Predictin, Data mining Supprt vectr based, HMM, Clustered Few examples: Determine bilgical functins f prteins Understand bichemical pathways Assemble strings t make Genme Apprach: Cmpare sequence data with knwn genmes

4 Experimental Setup Tw applicatins selected 1) Sequence alignment : FASTA (ssearch34) Smith-Waterman algrithm [ O(nm) ] Pairwise alignment f gene sequences Uses dynamic prgramming algrithm 2) Hmlgy detectin: ClustalW(clustalw) Multiple sequence alignment

5 Sequence alignment basics Pairwise alignment: Mst cmmnly perfrmed tasks in biinfrmatics T align tw sequences: i. Alignment scre Matrix (e.g: Blssm, PAM) ii. Cmparing them, assign scres iii. Insert gaps in ne r bth sequences iv. Traceback Dynamic prgramming table t Prduce an ptimal scre

6 Sequence alignment basics T align tw sequences: Alignment scre Matrix (e.g: Blssm, PAM) Cmparing them, assign scres Insert gaps in ne r bth sequences Traceback & prduce an ptimal scre Tw sequences: Scring table Aligned Sequences:

7 ClustalW basics In three steps: i. All sequences are cmpared pairwise (Smith- Waterman algrithm) ii. iii. Create a hierarchy fr alignment (guide tree) by cluster analysis (distance matrix) fr each pair Prgressive add ne sequence accrding t the guide tree t get multiple sequence alignment

8 ClustalW: Multiple seq alignment.. Guided tree r Phylgenetic tree

9 Applicatins characteristics Embarrassingly parallel cmputatin Small critical time-cnsuming cde size Regular memry accesses Vectrized cde

10 Perfrm prfiling (gprf) Mre than half the executin time is taken by a single functin: FASTA: drpgsw ClustalW: frward pass HMMER: P7Viterbi Figure: Executin prfile frm gprf fr three applicatins & the BLASTapp.

11 Prting t Cell Architecture Altivec: is a PwerPC frm AIM alliance Altivec SSE implementatins: drpgsw fr FASTA and P7Viterbi fr HMMER IBM Life Sciences: Vectrized kernel fr frward_pass f ClustalW Prted with few mdificatins t CELL

12 Prting t Cell Architecture Advantage n CELL: Used 9 cres: PPU als as a prcessing element Cmpilatin f prgrams: Fr CELL: XLC v8.1 with -O3 PwerPC G5: -O3 -mcpu=g5 -mtune=g5 Optern & Wdcrest: -O3

13 FASTA (Smith-waterman) n CELL FASTA package includes Altivec-enabled Smith- Waterman Smith_waterman_altivec_wrd kernal was prted with simple changes t CELL Altivec APIs: vec_max, vec_subs were written fr SPUs Pairwise alignment f 8 pairs f sequences, using ne SPU fr each pairwise alignment Limitatin in current implementatin: Size f bth sequences <= SPU lcal stre (256 KB) Sequence size <= 2048 characters

14 Lng sequence cmparisns: T d genme-wide r lng sequence cmparisns: Implement pipelined apprach amng SPUs Each SPU perfrms Smith-Waterman alignment fr a blck, ntifies the next SPU thrugh a mailbx message Later SPU uses bundary results f previus SPU fr its wn blck cmputatin Future research: Supprt f bigger sequences n the Cell

15 Perfrmance f Smith- Waterman Alignment executin time fr different prcessrs: 1: Sequence length = : Sequence length = 2048

16 Prting ClustalW n CELL pairalign functin: All-t-all pairwise cmparisns fr n sequences perfrms n(n 1)/2 alignments Takes 60%-80% f the executin time pairalign functin is made f 4 functins 1) Frward_pass cmputes the maximum scre and is the mst time-cnsuming step f pairalign

17 Applicatin s Architecture Input t ClustalW: n sequences in a query sequence file n(n 1)/2 cmputatins Mfc DMA in/ut frm 16-byte bundaries: Pack all sequences in a single array Each sequence begin at a multiple f 16- bytes

18 Applicatin s Architecture PPU creates threads, passes max sequence size SPUs wait fr PPU t send a message t pull in the cntext data & begin cmputatin Wrk distributin Rund-rbin strategy: Each SPU is assigned a number frm 0 t 7 if i md 8=k SPU k cmpares seq n. i against all sequences i+1 t n [ i=9 => k=0 ] [i=15 => k=7] [ s n ]

19 Issues in prting ClustalW and bttlenecks IBM Life Sciences vectrized versin f frward_pass Altivec APIs: vec_max, vec_adds written fr SPUs SPUs dn t supprt 16-bit: Altivec used vectr status & cntrl register t detect verflw n it SPU use f 32-bit (int) lwers vectr cmputing efficiency (nly 4 values can be packed in a vectr) SPU has nly vectr registers: Reading Alignment matrix scre a scalar peratin suffers n SPU

20 Issues in prting ClustalW and bttlenecks SPUs nly have static branch predictin: Fails n a branch with multiple cnditins r Mre lp variables handling bundary cases Such branches are difficult t predict fr the SPU Slutin: Make branch depend n a single lp variable Break inner alignment lp int several lps Explicit handling f bundary cases 2X perfrmance gains

21 Cde changes behavir Imprvement f perfrmance f ClustalW alignment functin with different cde changes. Best implementatin: Using integer datatypes with n branches

22 Perfrmance f frward_pass (ClustalW) Cmparisn f Cell Perfrmance with ther prcessrs fr nly alignment functin with simple rund-rbin strategy Tw inputs frm BiPerf suite: 1) 1290.seq has 66 sequences f average length ) 6000.seq has 318 sequences f average length 1043 NOTE: Optern and the Wdcrest perfrmance is nn-vectrized

23 Perfrmance f ClustalW Cmparisn f Cell Perfrmance with ther prcessrs fr ttal time f executin Tw inputs frm BiPerf suite: 1) 1290.seq has 66 sequences f average length ) 6000.seq has 318 sequences f average length 1043 NOTE: Optern and the Wdcrest perfrmance is nn-vectrized

24 Cmputing the final alignment Perfrmance gain in Frward_pass Final step executing n PPU is much slwer cmpared t ther superscalar prcessrs Tw appraches t this prblem: Execute mre cde n the SPUs, r Use Cell as an acceleratr, alng with a superscalar prcessr Future wrk: Increasing PPU perfrmance (RadRunner prject is explring such hybrid architectures)

25 PPU penalty: Cell perfrmance is marginally better in verall executin time due t perfrmance f the PPU Frward_pass Frward_pass: Cell (8 SPUs) 7.5 times t Pwer G5 Overall: Cell (8 SPUs) 1.2 times t Pwer G5

26 Current prgress in prting Many biinfrmatics applicatins are being prted t the Cell prcessr 2500 playstatins used t parallelize gene-finding and sequence alignment sftwares Prtein flding n distributed cmputing and GPUs Charm++ runtime system, used fr NAMD simulatins FASTA, ClustalW, and HMMER

27 Cnclusins & Future Wrk Cell s ttal pwer cnsumptin < half f a superscalar prcessr Cell is price & pwer-efficient platfrm fr future biinfrmatics cmputing Future Wrk: Remving limitatins & increasing ptimizatin Prting HMMER t Cell prcessr Handling size that exceeds 256 KB Use f partitining input amng 8 SPUs Prting prtein dcking, RNA interference, medical imaging and few mre applicatins

28 QUESTIONS

B Tech Project First Stage Report on

B Tech Project First Stage Report on B Tech Prject First Stage Reprt n GPU Based Image Prcessing Submitted by Sumit Shekhar (05007028) Under the guidance f Prf Subhasis Chaudhari 1. Intrductin 1.1 Graphic Prcessr Units A graphic prcessr unit

More information

Parallel Processing in NCAR Command Language for Performance Improvement

Parallel Processing in NCAR Command Language for Performance Improvement Parallel Prcessing in NCAR Cmmand Language fr Perfrmance Imprvement Ping Gu, University f Wyming Mentr: Wei Huang, NCAR C- Mentr: Dave Brwn, NCAR August 1, 2013 Intrductin and Mtivatin ² The NCAR Cmmand

More information

Operating systems. Module 7 IPC (Interprocess communication) PART I. Tami Sorgente 1

Operating systems. Module 7 IPC (Interprocess communication) PART I. Tami Sorgente 1 Operating systems Mdule 7 IPC (Interprcess cmmunicatin) PART I Tami Srgente 1 INTERPROCESS COMMUNICATION Prcesses within a system may be independent r cperating Cperating prcess can affect r be affected

More information

SW-G using new DryadLINQ(Argentia)

SW-G using new DryadLINQ(Argentia) SW-G using new DryadLINQ(Argentia) DRYADLINQ: Dryad is a high-perfrmance, general-purpse distributed cmputing engine that is designed t manage executin f large-scale applicatins n varius cluster technlgies,

More information

NVIDIA Tesla K20X GPU Accelerator. Breton Minnehan, Beau Sattora

NVIDIA Tesla K20X GPU Accelerator. Breton Minnehan, Beau Sattora NVIDIA Tesla K20X GPU Acceleratr Bretn Minnehan, Beau Sattra Overview Jb f the GPU Histry What is the K20X GK110 Benchmark Perfrmance Jb f the GPU Vertex Shader Applies transfrms n each vertex Applies

More information

MICRO Graphicionado. A High-Performance and Energy-Efficient Graph Analytics Accelerator

MICRO Graphicionado. A High-Performance and Energy-Efficient Graph Analytics Accelerator MICRO 2016 Graphicinad A High-Perfrmance and Energy-Efficient Graph Analytics Acceleratr Tae Jun Ham Lisa Wu Narayanan Sundaram Nadathur Satish Margaret Martnsi Slide: http://tiny.cc/graphicinad Graph

More information

NQueens Problem with CUDA

NQueens Problem with CUDA NQueens Prblem with CUDA Shuqing Chen (21760448) [MAP] [S.Chen] [NQueens Prblem with CUDA] Table f Cntents Backgrund Apprach Evaluatin Discussin Cnclusin [MAP] [S.Chen] [NQueens Prblem with CUDA] Backgrund

More information

It has hardware. It has application software.

It has hardware. It has application software. Q.1 What is System? Explain with an example A system is an arrangement in which all its unit assemble wrk tgether accrding t a set f rules. It can als be defined as a way f wrking, rganizing r ding ne

More information

Dynamic Instruction Reuse

Dynamic Instruction Reuse Dynamic Instructin Reuse Guri Shi Cmputer Sciences Department University f Wiscnsin Madisn 1 Mtivatin Prgrams cnsist f static instructins Executin sees static instructin many times - ften with same inputs

More information

Executing Parallelized Dictionary Attacks on CPUs and GPUs

Executing Parallelized Dictionary Attacks on CPUs and GPUs Executing Parallelized Dictinary Attacks n CPUs GPUs Hassan Alnn ENSIMAG Grenble, France hassan.alnn@ensimag.imag.fr Shaima Al Awadi ENSIMAG Grenble, France shayma.al-awadi@ensimag.imag.fr ABSTRACT This

More information

Extensible Query Processing in Starburst

Extensible Query Processing in Starburst Extensible Query Prcessing in Starburst Laura M. Haas, J.C. Freytag, G.M. Lhman, and H.Pirahesh IBM Almaden Research Center CS848 Instructr: David Tman Presented By Yunpeng James Liu Outline Intrductin

More information

CS4500/5500 Operating Systems Synchronization

CS4500/5500 Operating Systems Synchronization Operating Systems Synchrnizatin Yanyan Zhuang Department f Cmputer Science http://www.cs.uccs.edu/~yzhuang UC. Clrad Springs Recap f the Last Class Multiprcessr scheduling Tw implementatins f the ready

More information

NVIDIA S KEPLER ARCHITECTURE. Tony Chen 2015

NVIDIA S KEPLER ARCHITECTURE. Tony Chen 2015 NVIDIA S KEPLER ARCHITECTURE Tny Chen 2015 Overview 1. Fermi 2. Kepler a. SMX Architecture b. Memry Hierarchy c. Features 3. Imprvements 4. Cnclusin 5. Brief verlk int Maxwell Fermi ~2010 40 nm TSMC (sme

More information

Because this underlying hardware is dedicated to processing graphics commands, OpenGL drawing is typically very fast.

Because this underlying hardware is dedicated to processing graphics commands, OpenGL drawing is typically very fast. The Open Graphics Library (OpenGL) is used fr visualizing 2D and 3D data. It is a multipurpse pen-standard graphics library that supprts applicatins fr 2D and 3D digital cntent creatin, mechanical and

More information

Computer Organization and Architecture

Computer Organization and Architecture Campus de Gualtar 4710-057 Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW.

More information

Memory Hierarchy. Goal of a memory hierarchy. Typical numbers. Processor-Memory Performance Gap. Principle of locality. Caches

Memory Hierarchy. Goal of a memory hierarchy. Typical numbers. Processor-Memory Performance Gap. Principle of locality. Caches Memry Hierarchy Gal f a memry hierarchy Memry: hierarchy f cmpnents f varius speeds and capacities Hierarchy driven by cst and perfrmance In early days Primary memry = main memry Secndary memry = disks

More information

Greg Dias, Alex Wilson. Fermi

Greg Dias, Alex Wilson. Fermi Greg Dias, Alex Wilsn Fermi Agenda Cmputer Graphics and Parallelism Basic GPU structure NVIDIA Fermi and CUDA Graphics Rendering Methds Plygn Rendering Ray Tracing Plygn Rendering Apprximatin f cmplex

More information

Computer Organization and Architecture

Computer Organization and Architecture Campus de Gualtar 4710-057 Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW.

More information

Year 4 and After Fielded HPC Multi- and Many-core-based Systems

Year 4 and After Fielded HPC Multi- and Many-core-based Systems Year 4 and After Fielded HPC Multi- and Many-cre-based Systems Mtivatin: Accelerate infusin f new technlgies int n-bard and field-deplyable systems Increase cmputatinal capabilities Speed-up applicatin

More information

On the road again. The network layer. Data and control planes. Router forwarding tables. The network layer data plane. CS242 Computer Networks

On the road again. The network layer. Data and control planes. Router forwarding tables. The network layer data plane. CS242 Computer Networks On the rad again The netwrk layer data plane CS242 Cmputer Netwrks The netwrk layer The transprt layer is respnsible fr applicatin t applicatin transprt. The netwrk layer is respnsible fr hst t hst transprt.

More information

CS4500/5500 Operating Systems Page Replacement Algorithms and Segmentation

CS4500/5500 Operating Systems Page Replacement Algorithms and Segmentation Operating Systems Page Replacement Algrithms and Segmentatin Yanyan Zhuang Department f Cmputer Science http://www.cs.uccs.edu/~yzhuang UC. Clrad Springs Ref. MOSE, OS@Austin, Clumbia, Rchester Recap f

More information

Presentation of Results Experiment:

Presentation of Results Experiment: Presentatin f Results Experiment: Metrics & CdePr AnalytiX Grup 6: Brun Cards Felipe César Tarcísi Filó William Marcndes Empirical Sftware Engineering - 2014/1 Intrductin Sftware Measure is imprtant: Evaluate

More information

- Replacement of a single statement with a sequence of statements(promotes regularity)

- Replacement of a single statement with a sequence of statements(promotes regularity) ALGOL - Java and C built using ALGOL 60 - Simple and cncise and elegance - Universal - Clse as pssible t mathematical ntatin - Language can describe the algrithms - Mechanically translatable t machine

More information

Speculative Parallelization. Devarshi Ghoshal

Speculative Parallelization. Devarshi Ghoshal Speculative Parallelizatin Devarshi Ghshal Indiana University, Blmingtn 10/10/2011 1 Agenda Speculative Parallelizatin FastFrward-A Speculatin using Checkpint/Restart System Design Sftware-based Speculatin

More information

Due Date: Lab report is due on Mar 6 (PRA 01) or Mar 7 (PRA 02)

Due Date: Lab report is due on Mar 6 (PRA 01) or Mar 7 (PRA 02) Lab 3 Packet Scheduling Due Date: Lab reprt is due n Mar 6 (PRA 01) r Mar 7 (PRA 02) Teams: This lab may be cmpleted in teams f 2 students (Teams f three r mre are nt permitted. All members receive the

More information

CS510 Concurrent Systems Class 2. A Lock-Free Multiprocessor OS Kernel

CS510 Concurrent Systems Class 2. A Lock-Free Multiprocessor OS Kernel CS510 Cncurrent Systems Class 2 A Lck-Free Multiprcessr OS Kernel The Synthesis kernel A research prject at Clumbia University Synthesis V.0 ( 68020 Uniprcessr (Mtrla N virtual memry 1991 - Synthesis V.1

More information

Analysing Big Data with Microsoft R

Analysing Big Data with Microsoft R Analysing Big Data with Micrsft R Analysing Big Data with Micrsft R Curse Cde: 20773 Certificatin Exam: 70-773 Duratin: 3 Days Certificatin Track: MCSA: Machine Learning Frmat: Classrm Level: 300 Abut

More information

UNIT-II INTRODUCTION TO EMBEDDED SYSTEMS

UNIT-II INTRODUCTION TO EMBEDDED SYSTEMS UNIT-II INTRODUCTION TO EMBEDDED SYSTEMS Embedded System: Def: An Embedded system is ne that has cmputer hardware with sftware embedded in it as ne f its mst imprtant cmpnent. The three main cmpnents f

More information

Operating systems. Module 15 kernel I/O subsystem. Tami Sorgente 1

Operating systems. Module 15 kernel I/O subsystem. Tami Sorgente 1 Operating systems Mdule 15 kernel I/O subsystem Tami Srgente 1 SWAP SPACE MANAGEMENT Swap space can be defined as a temprary strage lcatin that is used when system s memry requirements exceed the size

More information

Admin Report Kit for Exchange Server

Admin Report Kit for Exchange Server Admin Reprt Kit fr Exchange Server Reprting tl fr Micrsft Exchange Server Prduct Overview Admin Reprt Kit fr Exchange Server (ARKES) is an Exchange Server Management and Reprting slutin that addresses

More information

Common Language Runtime

Common Language Runtime Intrductin t.net framewrk.net is a general-purpse sftware develpment platfrm, similar t Java. Micrsft intrduced.net with purpse f bridging gap between different applicatins..net framewrk aims at cmbining

More information

Xilinx Answer Xilinx PCI Express DMA Drivers and Software Guide

Xilinx Answer Xilinx PCI Express DMA Drivers and Software Guide Xilinx Answer 65444 Xilinx PCI Express DMA Drivers and Sftware Guide Imprtant Nte: This dwnladable PDF f an Answer Recrd is prvided t enhance its usability and readability. It is imprtant t nte that Answer

More information

Hierarchical Classification of Amazon Products

Hierarchical Classification of Amazon Products Hierarchical Classificatin f Amazn Prducts Bin Wang Stanfrd University, bwang4@stanfrd.edu Shaming Feng Stanfrd University, superfsm@ stanfrd.edu Abstract - This prjects prpsed a hierarchical classificatin

More information

ECE 545 Project Deliverables

ECE 545 Project Deliverables Tp-level flder: _ Secnd-level flders: 1_assumptins 2_blck_diagrams 3_interface 4_ASM_charts 5_surce_cdes 6_verificatin 7_timing_analysis 8_results 9_benchmarking 10_bug_reprts

More information

KIRA-EMTA. Why KIRA-EMTA Multi-Threaded Supercomputer. Inside KIRA-EMTA. Elastic Supercomputing Architecture. Exa-Converged Architecture

KIRA-EMTA. Why KIRA-EMTA Multi-Threaded Supercomputer. Inside KIRA-EMTA. Elastic Supercomputing Architecture. Exa-Converged Architecture Explring New Supercmputer Perfrmance Scenaris Fr New Emerging Applicatins Why KIRA-EMTA Multi-Threaded Supercmputer The A3Cube KIRA-EMTA supercmputer realizes an adaptive supercmputing architecture that

More information

UFuRT: A Work-Centered Framework and Process for Design and Evaluation of Information Systems

UFuRT: A Work-Centered Framework and Process for Design and Evaluation of Information Systems In: Prceedings f HCI Internatinal 2007 UFuRT: A Wrk-Centered Framewrk and Prcess fr Design and Evaluatin f Infrmatin Systems Jiajie Zhang 1, Keith A. Butler 2 1 University f Texas at Hustn, 7000 Fannin,

More information

Elasticity : Advanced Cloud Computing. Garth Gibson Greg Ganger Majd Sakr. Feb 6, Adv. Cloud Computing 1

Elasticity : Advanced Cloud Computing. Garth Gibson Greg Ganger Majd Sakr. Feb 6, Adv. Cloud Computing 1 Elasticity 15-719: Advanced Clud Cmputing Garth Gibsn Greg Ganger Majd Sakr Feb 6, 2017 15719 Adv. Clud Cmputing 1 Advanced Clud Cmputing Elasticity Readings Req d Ref 1: Dynamically Scaling Applicatins

More information

Parallel error-correcting output codes classification in volume visualization: parallelism for AI and AI for parallelism

Parallel error-correcting output codes classification in volume visualization: parallelism for AI and AI for parallelism Parallel errr-crrecting utput cdes classificatin in vlume visualizatin: parallelism fr AI and AI fr parallelism Oscar Amrós Huguet Advisrs: Sergi Escalera, Anna Puig UPC-UB-URV Intrductin Main Gal: explre

More information

CSE 3320 Operating Systems Page Replacement Algorithms and Segmentation Jia Rao

CSE 3320 Operating Systems Page Replacement Algorithms and Segmentation Jia Rao CSE 0 Operating Systems Page Replacement Algrithms and Segmentatin Jia Ra Department f Cmputer Science and Engineering http://ranger.uta.edu/~jra Recap f last Class Virtual memry Memry verlad What if the

More information

CS4500/5500 Operating Systems Computer and Operating Systems Overview

CS4500/5500 Operating Systems Computer and Operating Systems Overview Operating Systems Cmputer and Operating Systems Overview Yanyan Zhuang Department f Cmputer Science http://www.cs.uccs.edu/~yzhuang UC. Clrad Springs Ref. MOS4E, OS@Austin, Clumbia, UWisc Overview Recap

More information

Qlucore Omics Explorer 3.3 feature overview

Qlucore Omics Explorer 3.3 feature overview Qlucre Omics Explrer 3.3 feature verview INTRODUCTION Qlucre Omics Explrer (QOE) is develped t supprt the user with fast, simple and visual analysis f measured data cnsidering publicly available infrmatin

More information

Tekmos. TK68020 Microprocessor. Features. General Description. 9/03/14 1

Tekmos. TK68020 Microprocessor. Features. General Description. 9/03/14   1 Tekms TK68020 Micrprcessr September 3, 2014 Prduct Overview Features Addressing Mde Extensins fr Enhanced Supprt f High-Level Languages Object-Cde Cmpatible with Earlier M68000 Micrprcessrs Addressing

More information

CS 309: Autonomous Intelligent Robotics. Instructor: Jivko Sinapov

CS 309: Autonomous Intelligent Robotics. Instructor: Jivko Sinapov CS 309: Autnmus Intelligent Rbtics Instructr: Jivk Sinapv http://www.cs.uteas.edu/~jsinapv/teaching/cs309_spring2017/ Machine Learning Annuncements Final Prject Presentatins Saturday, May 13, 7:00-10:00

More information

Using SPLAY Tree s for state-full packet classification

Using SPLAY Tree s for state-full packet classification Curse Prject Using SPLAY Tree s fr state-full packet classificatin 1- What is a Splay Tree? These ntes discuss the splay tree, a frm f self-adjusting search tree in which the amrtized time fr an access,

More information

CSE 3320 Operating Systems Synchronization Jia Rao

CSE 3320 Operating Systems Synchronization Jia Rao CSE 3320 Operating Systems Synchrnizatin Jia Ra Department f Cmputer Science and Engineering http://ranger.uta.edu/~jra Recap f the Last Class Multiprcessr scheduling Tw implementatins f the ready queue

More information

ARM Programmer s Model

ARM Programmer s Model ARM Prgrammer s Mdel Hsung-Pin Chang Department f Cmputer Science Natinal Chung Hsing University PDF created with FinePrint pdffactry Pr trial versin www.pdffactry.cm Outline ARM Data Types ARM Prcessr

More information

Infrastructure Series

Infrastructure Series Infrastructure Series TechDc WebSphere Message Brker / IBM Integratin Bus Parallel Prcessing (Aggregatin) (Message Flw Develpment) February 2015 Authr(s): - IBM Message Brker - Develpment Parallel Prcessing

More information

An Introduction to Crescendo s Maestro Application Delivery Platform

An Introduction to Crescendo s Maestro Application Delivery Platform An Intrductin t Crescend s Maestr Applicatin Delivery Platfrm Intrductin This dcument is intended t serve as a shrt intrductin t Crescend s Maestr Platfrm and its cre features/benefits. The dcument will

More information

Contents: Module. Objectives. Lesson 1: Lesson 2: appropriately. As benefit of good. with almost any planning. it places on the.

Contents: Module. Objectives. Lesson 1: Lesson 2: appropriately. As benefit of good. with almost any planning. it places on the. 1 f 22 26/09/2016 15:58 Mdule Cnsideratins Cntents: Lessn 1: Lessn 2: Mdule Befre yu start with almst any planning. apprpriately. As benefit f gd T appreciate architecture. it places n the understanding

More information

Verigy V93000 HSM HSM3G

Verigy V93000 HSM HSM3G Verigy V93000 HSM HSM3G Prduct Overview Industry Challenges High-end wrkstatin, desktp and laptp PCs, cmputer servers, perfrmance graphics cards, dynamic game cnsles, high-end vide/hdtv, cmputer netwrking

More information

Computer Organization and Architecture

Computer Organization and Architecture Campus de Gualtar 4710-057 Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW.

More information

CIM System Virtualization Model

CIM System Virtualization Model DMTF Server Management Wrking Grup CIM System Virtualizatin Mdel Steve Hand DMTF System Virtualizatin Partitining and Clustering Wrkgrup (SVPC) Symantec Thanks t Rn Gering, C-Chair SVPC, Distinguished

More information

Datacenter Traffic Measurement and Classification

Datacenter Traffic Measurement and Classification Datacenter Traffic Measurement and Classificatin Speaker: Lin Wang Research Advisr: Biswanath Mukherjee Grup meeting 6/15/2017 Datacenter Traffic Measurement and Analysis Data Cllectin Cllect netwrk events

More information

MediaTek LinkIt Development Platform for RTOS Memory Layout Developer's Guide

MediaTek LinkIt Development Platform for RTOS Memory Layout Developer's Guide MediaTek LinkIt Develpment Platfrm fr RTOS Memry Layut Develper's Guide Versin: 1.1 Release date: 31 March 2016 2015-2016 MediaTek Inc. MediaTek cannt grant yu permissin fr any material that is wned by

More information

Data reduction in the ITMS system through a data acquisition model with self-adaptive sampling rate

Data reduction in the ITMS system through a data acquisition model with self-adaptive sampling rate Data reductin in the ITMS system thrugh a data acquisitin mdel with self-adaptive sampling rate M. Ruiz, JM. Lpez, G. de Areas, E. Barrera, R. Melendez, J. Vega Grup de Investigatin en Instrumentatin y

More information

2. When logging is used, which severity level indicates that a device is unusable?

2. When logging is used, which severity level indicates that a device is unusable? CCNA 4 Chapter 8 v5.0 Exam Answers 2015 (100%) 1. What are the mst cmmn syslg messages? thse that ccur when a packet matches a parameter cnditin in an access cntrl list link up and link dwn messages utput

More information

Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand

Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand Illusinist: Transfrming s int Aggressive s n Demand Amin Ansari 1, Shuguang Feng 2, Shantanu Gupta 3, Jsep Trrellas 1, and Sctt Mahlke 4 1 University f Illinis, Urbana-Champaign 2 Nrthrp Grumman Crp. 3

More information

Low-Cost Solutions for Video Compression Systems

Low-Cost Solutions for Video Compression Systems Overview Lw-Cst Slutins fr Cmpressin Systems Brian Jentz Altera Crpratin 101 Innvatin Drive San Jse, CA 9505, USA (08) 5-7709 bjentz@altera.cm Many device applicatins utilize vide cmpressin t reduce the

More information

These tasks can now be performed by a special program called FTP clients.

These tasks can now be performed by a special program called FTP clients. FTP Cmmander FAQ: Intrductin FTP (File Transfer Prtcl) was first used in Unix systems a lng time ag t cpy and mve shared files. With the develpment f the Internet, FTP became widely used t uplad and dwnlad

More information

Profiling & Debugging

Profiling & Debugging Prfiling & Debugging CISC 879 Tristan Vanderbruggen & Jhn Cavazs Dept f Cmputer & Infrmatin Sciences University f Delaware 1 Lecture Overview Prfiling and Debugging Why? Tls Data sets Race Cnditin and

More information

CSE 3320 Operating Systems Computer and Operating Systems Overview Jia Rao

CSE 3320 Operating Systems Computer and Operating Systems Overview Jia Rao CSE 3320 Operating Systems Cmputer and Operating Systems Overview Jia Ra Department f Cmputer Science and Engineering http://ranger.uta.edu/~jra Overview Recap f last class What is an perating system?

More information

NIST Fingerprint Image Quality. Elham Tabassi Biometric Consortium Conference September 20, 2005

NIST Fingerprint Image Quality. Elham Tabassi Biometric Consortium Conference September 20, 2005 NIST Fingerprint Image Quality Elham Tabassi Bimetric Cnsrtium Cnference September 20, 2005 backgrund quality is imprtant previus research mstly defined as a measure f the extractability f the features

More information

WLAN Interoperability Testing with Expert Analysis

WLAN Interoperability Testing with Expert Analysis WLAN Interperability Testing with Expert Analysis Highlights Tests interperability and perfrmance f real WLAN client device with access pints Prvides data plane perfrmance f IEEE 802.11a/b/g/n/ac ver time

More information

Class 3: Training Recurrent Nets

Class 3: Training Recurrent Nets Class 3: Training Recurrent Nets Arvind Ramanathan Cmputatinal Science & Engineering, Oak Ridge Natinal Labratry, Oak Ridge, TN 3783 ramanathana@rnl.gv 1 Last class Basics f RNNs Recurrent netwrk mdeling

More information

Secure Mobile Access to the Local ICS Network. Jan Vossaert Veilige industriële netwerken 29/09/2016

Secure Mobile Access to the Local ICS Network. Jan Vossaert Veilige industriële netwerken 29/09/2016 Secure Mbile Access t the Lcal ICS Netwrk Jan Vssaert Veilige industriële netwerken 29/09/2016 Intrductin ffice netwrk prductin cell ruter 192.168.2.0/24 Internet ICS DMZ servers 192.168.1.0/24 prductin

More information

16/07/2012. Design Patterns. By Võ Văn Hải Faculty of Information Technologies - HUI. Behavioral Patterns. Session objectives. Strategy.

16/07/2012. Design Patterns. By Võ Văn Hải Faculty of Information Technologies - HUI. Behavioral Patterns. Session objectives. Strategy. Design Patterns By Võ Văn Hải Faculty f Infrmatin Technlgies - HUI Behaviral Patterns Sessin bjectives Strategy Observer 2 1 Behaviral Patterns 3 Mtivating example - SimpleUDuck Je wrks fr a cmpany that

More information

CS510 Concurrent Systems Class 1a. Linux Kernel Locking Techniques

CS510 Concurrent Systems Class 1a. Linux Kernel Locking Techniques CS510 Cncurrent Systems Class 1a Linux Kernel Lcking Techniques Intr t kernel lcking techniques (Linux) Why d we need lcking in the kernel? Which prblems are we trying t slve? What implementatin chices

More information

KIRA-CS. Why KIRA-CS Supercomputer. Inside KIRA-CS. Elastic Supercomputing Architecture. Exa-Converged Architecture

KIRA-CS. Why KIRA-CS Supercomputer. Inside KIRA-CS. Elastic Supercomputing Architecture. Exa-Converged Architecture Explring Exa-Supercmputing Scenaris Fr New Emerging Challenges Why Supercmputer The series delivers n A3Cube s cmmitment t an adaptive supercmputing architecture that prvides bth extreme scalability and

More information

Cisco Tetration Analytics, Release , Release Notes

Cisco Tetration Analytics, Release , Release Notes Cisc Tetratin Analytics, Release 1.102.21, Release Ntes This dcument describes the features, caveats, and limitatins fr the Cisc Tetratin Analytics sftware. Additinal prduct Release ntes are smetimes updated

More information

Instance Based Learning

Instance Based Learning Instance Based Learning Vibhav Ggate The University f Texas at Dallas Readings: Mitchell, Chapter 8 surces: curse slides are based n material frm a variety f surces, including Tm Dietterich, Carls Guestrin,

More information

Data Structure Interview Questions

Data Structure Interview Questions Data Structure Interview Questins A list f tp frequently asked Data Structure interview questins and answers are given belw. 1) What is Data Structure? Explain. Data structure is a way that specifies hw

More information

Priority-aware Coflow Placement and scheduling in Datacenters

Priority-aware Coflow Placement and scheduling in Datacenters Pririty-aware Cflw Placement and scheduling in Datacenters Speaker: Lin Wang Research Advisr: Biswanath Mukherjee Intrductin Cflw Represents a cllectin f independent flws that share a cmmn perfrmance gal.

More information

Exploring the Viability of the Cell Broadband Engine for Bioinformatics Applications

Exploring the Viability of the Cell Broadband Engine for Bioinformatics Applications Exploring the Viability of the Cell Broadband Engine for Bioinformatics Applications Vipin Sachdeva 1, Michael Kistler 1, Evan Speight, 1 and Tzy-Hwa Kathy Tzeng 2 1 IBM Austin Research Lab 2 IBM Systems

More information

CA CMDB Connector for z/os

CA CMDB Connector for z/os PRODUCT SHEET: CA CMDB CONNECTOR FOR Z/OS CA CMDB Cnnectr fr z/os CA CMDB Cnnectr fr z/os discvers mainframe cnfiguratin items (CIs) and enables ppulatin f that infrmatin int the CA CMDB repsitry. Designed

More information

Teaching Operating Systems Scheduling

Teaching Operating Systems Scheduling Prceedings f Infrming Science & IT Educatin Cnference (InSITE) 2010 Teaching Operating Systems Scheduling Shimn Chen MLA Academic Learning Center, Israel shamn51@gmail.cm Abstract The Operating System

More information

Developing Microsoft SharePoint Server 2013 Core Solutions

Developing Microsoft SharePoint Server 2013 Core Solutions Develping Micrsft SharePint Server 2013 Cre Slutins Develping Micrsft SharePint Server 2013 Cre Slutins Curse Cde: 20488 Certificatin Exam: 70-488 Duratin: 5 Days Certificatin Track: N/A Frmat: Classrm

More information

Scatter Search And Bionomic Algorithms For The Aircraft Landing Problem

Scatter Search And Bionomic Algorithms For The Aircraft Landing Problem Scatter Search And Binmic Algrithms Fr The Aircraft Landing Prblem J. E. Beasley Mathematical Sciences Brunel University Uxbridge UB8 3PH United Kingdm http://peple.brunel.ac.uk/~mastjjb/jeb/jeb.html Abstract:

More information

HP ExpertOne. HP2-T21: Administering HP Server Solutions. Table of Contents

HP ExpertOne. HP2-T21: Administering HP Server Solutions. Table of Contents HP ExpertOne HP2-T21: Administering HP Server Slutins Industry Standard Servers Exam preparatin guide Table f Cntents In this sectin, include a table f cntents (TOC) f all headings. After yu have finished

More information

Retrieval Effectiveness Measures. Overview

Retrieval Effectiveness Measures. Overview Retrieval Effectiveness Measures Vasu Sathu 25th March 2001 Overview Evaluatin in IR Types f Evaluatin Retrieval Perfrmance Evaluatin Measures f Retrieval Effectiveness Single Valued Measures Alternative

More information

Eastern Mediterranean University School of Computing and Technology Information Technology Lecture2 Functions

Eastern Mediterranean University School of Computing and Technology Information Technology Lecture2 Functions Eastern Mediterranean University Schl f Cmputing and Technlgy Infrmatin Technlgy Lecture2 Functins User Defined Functins Why d we need functins? T make yur prgram readable and rganized T reduce repeated

More information

To over come these problems collections are recommended to use. Collections Arrays

To over come these problems collections are recommended to use. Collections Arrays Q1. What are limitatins f bject Arrays? The main limitatins f Object arrays are These are fixed in size ie nce we created an array bject there is n chance f increasing r decreasing size based n ur requirement.

More information

Multi-Device Basic. Sample User's Guide. Intel SDK for OpenCL* Applications - Samples. Document Number: US

Multi-Device Basic. Sample User's Guide. Intel SDK for OpenCL* Applications - Samples. Document Number: US Sample User's Guide Intel SDK fr OpenCL* Applicatins - Samples Dcument Number: 329763-004US Cntents Legal Infrmatin... 3 Abut Multi-Device Basic Sample... 4 Algrithm... 4 OpenCL* Implementatin... 5 System-Level

More information

History of Java. VM (Java Virtual Machine) What is JVM. What it does. 1. Brief history of Java 2. Java Version History

History of Java. VM (Java Virtual Machine) What is JVM. What it does. 1. Brief history of Java 2. Java Version History Histry f Java 1. Brief histry f Java 2. Java Versin Histry The histry f Java is very interesting. Java was riginally designed fr interactive televisin, but it was t advanced technlgy fr the digital cable

More information

CONTROL-COMMAND. Software Technical Specifications for ThomX Suppliers 1.INTRODUCTION TECHNICAL REQUIREMENTS... 2

CONTROL-COMMAND. Software Technical Specifications for ThomX Suppliers 1.INTRODUCTION TECHNICAL REQUIREMENTS... 2 Réf. ThmX-NT-SI-CC001 Table f Cntents Sftware Technical Specificatins fr ThmX Authr : Philippe Page 1 / 9 1.INTRODUCTION... 2 2.TECHNICAL REQUIREMENTS... 2 3.DOCUMENTATION REQUIREMENTS... 4 4.COMPUTING

More information

DVS Enterprise Test Results for Microsoft Lync 2013 and Citrix XenDesktop 7. Dell Client Cloud Computing Engineering Revision: 1.

DVS Enterprise Test Results for Microsoft Lync 2013 and Citrix XenDesktop 7. Dell Client Cloud Computing Engineering Revision: 1. DVS Enterprise Test Results fr Micrsft Lync 2013 and Citrix XenDesktp 7 Dell Client Clud Cmputing Engineering Revisin: 1.0 11/6/13 THIS DOCUMENT IS FOR INFORMATIONAL PURPOSES ONLY, AND MAY CONTAIN TYPOGRAPHICAL

More information

Overview. Features. Intel Media SDK 2014 Audio Library has API version 1.8. The following audio formats are supported: Decoding

Overview. Features. Intel Media SDK 2014 Audio Library has API version 1.8. The following audio formats are supported: Decoding Intel Media Sftware Develpment Kit 2014 Audi Library Release Ntes (Versin 5.0.337.79303) Overview Features System Requirements Package Cntents Installatin Knwn Limitatins Legal Infrmatin Overview The Intel

More information

RELEASE NOTES FOR PHOTOMESH 7.3.1

RELEASE NOTES FOR PHOTOMESH 7.3.1 RELEASE NOTES FOR PHOTOMESH 7.3.1 Abut PhtMesh Skyline s PhtMesh fully autmates the generatin f high-reslutin, textured, 3D mesh mdels frm standard 2D phtgraphs, ffering a significant reductin in cst and

More information

Troubleshooting of network problems is find and solve with the help of hardware and software is called troubleshooting tools.

Troubleshooting of network problems is find and solve with the help of hardware and software is called troubleshooting tools. Q.1 What is Trubleshting Tls? List their types? Trubleshting f netwrk prblems is find and slve with the help f hardware and sftware is called trubleshting tls. Trubleshting Tls - Hardware Tls They are

More information

Understanding the Backward Slices of Performance Degrading Instructions

Understanding the Backward Slices of Performance Degrading Instructions Understanding the Backward Slices of Performance Degrading Instructions Craig Zilles and Guri Sohi University of Wisconsin - Madison International Symposium on Computer Architecture June, 2000 Motivation

More information

SSDNow vs. HDD and Use Cases/Scenarios. U.S.T.S. Tech. Comm

SSDNow vs. HDD and Use Cases/Scenarios. U.S.T.S. Tech. Comm SSDNw vs. HDD and Use Cases/Scenaris U.S.T.S. Tech. Cmm Intrductin This white paper examines the technlgy f SSDNw and its ptential applicatin scenaris. Features and benefits f emplying Slid State Drives

More information

WEB LAB - Subset Extraction

WEB LAB - Subset Extraction WEB LAB - Subset Extractin Fall 2005 Authrs: Megha Siddavanahalli Swati Singhal Table f Cntents: Sl. N. Tpic Page N. 1 Abstract 2 2 Intrductin 2 3 Backgrund 2 4 Scpe and Cnstraints 3 5 Basic Subset Extractin

More information

RTXC Quadros Real-time Operating System Technical Summary Quadros Systems, Inc.

RTXC Quadros Real-time Operating System Technical Summary Quadros Systems, Inc. RTXC Quadrs Real-time Operating System Technical Summary Quadrs Systems, Inc. Real-time Operating Systems fr Cnvergent Prcessing www.quadrs.cm RTXC Quadrs Technical Summary Table f Cntents 1 Intrductin...

More information

SVC-T using DM36x H.264 codec

SVC-T using DM36x H.264 codec SVC-T using DM36x H.264 cdec Applicatin nte Versin 1.1 Date: 10 th Dec 2010 Scalable vide cding n DM36x This dcument describes hw t use tempral scalability in the beta H.264 ver 2.1 cdec. It is assumed

More information

Matlab Based High Level Synthesis Engine for Area And Power Efficient Arithmetic Operations

Matlab Based High Level Synthesis Engine for Area And Power Efficient Arithmetic Operations ISSN (e): 2250 3005 Vlume, 06 Issue, 04 April 2016 Internatinal Jurnal f Cmputatinal Engineering Research (IJCER) Matlab Based High Level Synthesis Engine fr Area And Pwer Efficient Arithmetic Operatins

More information

PaperStream Capture change history

PaperStream Capture change history PaperStream Capture change histry Versin 2.0.1 New features: 1. Ad hc scan is added, which allws yu t mdify sme f the settings (scanner setting, destinatin setting, etc.) extempre and scan withut changing

More information

Lecture 6 -.NET Remoting

Lecture 6 -.NET Remoting Lecture 6 -.NET Remting 1. What is.net Remting?.NET Remting is a RPC technique that facilitates cmmunicatin between different applicatin dmains. It allws cmmunicatin within the same prcess, between varius

More information

Studio Software Update 7.7 Release Notes

Studio Software Update 7.7 Release Notes Studi Sftware Update 7.7 Release Ntes Summary: Previus Studi Release: 2013.10.17/2015.01.07 All included Studi applicatins have been validated fr cmpatibility with previusly created Akrmetrix Studi file

More information

CSE 361S Intro to Systems Software Lab #2

CSE 361S Intro to Systems Software Lab #2 Due: Thursday, September 22, 2011 CSE 361S Intr t Systems Sftware Lab #2 Intrductin This lab will intrduce yu t the GNU tls in the Linux prgramming envirnment we will be using fr CSE 361S this semester,

More information

The programming for this lab is done in Java and requires the use of Java datagrams.

The programming for this lab is done in Java and requires the use of Java datagrams. Lab 2 Traffic Regulatin This lab must be cmpleted individually Purpse f this lab: In this lab yu will build (prgram) a netwrk element fr traffic regulatin, called a leaky bucket, that runs ver a real netwrk.

More information

This labs uses traffic traces from Lab 1 and traffic generator and sink components from Lab 2.

This labs uses traffic traces from Lab 1 and traffic generator and sink components from Lab 2. Lab 3 Packet Scheduling Purpse f this lab: Packet scheduling algrithms determine the rder f packet transmissin at the utput link f a packet switch. This lab includes experiments that exhibit prperties

More information