Computer Organization and Architecture

Transcription

1 Campus de Gualtar Braga UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA Departament de Infrmática Cmputer Organizatin and Architecture 5th Editin, 2000 by William Stallings Table f Cntents I. OVERVIEW. 1. Intrductin. 2. Cmputer Evlutin and Perfrmance. II. THE COMPUTER SYSTEM. 3. System Buses. 4. Internal Memry. 5. External Memry. 6. Input/Output. 7. Operating System Supprt. III. THE CENTRAL PROCESSING UNIT. 8. Cmputer Arithmetic. 9. Instructin Sets: Characteristics and Functins. 10. Instructin Sets: Addressing Mdes and Frmats. 11. CPU Structure and Functin. 12. Reduced Instructin Set Cmputers (RISCs). 13. Instructin-Level Parallelism and Superscalar Prcessrs. IV. THE CONTROL UNIT. 14. Cntrl Unit Operatin. 15. Micrprgrammed Cntrl. V. PARALLEL ORGANIZATION. 16. Parallel Prcessing. Appendix A: Digital Lgic. Appendix B: Prjects fr Teaching Cmputer Organizatin and Architecture. References. Glssary. Index. Acrnyms.

2 2 III. THE CENTRAL PROCESSING UNIT Reduced Instructin Set Cmputers (RISCs). (5-Jan-01) Intrductin RISC is ne f the few true innvatins in cmputer rganizatin and architecture in the last 50 years f cmputing. Key elements cmmn t mst designs: A limited and simple instructin set A large number f general purpse registers, r the use f cmpiler technlgy t ptimize register usage An emphasis n ptimizing the instructin pipeline Instructin Executin Characteristics (12.1) Overview Semantic Gap - the difference between the peratins prvided in high-level languages and thse prvided in cmputer architecture Symptms f the semantic gap: Executin inefficiency Excessive machine prgram size Cmpiler cmplexity New designs had features trying t clse gap: Large instructin sets Dzens f addressing mdes Varius HLL statements in hardware Intent f these designs: Make cmpiler-writing easier Imprve executin efficiency by implementing cmplex sequences f peratins in micrcde Prvide supprt fr even mre cmplex and sphisticated HLL's Cncurrently, studies f the machine instructins generated by HLL prgrams Lked at the characteristics and patterns f executin f such instructins Results lead t using simpler architectures t supprt HLL's, instead f mre cmplex T understand the reasning f the RISC advcates, we lk at study results n 3 main aspects f cmputatin: Operatins perfrmed - the functins t be perfrmed by the CPU and its interactin with memry. Operands used - types f perands and their frequency f use. Determine memry rganizatin and addressing mdes. Executin Sequencing - determines the cntrl and pipeline rganizatin. Study results are based n dynamic measurements (during prgram executin), s that we can see effect n perfrmance Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

3 3 Operatins Simple cunting f statement frequency indicates that assignment (data mvement) predminates, fllwed by selectin/iteratin. Weighted studies shw that call/return actually accunts fr the mst wrk Target architectural rganizatin t supprt these peratins well Pattersn study als lked at dynamic frequency f ccurrence f classes f variables. Results shwed a prepnderance f references t highly lcalized scalars: Majrity f references are t simple scalars Over 80% f scalars were lcal variables References t arrays/structures require a previus ref t their index r pinter, which is usually a lcal scalar Operands Anther study fund that each instructin (DEC-10 in this case) references 0.5 perands in memry and 1.4 registers. Implicatins: Need fr fast perand accessing Need fr ptimized mechanisms fr string and accessing lcal scalar variables Executin Sequencing Subrutine calls are the time-cnsuming peratin in HLL's Minimize their impact by Streamlining the parameter passing Efficient access t lcal variables Supprt nested subrutine invcatin Statistics 98% f dynamically called prcedures passed fewer than 6 parameters 92% use less than 6 lcal scalar variables Rare t have lng sequences f subrutine calls fllwed by returns (e.g., a recursive srting algrithm) Depth f nesting was typically rather lw Implicatins Reducing the semantic gap thrugh cmplex architectures may nt be the mst efficient use f system hardware Optimize machine design based n the mst time-cnsuming tasks f typical HLL prgrams Use large numbers f registers Reduce memry reference by keeping variables clse t CPU (mre register refs instead) Streamlines instructin set by making memry interactins primarily lads and stres Pipeline design Minimize impact f cnditinal branches Simplify instructin set rather than make it mre cmplex Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

4 4 Large Register Files (12.2) Hw can we make prgrams use registers mre ften? Sftware - ptimizing cmpilers Cmpiler attempts t allcate registers t thse variables that will be used mst in a given time perid Requires sphisticated prgram-analysis algrithms Hardware Make mre registers available, s that they'll be used mre ften by rdinary cmpilers Pineered at Berkeley by first cmmercial RISC prduct, the Pyramid Register Windws Naively adding registers will nt effectively reduce need t access memry Since mst perand references are t lcal scalars, bviusly stre them in registers, with maybe a few fr glbal variables Prblem: Definitin f lcal changes with each prcedure call and return (which happen a lt!) On call, lcals must be mved frm registers t memry t make rm fr called subrutine Parameters must be passed On return, parent variables must mve back t registers Remember study results: S: A typical prcedure uses nly a few passed parameters and lcal variables The depth f prcedure activatin fluctuates within a relatively narrw range Use multiple small sets f registers, each assigned t a different prcedure A prcedure call autmatically switches the CPU t use a different fixedsize windw f registers (n saving registers in memry!) Windws fr adjacent prcedures are verlapped t allw parameter passing Since there is a limit t number f windws, we use a circular buffer f windws Only hld the mst recent prcedure activatins in register windws Older activatins must be saved t memry and later restred An N-windw register file can hld nly N-1 prcedure activatins One study fund that with 8 windws, a save r restre is needed n nly 1% f calls r returns Glbal variables Culd just use memry, but wuld be inefficient fr frequently used glbals Incrprate a set f glbal registers in the CPU. Then, the registers available t a prcedure wuld be split: sme wuld be the glbal registers the rest wuld be in the current windw. Hardware wuld have t als: decide which glbals t put in registers accmmdate the split in register addressing Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

5 5 Large Register File vs. Cache Why nt just build a big cache? Answer nt clear cut Windw hlds all lcal scalars Cache hlds selectin f recently used data Cache can be frced t hld data it never uses (due t blck transfers) Current data in cache can be swapped ut due t accessing scheme used Cache can easily stre glbal and lcal variables Addressing registers is cleaner and faster Cmpiler-Based Register Optimizatin (12.3) In this case, the number f registers is small cmpared t the large register file implementatin The cmpiler is respnsible fr managing the use f the registers Cmpiler must map the current and prjected use f variables nt the available registers Similar t a graph clring prblem Frm a graph with variables as ndes and edges that link variables that are active at the same time Clr the graph with as many clrs as yu have registers Variables nt clred must be stred in memry Reduced Instructin Set Architecture (12.4) Why CISC? CISC trends t richer instructin sets Mre instructins Mre cmplex instructins Reasns T simplify cmpilers Are cmpilers simplified? T imprve perfrmance Assertin: If there are machine instructins that resemble HLL statements, cmpiler cnstructin is simpler Cunter-arguments: Cmplex machine instructins are ften hard t explit because the cmpiler must find thse cases that fit the cnstruct Other cmpiler gals Minimizing cde size Reducing instructin executin cunt Enhancing pipelining are mre difficult with a cmplex instructin set Studies shw that mst instructins actually prduced by CISC cmpilers are the relatively simple nes Is perfrmance imprved? Assertin: Prgrams will be smaller and they will execute faster Smaller prgrams save memry Smaller prgrams have fewer instructins, requiring less instructin fetching Smaller prgrams ccupy fewer pages in a paged envirnment, s have fewer page faults Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

6 Cunter- Inexpensive memry makes memry savings less cmpelling used may nt be smaller 6 Opcdes require mre bits t register identifiers (which are the usual case fr RISC) peratins, s even the mre ften- The speedup fr cmplex instructins may be mstly due t their implementatin as simpler that the CISC designer must decide a priri which instructins t speed up in this way) One instructin per cycle registers, perfrm and ALU peratin, and stre the result in a register RISC machine instructins shuld be n mre cmplicated than, and execute s fast as micrinstructins n a CISC machine N micrcding needed, and simple instructins will execute faster than their Register- -register peratins Ptential benefits ins access memry Simplifies instructin set and cntrl unit Ex. VAX has 25 different ADD instructins Encurages ptimizatin f register use Almst all instructins use simple register addressing Mre cmplex addressing is implemented in sftware frm the simpler nes Further simplifies instructin set and cntrl unit Only a few frmats are used Instructin length is fixed and aligned n wrd bundaries Optimizes instructin fetching Field lcatins (especially the pcde) are fixed Allws simul Mre effective ptimizing cmpilers Instructin pipelining can be applied mre effectively with a reduced instructin set They are checked between rudimentary peratins N need fr cmplex instructin restarting mechanisms Universidade d Minh Dep. Infrmática Campus de Gualtar Braga - PORTUGAL

7 Requires less "real estate" fr cntrl unit (6% in RISC I vs. abut 50% fr CISC micrcde stre) Less design and implementatin time 7 RISC Pipelining (12.5) The simplified structure f RISC instructins allws us t recnsider pipelining Mst instructins are register-t-register, s an instructin cycle has 2 phases I: Instructin Fetch E: Execute (an ALU peratin w/ register input and utput) Fr lad and stre peratins, 3 phases are needed I: Instructin fetch E: Execute (actually memry address calculatin) D: Memry (register-t-memry r memry-t-register) Since the E phase usually invlves an ALU peratin, it may be lnger than the ther phases. In this case, we can divide it int 2 sub phases: E1: Register file read E2: ALU peratin and register write Optimizatin f Pipelining Delayed Branch We've seen that data and branch dependencies reduce the verall executin rate in the pipeline Delayed branch makes use f a branch that des nt take effect until after the executin f the fllwing instructin Nte that the branch "takes effect" during its executin phase S, the instructin lcatin immediately fllwing the branch is called the delay slt This is because the instructin fetching rder is nt affected by the branch until the instructin after the delay slt Rather than wasting an instructin with a NOOP, it may be pssible t mve the instructin preceding the branch t the delay slt, while still retaining the riginal prgram semantics. Cnditinal branches If the instructin immediately preceding the branch cannt alter the branch cnditin, this ptimizatin can be applied Otherwise a NOOP delay is still required. Experience with bth the Berkeley RISC and IBM 801 systems shws that a majrity f cnditinal branches can be ptimized this way. Delayed Lad On lad instructins, the register t be laded is lcked by the prcessr The prcessr cntinues executin f the instructin stream until reaching an instructin needing a lcked register It then idles until the lad is cmplete If lad takes a specific maximum number f clck cycles, it may be pssible t rearrange instructins t avid the idle. Superpipelining A superpipelined architecture is ne that makes use f mre, and finer-grained, pipeline stages. Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

8 The MIPS R3000 is an example f superpipelining All instructins fllw the same sequence f 5 pipeline stages (the 60-ns clck cycle is divided int tw 30-ns phases) But the activities needed fr each stage may ccur in parallel, and may nt use an entire stage Essentially then, we can break up the external instructin and data cache peratins, and the ALU peratins, int 2 phases 8 In general: In a superpipelined system existing hardware is used several times per cycle by inserting pipeline registers t split up each pipe stage Each superpipeline stage perates at a multiple f the base clck frequency The multiple depends n the degree f superpipelining (the number f phases int which each stage is split) The MIPS R4000 (which has imprvements ver the R3000 f the previus slide) is an example f superpipelining f degree 2 (see sectin 12.6 fr details). Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000

9 9 The RISC vs. CISC Cntrversy (12.8) In spite f the apparent advantages f RISC, it is still an pen questin whether the RISC apprach is demnstrably better. Studies t cmpare RISC t CISC are hampered by several prblems (as f the textbk writing): There is n pair f RISC and CISC machines that are clsely cmparable N definitive set f test prgrams exist. It is difficult t srt ut hardware effects frm effects due t skill in cmpiler writing. Mst f the cmparative analysis n RISC has been dne n ty machines, rather than cmmercial prducts. Mst cmmercially available RISC machines pssess a mixture f RISC and CISC characteristics. The cntrversy has died dwn t a great extent As chip densities and speeds increase, RISC systems have becme mre cmplex T imprve perfrmance, CISC systems have increased their number f generalpurpse registers and increased emphasis n instructin pipeline design. Universidade d Minh Dep. Infrmática - Campus de Gualtar Braga - PORTUGAL- William Stallings, Cmputer Organizatin and Architecture, 5th Ed., 2000