ARM Programmer s Model

Transcription

1 ARM Prgrammer s Mdel Hsung-Pin Chang Department f Cmputer Science Natinal Chung Hsing University PDF created with FinePrint pdffactry Pr trial versin

2 Outline ARM Data Types ARM Prcessr Mdes ARM Operating States ARM Registers ARM Exceptins Memry and memry-mapped I/O PDF created with FinePrint pdffactry Pr trial versin

3 ARM Data Type ARM prcessr supprt the fllwing data types Byte: 8 bits Halfwrd: 16 bits Halfwrds must be aligned t tw-byte bundaries Wrd: 32 bits Wrds must be aligned t fur-byte bundaries PDF created with FinePrint pdffactry Pr trial versin

4 ARM Data Type (Cnt.) ARM allw addresses t be 32 bits lng An address refer t a byte, nt a wrd Wrd 0 is at lcatin 0 Wrd 1 is at lcatin 4 PC is incremented by 4 in sequential access Can be cnfigured at pwer-up t address the bytes in a wrd in either little-endian r bitendian mde PDF created with FinePrint pdffactry Pr trial versin

5 Byte Organizatin Within an ARM Wrd Little-endian mde The lwest-rder byte residing in the lw-rder bits f the wrd Big-endian mde The lwest-rder byte stred in the highest bits f the wrd bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian PDF created with FinePrint pdffactry Pr trial versin

6 ARM Prcessr Mdes User mde: a nrmal prgram executin state FIQ (Fast Interrupt Request) mde: fr supprting a specific data transfer r channel prcessing IRQ (Interrupt ReQuest) mde: fr general purpse interrupt handling Supervisr mde: a prtected mde fr the perating system Abrt mde: entered when a data r instructin pre-fetch is abrted System mde: a privileged user mde fr the perating system, fr example, implement reentrant interrupt handler Undefined mde: entered when an undefined instructin is executed PDF created with FinePrint pdffactry Pr trial versin

7 ARM Operating Mdes (Cnt.) Operating mde changes Can be cntrlled by sftware. Can als be caused by external interrupts r exceptin prcessing Mst applicatin prgrams execute in user mde. Privileged mdes (the mdes ther than User mde) Are entered t service interrupts r exceptins, r t access prtected resurces. PDF created with FinePrint pdffactry Pr trial versin

8 ARM Operating Mdes (Cnt.) Exceptin mde (the privileged mde ther than the system mde) Entered when specific exceptins ccur Each has sme additinal registers t avid crrupting User mde state when the exceptin ccurs System mde Nt entered by an exceptin Have exactly the same registers available in User mde Hwever, it is a privileged mde and can access any system resurces PDF created with FinePrint pdffactry Pr trial versin

9 ARM Operating States ARM state Executing 32-bit, wrd-aligned, ARM instructins THUMB state Executing 16-bit, half-wrd aligned THUMB instructins These states can be switched by sftware r by exceptin prcessing PDF created with FinePrint pdffactry Pr trial versin

10 ARM Registers ARM has a ttal f 37 registers 31: general-purpse, 32-bit registers r0~r15, r8_fiq~r13_fiq, r14_fiq, r13_irq, r14_irq, r13_svc, r14_svc, r13_abt, r14_abt, r13_und, r14_und 6: status registers CPSR SPSR_fiq, SPSR_irq, SPSR_svc, SPSR_abt, SPSR_und Nt all f these registers are always available Prcessr state: ARM r Thumb Operating mde Unbanked registers: r0~r7 Banked registers: r8~r14 PDF created with FinePrint pdffactry Pr trial versin

11 Nte Unbanked registers (R0-R7) Each f the registers refers t the same 32-bit physical registers in all prcessr mdes Bankded registers (R8-R14) The physical register referred t by each f them depends n the current prcessr mde If a particular register is intended withut depending n the current prcessr mde Fr example, R8_usr v.s. R8_fiq PDF created with FinePrint pdffactry Pr trial versin

12 Register Organizatin in ARM States Mde User Mde & System Mde FIQ Mde Registers r0~r13, LR(r14), PC (r15), CPSR r0~r7, r8_fiq~r13_fiq, r14_fiq, PC, CPSR, SPSR_fiq IRQ Mde Supervisr Mde Abrt Mde Undefined Mde r0~r12, r13_irq, r14_irq, PC, CPSR, SPSR_irq r0~r12, r13_svc, r14_svc, PC, CPSR, SPSR_svc r0~r12, r13_abt, r14_abt, PC, CPSR, SPSR_abt r0~r12, r13_und, r14_und, PC, CPSR, SPSR_und PDF created with FinePrint pdffactry Pr trial versin

13 Register Organizatin in ARM States PDF created with FinePrint pdffactry Pr trial versin

14 Register Organizatin in ARM States PDF created with FinePrint pdffactry Pr trial versin

15 ARM Registers (Cnt.) R8-R12 Have tw banked physical registers R13-R14 Have six banked physical registers PDF created with FinePrint pdffactry Pr trial versin

16 ARM Registers (Cnt.) By cnventin R13: SP (stack pinter) R14: LR (link register) In User mde: R14 is used as a link register t stre the return address when a subrutine is made In the exceptin handling mdes, R14 hlds the return address fr the exceptin R15: PC (prgram cunter) Incremented by ne wrd fr each instructin T return frm a subrutine MOV pc, lr PDF created with FinePrint pdffactry Pr trial versin

17 PSR (Prgram Status Register) Register The frmat f CPSR and SPSR are the same Called PSR in general One CPSR (Current Prgram Status Register) Cpies f the Arithmetic Lgic Unit (ALU) status flags The current prcessr mde Interrupt disable flags Five SPSR (Saved Prgram Status Registers) Used t stre the CPSU when an exceptin is taken One SPSU is accessible in each f the exceptin-handling mde User mde and System mde d nt have an SPSR because they are nt exceptin handling mdes PDF created with FinePrint pdffactry Pr trial versin

18 PSR Register (Cnt.) Flag field: PSR[31:24], ARM7TDMI nly defines fur bits PSR[31]: N, PSR[30]: Z, PSR[29]: C, PSR[28]: V Status field: PSR[23:16], undefined in ARM7TDMI Extensin field: PSR[15:8], undefined in ARM7TDMI Cntrl field I: PSR[7]: if 1, disable interrupt F: PSR[6]: if 1, disable fast interrupt T: prcessr is in ARM state (T=0) r in Thumb state (T = 1) Mde: prcessr mde N Z C V undefined I F T mde PDF created with FinePrint pdffactry Pr trial versin

19 Status Bits Tp fur bits f the CPSR N: set when the result is negative in tw scmplement arithmetic Z: set when every bit f the result is zer C: set when there is a carry ut f the peratin V: set when an arithmetic peratin results in an verflw PDF created with FinePrint pdffactry Pr trial versin

20 Mde Bits PDF created with FinePrint pdffactry Pr trial versin

21 PSR Registers (Cnt.) PDF created with FinePrint pdffactry Pr trial versin

22 MSR and MRS Instructins T access the CPSR and SPSR registers must use MSR and MRS instructins MRS: Mve PSR t a General-purpse Register MSR: Mve Register t PSR status/flags Discussed later in the instructin set sectin PDF created with FinePrint pdffactry Pr trial versin

23 ARM Exceptins An exceptin arises when the nrmal flw f prgram executin is interrupted The prcessr state just prir t handling the exceptin must be preserved The prgram flw can be resumed when the exceptin rutine is cmpleted T prcess exceptins, the ARM prcessr uses the banked cre registers t save the current state The ld PC value are cpied int the R14 (LR) register The CPSR cntents are cpied int the SPSR registers. PDF created with FinePrint pdffactry Pr trial versin

24 ARM Exceptins (Cnt.) T return after handling the exceptin SPSR is mved t the CPSR R14 is mved t the PC (R14) When an exceptin ccurs Executin is frced t execute frm a fixed memry address crrespnding t the type f executin These fixed addresses are called the exceptin vectr PDF created with FinePrint pdffactry Pr trial versin

25 ARM Exceptin PDF created with FinePrint pdffactry Pr trial versin

26 ARM Exceptin Types Reset Undefined instructin Sftware Interrupt (SWI) Prefetch Abrt Data Abrt IRQ FIQ PDF created with FinePrint pdffactry Pr trial versin