Data reduction in the ITMS system through a data acquisition model with self-adaptive sampling rate

Transcription

1 Data reductin in the ITMS system thrugh a data acquisitin mdel with self-adaptive sampling rate M. Ruiz, JM. Lpez, G. de Areas, E. Barrera, R. Melendez, J. Vega Grup de Investigatin en Instrumentatin y Acustica Aplicada, Universidad Plitecnica de Madrid (UPM), Departament de Sistemas Electrnics y de Cntrl, Universidad Plitecnica de Madrid (UPM), Asciacin EURATOM/CIEMAT para Fusin, Madrid, Spain Abstract Lng pulse r steady state peratin f fusin experiments require data acquisitin and prcessing systems that reduce the vlume f data invlved. The availability f self-adaptive sampling rate systems and the use f real-time lssless data cmpressin techniques can help slve these prblems. The frmer is imprtant fr cntinuus adaptatin f sampling frequency fr experimental requirements. The latter allws the maintenance f cntinuus digitizatin under limited memry cnditins. This can be achieved by permanent transmissin f cmpressed data t ther systems. The cmpacted transfer ensures the use f minimum bandwidth. This paper presents an implementatin based n intelligent test and measurement system (ITMS), a data acquisitin system architecture with multiprcessing capabilities that permits it t adapt the system's sampling frequency thrughut the experiment. The sampling rate can be cntrlled depending n the experiment's specific requirements by using an external dc vltage signal r by defining user events thrugh sftware. The system takes advantage f the high prcessing capabilities f the ITMS platfrm t implement a data reductin mechanism based in lssless data cmpressin algrithms which are themselves based in peridic deltas. Keywrds: Real-time data acquisitin and prcessing; Adaptive sampling; Lssless cmpressin; Advanced intelligent instrumentatin 1. Intrductin One gal in data acquisitin systems used in lng pulse r steady state fusin diagnstics is t acquire capabilities t adapt the sampling rate depending n the experiment's time evlutin. Anther is t cmpress the acquired infrmatin in rder t reduce the high amunt f data t be prcessed, and therefre reduce the required netwrk bandwidth and strage requirements. In rder t achieve these gals, flexible data acquisitin system architecture that can be easily custmized t specific experiment requirements within a shrt develpment time is needed The ITMS platfrm is an example f such system architecture. The final gal f ITMS is t ffer a technlgy, cnsisting f a set fhardware and sftware tls that allws the develpment f advanced intelligent instruments (All) with fast data acquisitin and prcessing capabilities that can be recnfigured thrugh sftware. The system architecture and the use f furth generatin prgramming languages, such as Lab VIEW, allw the reductin f develpment time substantially. This paper presents an applicatin f this technlgy t implement a data acquisitin and prcessing system that has adaptive sampling capabilities, and can als cmpress the acquired data befre sending it t a database server r t ther prcessing systems thrugh a netwrk cnnectin. Bth features reduce the amunt f data acquired by the system, while maintaining the same amunt f infrmatin, allwing a reductin f the required transmissin bandwidth and strage requirements f the verall system. Adaptive sampling capabilities means that the sampling rate f data acquisitin cards that are used can be changed dynamically, e.g. during the experiment duratin, accrding t specific requirements. In rder t keep track f the sampling frequency used t acquire each sample,

2 this system uses an analgue dc vltage applied t an input f each data acquisitin card, which is related t the sampling rate being used. There is a direct relatin between the dc vltage value f that input channel and the sampling frequency being used t acquire the rest f the channels (see Sectin 3). The system als includes a data reductin mechanism that is implemented based in data cmpressin algrithms develped in Lab VIEW 2. ITMS architecture Fig. 1 shws the hardware architecture f the ITMS platfrm adapted t this applicatin. The hardware cnsists f the fllwing elements: One standard PXI chassis, with an embedded system CPU (SCPU). SCPU is used t cnfigure data acquisitin cards (DAQ), t acquire data frm DAQ channels, t distribute the acquired data amng system's CPUs and t prcess the data f desired channels. Several DAQ cards. Several peripheral CPU cards (PCPU) allcated in peripheral PXI slts (CC8-BLUES Pentium 3 frmekf System r Inva ICP-PM-4). PCPUs are used t prcess the data acquired frm desired channels. PCPUs will increase the cmputing capacity f the PXI platfrm as cmpared t typical PXI systems based nly in the system CPU cntrller ITMS sftware architecture is based in three sftware mdules that run bth in the SCPU and in the PCPUs (Fig. 2): Setup&DAQ, dynamic data prcessing system (DDPS) and event detectin and sample rate mdificatin (EDSRM). These mdules were develped using Linux kernel mdules (Fedra Cre 1) based n RTAI (Versin 3.3), the COMEDI data acquisitin driver and Lab VIEW (Versin 8.2). The Setup&DAQ mdule deals with the data acquisitin and distributin cnfiguratin and the acquisitin and data distributin amng prcessing elements f the system (PCPUs and SCPU). The user interface was develped in Lab VIEW, while the data acquisitin and distributin part was cded using Linux kernel mdules. The part that deals with the cntinuus data cllectin in the final user applicatins was develped in C and integrated in Lab VIEW cde by using cde interface ndes (CINs). The DDPS mdule is in charge f running the data prcessing rutines defined by the user. These rutines were develped in Lab VIEW. The results btained by DDPS are sent t anther cmputer using the netwrk cnnectin. The EDSRM mdule is a client-server applicatin that runs in each CPU (SCPU r PCPUs). The client, which usually runs in the PCPUs, detects the events generated by the DDPS mdule and sends them t the server mdule as messages thrugh TCP/IP. The server, which always runs in the SCPU, receives the messages frm the clients, r any ther external systems, and updates the sampling rate accrdingly. Sampling rate changes can als be caused by external systems by applying an external dc vltage signal t ne f the system's inputs (external sampling rate cntrl signal). The relatin between the sampling frequency and the external dc vltage value is defined during the system cnfiguratin prcess. The EDSRM server als checks fr changes in this vltage t detect sampling rate mdificatin requests. 3. Implementatin f the adaptive sampling rate mdel in the ITMS Sampling rate in cmmercial data acquisitin cards is cntrlled thrugh an internal r external clck signal. The raw data acquired frm the card des nt include any infrmatin abut the sampling rate that has been used t acquire it. The sampling rate infrmatin is added by the data acquisitin driver when it cllects the data, accrding t the data acquisitin cnfiguratin infrmatin. Fig. 3 shws hw the ITMS hardware architecture was mdified t implement adaptive sampling rate. The DAQ's external clck input is used t cntrl the acquisitin prcess. This clck is generated using a cunter f an additinal DAQ card (DAQO), whse input can be chsen between an external master clck signal cnnected t the clck's surce input, r the internal DAQ timebase clck. In additin, ne analg input channel f the DAQ card is used t read the value f the external sampling rate cntrl signal. Finally, an analg utput vltage channel f the same card is used t generate the mark vltage System Cntrller (SCPU) Prcessing card (PCPU) DAQ card System Cntrller slt Peripheral slt Peripheral slt Fig. 1. Standard ITMS platfrm hardware architecture.

3 SCPU EDSRM Server ^ DDPS T SETUP&DAQ l RTAI FIFOs 'J" LabVIEW SETUP&DAQ LINUX KERNEL f TCP/IP J PCPU Client I 1 T DDPS SETUP&DAQ [ LabVIEW RTAI FIFOs SETUP&DAQ ' LINUX KERNEL Fig. 2. Diagram f sftware applicatins, at LabVIEW and Linux kernel level, running in system CPU (SCPU) and peripheral CPUs (PCPUs). channel. This vltage is related t the sampling rate used fr a predefined set f values, and is cnnected t the analg input channel 0 f each DAQ card. This channel is named mark vltage channel ( VMC). When the sampling frequency is changed during an acquisitin, the analg dc vltage generated is als updated, and therefre when new samples are acquired, the sampling rate used can be determined by lking fr a change in the vltage level f the first input channel f that DAQ card. The hardware must guarantee that the changes in the sampling rate clck and the generated vltages are prduced simultaneusly. It must be nted that in this implementatin mdel it is nt necessary t stp and start the data acquisitin driver in rder t change the sampling rate. EXTERNAL REFERENCE CLOCK SCPU PCPUS v c DAQO SOURCE CLK O CLK OUT DACO CONTROL VOLTAGE DAQ1 SCAN CLOCK ACH1 ACHN DAQN SCAN CLOCK v ACH1 ACHN N-1 N-1 Measurement Signals Fig. 3. Mdified ITMS hardware architecture fr self-adaptive sampling rate. J The Setup&DAQ mdule running in the SCPU analyzes the mark channel in the data blcks in rder t determine if a change f the sampling rate has been prduced at any time, and assigns the crrect sampling infrmatin t each data blck. This mechanism ensures that any external system can change the sampling rate as needed by changing the analg dc vltage. An example f such an external system culd be a specific hardware f the experimental envirnment used t generate the tempral prfile f the sampling rate. Als, anther device f the same PXI system culd generate this cntrl vltage. Fig. 4 shws the steps in the ITMS during a change in the sampling rate fr a particular case in which it is necessary t increase the sampling rate if ne f the acquired signals has a significant amunt f energy in the 2 khz band (being this is a user defined event). The gal is that the system changes autmatically the sampling rate being used frm looks/s t 200 ks/s if it detects the abve mentined event. The system behaves as fllws (see Fig. 4): Step 1: The acquired data is cllected by the Setup&DAQ mdule running in the SCPU. This mdule analyzes the mark channel infrmatin t determine if there has been any change during that blck acquisitin in the sampling rate. Then it sends the data t be prcessed t the PCPU using a frame that cntains the fllwing elements: the initial sampling rate used in the buffer; the final sampling rate used in the buffer; the index within the buffer f the sample where the sampling rate was changed, r -1 if there had been n change; and the data blck size in bytes. Step 2: The frame is received by the Setup&DAQ mdule running in the PCPU and passed t the DDPS. Step 3: The frame is prcessed accrding t the desired event detectin algrithm develped by the user in LabVIEW. In this case, as an example, a flating pint FFT is perfrmed t determine if the input signal has energy in the 2 khz frequency band. As this is nt the case in this step nthing else happens and the cycle repeats. Step 4: Blck N is sent t PCPU1. Step 5: Blck N is received by PCPU 1. Step 6: If the DDPS mdule detects energy in the 2 khz band, it generates autmatically an event and sends it t the client EDSRM mdule running in the PCPU using Lab VIEW ntifiers. Step 7: The EDSRM client sends a message t the server EDSRM mdule running in the SCPU fr it t change the sampling rate. Step 8: When the server mdule receives this message it changes the sampling clck and the mark channel dc vltage accrdingly. These tasks can nly be dne in the SCPU. Step 9: The change in the sampling rate will be detected by the Setup&DAQ mdule running in the SCPU when a new blck arrives cntaining a change in the value f the vltage f the mark channel.

4 CD CO I g, < CO ^ ITMS SETUP & DAQ (Data acquisitin) Blck N-1 received PCPU1 a. «O t DL ~ ITMS DDPS (FFT analysis r amplitud detectin) Event Generatin ITMS EDSRM client (Event capture Message t EDSRM Server) I Blck N-1 prcessed FFT N event U Blck N prcessed FFT tj, Event Generatin Event Capture Message t EDSRM Server tsi 3 0) ITMS SETUP & DAQ (DAQ Setup Data acquisitin Data distributin) "Blck N-1 t PCPU1 Blck N t PPPU1 ijbick N+1 t PCPU1 Change detected in sample rate in sample x GO EDSRM server (Attend messages and changes sample rate) lil Message redeived New sample fate-> 200kS/s kj f,=100ks/s f s=200ks/s / < ra Q -5 c TO O i ra E V c,-»100ks/s V ca-+100ks/s Fig. 4. Steps (marked with squares) in the peratin f ITMS t adapt experiment's sampling rate when user defined events have been defined. Experimental results shw that if three input signals are acquired using the cnditins f Fig. 4, a sampling rate change appears, as an average, in the sample index 800 f the next blck. Fr the sampling rate used in the example, this means a latency time f 8 ms. This latency is measured by analyzing in which blck's sample the change in the mark channel appears. This latency is due t the internal prcesses f the system, which mainly cnsist f: reading the data samples frm the RTAI FIFO memry (? r FiF), prcess the data blck and generate the event t the EDSRM client (f p ), generate and receive the event message t finally update the sampling rate and mark channel vltage (f e i ) Therefre, the latency time depends n the number f samples t acquire, the event detectin algrithm implemented and the client-t-server latency time f the EDSRM mdules. In this example the cmmunicatin prtcl between the EDSRM mdules was implemented using TCP/IP trugh a netwrk cnnectin, but the next step is t implement it using the PCI bus t reduce its latency. In this example the DDPS mdule als sends the acquired data t a database strage server thrugh a netwrk cnnectin. One f the incnveniences f this apprach is the impact f the time needed t reprgram the cunter f the DAQ

5 card used t generate the sampling rate clck. With the hardware used it was detected that while the cunter is being reprgrammed its utput remains at a lw level, and thus n samples are acquired during that interval (mre less 500 (is) causing a small lss f data each time the sampling rate is changed. 4. Data reductin implementatin in ITMS The data reductin mechanism that was implemented in this applicatin cnsists f using the lssless data cmpressin algrithms based in peridic deltas These algrithms are applied t data blcks in the DDPS mdule befre sending them t the netwrk. The algrithms, develped in C, were integrated in Lab VIEW and cded using CINs. It must be nted that this means the ITMS can send three different data frame types thrugh the netwrk depending n the data frmat: binary, cmpressed binary and flating pint. In this particular applicatin the cmpressed binary frmat frame includes infrmatin abut the sampling rate, the cmpressin methd, the initial sample and the delta values. 5. Discussin Data acquisitin systems with adaptive sampling rate capabilities can be very interesting, if nt crucial, fr lng pulse r steady state experiments. The pssibility f having scalable DAQ systems with lcal multi-prcessing capabilities allws the develpment f highly efficient and cmplex data acquisitin applicatins riented t data reductin. The mdel presented here, based n the ITMS platfrm, in which the sample rate is cntrlled by a dc vltage, allws finding slutins t cmplex experiment requirements. Hardware slutins must be prpsed in rder t slve the prblems related t the lss f infrmatin during the shrt time needed t update the sampling rate clck. The slutin prpsed is the first step in the definitin f a mdel fr the develpment f AIL These can adapt their behaviur t the experiment tempral evlutin. References E. Barrera, M. Ruiz, S. Lpez, D. Machn, J. Vega, PXI-based architecture fr real time data acquisitin and distributed dynamic data prcessing, IEEE TNS 53 (3) (2006) M. Ruiz, E. Barrera, S. Lpez, D. Machn, J. Vega, E. Sanchez, Distributed real time data prcessing architecture fr the TJ-II data acquisitin system, Rev. Sci. Instrum. 75 (10) (2004) J. Vega, M. Ruiz, E. Sanchez, A. Pereira, A. Prtas, E. Barrera, Real-time lssless data cmpressin techniques fr lng-pulse peratin, Fusin Eng. Des. 82 (2007)