UNIT-II INTRODUCTION TO EMBEDDED SYSTEMS

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1 UNIT-II INTRODUCTION TO EMBEDDED SYSTEMS Embedded System: Def: An Embedded system is ne that has cmputer hardware with sftware embedded in it as ne f its mst imprtant cmpnent. The three main cmpnents f an embedded system are 1. Hardware 2. Main applicatin sftware 3. RTOS prcessrs in an Embedded System: General purpse prcessr Micrprcessr Micrcntrller Embedded prcessr Digital signal prcessr Media prcessr Applicatin specific system prcessr, Multiprcessr system using GPP and ASSP, GPP cre r ASIP cre integrated int either an ASIC r a VLSI circuit r an FPGA cre integrated with prcessr unit in a VLSI chip. Explanatin A prcessr has tw essential units Prgram Flw Cntrl Unit (CU) Executin Unit (EU) An embedded system prcessr chip r cre can be ne f the fllwing. a. Micrprcessr. b. Micrcntrller. c. Embedded Prcessr. d. Digital Signal Prcessr (DSP). e. Media Prcessr. HARDWARE UNITS IN THE EMBEDDED SYSTEMS: Pwer Surce and managing the pwer Mst systems have a pwer supply f wn. The supply has a specific peratin range r a range f vltages. Varius units in unzip fr place f Infatuatin t Embedded System in ne f the fllwing fur acceleratr are examples f embedded systems that d nt have their wn pwer supply v and cnnect t pi pwer-supply lines. 1Z; A charge pump cnsists f a dide in the series fllwed by a charging capacitr. The dide gets frward bias input frm an external signal. Real Time Clck (RTC) and Timers fr Varius Timing and Cunting Needs f the System a timer circuit suitably cnfigured is the system-clck, als called real-time clck (RTC). It is used by the schedulers and fr real-time prgramming. Mre than ne timer using the system clck (RTC) may be needed fr the varius

2 timing and cunting needs in a system. Clck Oscillatr Circuit and Clcking Unit(s) The Clck is an imprtant unit f a system. A prcessr needs a clck scillatr circuit. The clck cntrls the varius clcking requirements f the CPU, f the system timers and the CPU machine cycles Memries In a system, there are varius types f memries. They are as fllws: Internal RAI\4 f 256 r 5lZ bytes in a micrcntrller fr registers, temprary data stack Internal ROM/PROMIEPROM fr abut 4 KB t 16 KB f prgram External RAM fr the temprary data and stack Internal caches EEPROM r flash External ROM r PROM fr embedding sftware RAM Memry buffers Caches (in superscalar micrprcessrs) Pulse Dialer, Mdem and Transceiver Fr user cnnectivity thrugh the telephne line, wireless, r a system prvides the necessary interfacing circuit. It als prvides the sftware fr pulse dialing thrugh the telephne line, fr mdem intercnnectin fr fax, fr Internet packets ruting, and fr transmitting and cnnecting a WAG (Wireless Gateway) r cellular system. A transceiver is a circuit that can transmit as well as receive byte streams Linking and Interfacing Buses and Units f the Embedded System Hardware The buses and units in the embedded system hardware are needed t be linked and interfaced. One way t d this is t incrprate a glue lgic circuit. LCD and LED Displays System requires an interfacing circuit and sftware t display the status r message fr a fine, fr multi-line displays, r flashing displays An LCD screen may shw up a multilane display f characters r als shw a graph r icn An LCD needs little pwer. It is pwered by a supply r battery (a slar panel in the calculatr). LCD is a dide that absrbs r emits right n appreciatin f 3 V t 4 V and 50 r 60 Hz vltage pulses with currents less than 50 pa. An LSI (Lwer Scale Integrated circuit) display cntrller is ften used in the cise f matrix displays.

3 Embedded system design prcess: Requirements: We must knw what we are designing, the initial state f the design prcess capture this infrmatin fr use in creating the architecture and cmpnents. We gather an infrmal descriptin frm the custmer knwn as requirements and we refine the requirement int specificatin that cntain enugh infrmatin t design the system architecture. Requirement may be functinal r nn functinal requirements include Perfrmance: The speed f the system is majr cnsideratin fr the usability f the system and fr its ultimate cst. Perfrmance may be a cmbinatin f sft perfrmance metric and deadline by which a particular peratin must be cmpleted. Cst: Manufacturing cst Nn-Recurring Engineering

4 Physical size and Weight: An industrial cntrl system fr an assembly line may be designed t fit int a standard size with n limitatin and weight. A handheld device typically has tight requirement n bth size and weight that can mve t the entire system design. Pwer cnsumptin: Pwer can be specified in requirement states in terms f Architecture Cmpnents System Integratin Battery Life Describe the allwable vltage Validating Requirements: Checking that a system meets specificatins and fulfill its purpse. One gd way t refine the user interface prtin f a system requirement is t get a mck-up. Simple Requirement Frm: Specificatin: It serves as the cntract between the custmer and the architecture. These specificatins must be carefully written s that it reflects the custmer s requirements and it helps during design. Designers wh lack a clear idea what t build underg a faculty assumptin early in the prcess. Specificatin must be understandable Unclear specificatin will cause different types f prblems. Example fr specificatin: GPS system Architecture Design: The architecture is a plan fr the verall structure f the system. It will be used later t design the cmpnent that makeup the architecture. Name: Purpse: Input: Output: Functins: Perfrmance: Manufacture cst: Pwer: Physical size and weight: System Integratin: Once the cmpnents are build up then they are integrated tgether and see the wrking system. Bugs are determi ned during integratin. Careful attentin t inserting apprpriate debugging facilities during design can help ease system integratin.

Applicatins f each type f embedded system: Small Scale Embedded system A lng needle rtates elderly minute such that it 'returns t same psitin after an hur. A shrt needle rtates every hur.

5 Applicatins f each type f embedded system: Small Scale Embedded system A lng needle rtates elderly minute such that it 'returns t same psitin after an hur. A shrt needle rtates every hur. Such that it returns t same psitin after twelve hurs ACVM Stepper mtr cntrllers fr a rbtic system Washing r cking system Multitasking tys Medium scale embedded systems Ruter, a hub and a gateway Entertainment systems Banking systems Signal tracking systems Sphisticated embedded systems Embedded system fr wireless LAN Embedded systems fr real time vide Security prducts ES fr space lifebat The 8051 Micrcntrller is a Micrcntrller designed by Intel in 1980's. It was based n Harvard Architecture and develped primarily fr use in Embedded Systems. Originally it was

6 develped using NMOS technlgy but as thse requires mre pwer t perate therefre Intel redesigned Micrcntrller 8051 using CMOS technlgy and later versins came with a letter 'C' in their name, fr example: 80C51. Micrcntrller 8051 has tw buses fr prgram and data. Thus it has tw memry spaces f 64K X 8 size fr bth prgram and data. It has an 8 bit prcessing unit and 8 bit accumulatr. It als includes 8 bit B register as main prcessing blcks. It als have sme ther 8 bit and 16 bit registers. Micrcntrller 8051 have an built in RAM fr internal prcessing. This memry is primary memry and is used fr strage f temprary data. It is Vlatile memry i.e. its cntents get vanished when the pwer is turned OFF. Oscillatr: As we knw Micrcntrller is a digital circuit device, therefre it requires clck fr its peratin. Fr this purpse, Micrcntrller 8051 has an n-chip scillatr which wrks as a clck surce fr Central Prcessing Unit. As the utput pulses f scillatr are stable therefre it enables synchrnized wrk f all parts f 8051 Micrcntrller. Input/Output Prt: As we knw that Micrcntrller is used in Embedded systems t cntrl the peratin f machines. Therefre t cnnect it t ther machines, devices r peripherals we requires I/O interfacing prts in Micrcntrller. Fr this purpse Micrcntrller 8051 has 4 input utput prts t cnnect it t ther peripherals. Timers/Cunters: Micrcntrller 8051 has 2 16 bit timers and cunters. The cunters are divided int 8 bit registers. The timers are used fr measurement f intervals, t determine pulse width etc. Memry: Micrcntrller requires a prgram which is a cllectin f instructins. This prgram tells Micrcntrller t d specific tasks. These prgrams requires a memry n which these can be saved and read by Micrcntrller t perfrm specific peratin. The memry which is used t stre the prgram f Micrcntrller, is knwn as cde memry r Prgram memry. It is knwn as 'ROM'(Read Only Memry). Micrcntrller als requires a memry t stre data r perands temprarily. The

7 memry which is used t temprarily stre data fr peratin is knwn as Data Memry and we uses 'RAM'(Randm Access Memry) fr this purpse. Micrcntrller 8051 has 4K f Cde Memry r Prgram memry that is it has 4KB Rm and it als have 128 bytes f data memry i.e.ram. Central Prcessr Unit(CPU): CPU is the brain f any prcessing device. It mnitrs and cntrls all peratins that are perfrmed in the Micrcntrller. User have n cntrl ver the wrk f CPU. It reads prgram written in ROM memry and executes them and d the expected task. Bus: Basically Bus is a cllectin f wires which wrk as a cmmunicatin channel r medium fr transfer f Data. These buses cnsists f 8, 16 r mre wires. Thus these can carry 8 bits, 16 bits simultaneusly. Buses are f tw types: Address Bus Data Bus Address Bus: Micrcntrller 8051 has a 16 bit address bus. It used t address memry lcatins. It is used t transfer the address frm CPU t Memry. Data Bus: Micrcntrller 8051 has 8 bits data bus. It is used t carry data. Prcessr and Memry rganizatin 8051 Memry rganizatin is depends n type f architecture used. There are tw type f architectures are used in cntrller r prcessr generally : 1) Vn Neumann architecture 2) Harvard architecture Vn Neumann architecture The term Vn Neumann architecture, als knwn as the Vn Neumann mdel r the Princetn architecture. This architecture cnsist f address memry and data memry n a single unit is based n Vn Neumann architecture. Harvard architecture

8 Harvard architecture cnsist f prgram memry and data memry as separate unit. Thus fr accessing Harvard architecture we need separate address bus, data bus and cntrl bus is based n Vn Neumann architecture. Hence 8051 cnsist f tw separate memry units, prgram memry as well as data memry. Prgram memry rganizatin : The prgram memry rganizatin fr 8051 family is as shwn in fig. abve micrcntrller has an n chip internal prgram ROM f 4K size and if needed we can add an external memry f size 60K maximum by interfacing. Hence ttal 64K size memry is available fr 8051 micrcntrller. By default, the External Access (EA) pin shuld be cnnected Vcc its mean that instructins are fetched frm internal memry initially. When we crss the internal limit f memry (4K), cntrl f prgram will autmatically ges t external memry and remaining instructins will fetch frm external ROM. If we wants nly external memry i.e. t fetch instructin frm nly external memry means if we want bypass internal prgram ROM, then we have t must cnnect External Access (EA) pin t grund as shwn in fig. abve.

9 Data memry rganizatin : In the 8051 family, 8051 has ttal 128 bytes f internal data RAM and we can interface external data memry up t 64K. Hence, ttal size f data memry in 8051 can be upt external 64K + internal 128 bytes. Internal RAM f 8051 is divided int 3 parts:- 1) Register banks 2) Bit addressable area 3) Scratch pad area. There are 4 register banks in 8051 bank 0,1, 2 and 3. Each bank has 8 registers f 1 byte R0,R1 R7 respectively. Hence, register banks cnsist f the lwest 32 bytes f n chip RAM as shwn in fig. abve. At a time nly ne register bank can be selected fr peratins and bank registers are accessed using mnemnics R0..R1.. etc. By default register bank #0 is selected when we reset the system. The bit addressable area is 16 bytes next t register banks. We can access each bit separately f bit addressable area, Each bit have unique address f bit addressable area.the area f bit addressable space f 8051 is usually used t stre bit variables. address range 20H t 2FH (ttal 128 bits) is nthing but bit addressable area as shwn in fig. Each bits can be accessed frm 00H t 7FH within this 128 bits frm 20H t 2FH. Smetimes prgramming using bit addressable area saves wastage f memry. The upper 80 bytes are nthing but scratch pad area which is used fr general purpse string f data. Scratch pad area is in the address range 30H t 7FH. Scratch pad area can be used fr stack memry als if default stack area is insufficient. Interrupts in 8051 Micrcntrller The mst pwerful and imprtant features are interrupts in 8051 micrcntrller. In mst f the real-time prcesses, t handle certain cnditins prperly, the actual task must be halt fr sme

10 time it takes required actin and then must return t the main task. Fr executing such type f prgrams, interrupts are necessary. It entirely differs frm the plling methd wherein the prcessr must check sequentially each device and ask whether the service is required r nt while cnsuming mre prcessr time. Interrupts in 8051 micrcntrller are mre desirable t reduce the regular status checking f the interfaced devices r inbuilt devices. Interrupt is an event that temprarily suspends the main prgram, passes the cntrl t a special cde sectin, executes the event-related functin and resumes the main prgram flw where it had left ff. Interrupts are f different types like sftware and hardware, maskable and nn-maskable, fixed and vectr interrupts, and s n. Interrupt Service Rutine (ISR) cmes int the picture when interrupt ccurs, and then tells the prcessr t take apprpriate actin fr the interrupt, and after ISR executin, the cntrller jumps int the main prgram. Types f Interrupts in 8051 Micrcntrller The 8051 micrcntrller can recgnize five different events that cause the main prgram t interrupt frm the nrmal executin. These five surces f interrupts in 8051are: 1. Timer 0 verflw interrupt- TF0 2. Timer 1 verflw interrupt- TF1 3. External hardware interrupt- INT0 4. External hardware interrupt- INT1 5. Serial cmmunicatin interrupt- RI/TI The Timer and Serial interrupts are internally generated by the micrcntrller, whereas the external interrupts are generated by additinal interfacing devices r switches that are externally cnnected t the micrcntrller. These external interrupts can be edge triggered r level triggered. When an interrupt ccurs, the micrcntrller executes the interrupt service rutine s that memry lcatin crrespnds t the interrupt that enables it.

11 Interrupt Structure f 8051 Micrcntrller Upn RESET all the interrupts get disabled, and therefre, all these interrupts must be enabled by a sftware. In all these five interrupts, if anyne r all are activated, this sets the crrespnding interrupt flags as shwn in the figure. All these interrupts can be set r cleared by bit in sme special functin register that is Interrupt Enabled (IE), and this in turn depends n the pririty, which is executed by IP interrupt pririty register. Interrupt Enable (IE) Register: This register is respnsible fr enabling and disabling the interrupt. It is a bit addressable register in which EA must be set t ne fr enabling interrupts. The crrespnding bit in this register enables particular interrupt like timer, external and serial inputs. In the belw IE register, bit crrespnding t 1 activates the interrupt and 0 disables the interrupt.

TCON Register: In additin t the abve tw registers, the TCON register specifies the type f external interrupt t the 8051 micrcntrller, as shwn in the figure.

12 TCON Register: In additin t the abve tw registers, the TCON register specifies the type f external interrupt t the 8051 micrcntrller, as shwn in the figure. The tw external interrupts, whether edge r level triggered, specify by this register by a set, r cleared by apprpriate bits in it. And, it is als a bit addressable register. 1.Timer Interrupt Prgramming Timer 0 and Timer 1 interrupts are generated by the timer register bits TF0 and TF1. These interruptsprgramming by C cde invlves: Selecting the timer by cnfiguring TMOD register and its mde f peratin. Chsing and lading the initial values f TLx and THx fr apprpriate mdes. Enabling the IE registers and crrespnding timer bit in it.

13 Setting the timer run bit t start the timer. Writing the subrutine fr the timer fr time required and clear timer value TRx at the end f subrutine. 2.External Hardware Interrupt Prgramming 8051 micrcntrllers cnsists f tw external hardware interrupts: INT0 and INT1 as discussed earlier. These are enabled at pin 3.2 and pin 3.3. These can be edge triggered r level triggered. In level triggering, the lw at pin 3.2 enables the interrupt, while at pin 3.2 the high t lw transitin enables the edge triggered interrupt. This edge triggering r level triggering is decided by the TCON register that has been discussed abve. Theprgramming prcedure in 8051 is as fllws: Enable the crrespnding bit f external interrupt in IE register. If it is level triggering, just write the subrutine apprpriate t this interrupt, r else enable the TCON register bit crrespnding t the edge triggered interrupt whether it is INT0 r INT1. 3.Serial Cmmunicatin Interrupt Prgramming Serial cmmunicatin interrupts cme int picture when there is a need t send r receive data. Since ne interrupt bit is set fr bth TI (Transfer Interrupt) and RI (Receiver Interrupt) flags, Interrupt Service rutine must examine these flags t knw the actual interrupt. The lgical OR peratin f these tw flags (RI ands TI) causes this interrupt, and it is cleared by the sftware alne. Here, a special register SCON is used fr cntrlling cmmunicatin peratin by enabling the crrespnding bits in it. Cnfigure the IE register fr enabling serial interrupt Cnfigure the SCON register fr receiving r transferring peratin Write subrutine fr this interrupt with apprpriate functin and clear TI r RI flags with in this rutine.

It has hardware. It has application software.

It has hardware. It has application software. Q.1 What is System? Explain with an example A system is an arrangement in which all its unit assemble wrk tgether accrding t a set f rules. It can als be defined as a way f wrking, rganizing r ding ne