Arithmetic Transforms for Verifying Compositions of Sequential Datapaths

Transcription

1 Arithmetic Trasforms for Verifyig Compositios of Sequetial Datapaths Katarzya Radecka ad Zeljko Zilic McGill Uiversity, Motreal, Caada { ABSTRACT this paper, we address the issue of obtaiig compact caoical represetatios of datapath circuits with sequetial elemets, for the purpose of equivalece checkig. First, we demostrate the mechaisms for efficiet compositioal costructio of Arithmetic Trasform (AT), which is the uderlyig fuctio represetatio, used i moder word-level decisio diagrams. Secod, we itroduce a way of geeratig the caoical trasforms of the sequetial datapath circuits. Usig these priciples, we verib by AT highly sequetial Distributed Arithmetic (DA) architectures. 1. TRODUCTO Desig verificatio aims at providig a aswer to the questio: "Does the implemeted circuit coform to the specificatio?" Verificatios are ofte coducted through equivalece checkig. Uder this sceario, a caoical represetatio of the circuit is costructed ad compared agaist the descriptio obtaied from the specificatio. Origial equivalece checkig methods that relied o graph-based Biary Decisio Diagram represetatios were uable to deal with arithmetic circuits such as multipliers. However, efficiet word-level graphs like Biary Momet Diagrams (BMDs) [4] ad their geeralizatios [5] ca overcome this obstacle. Due to their word-level ature, the costructio from biary sigals is possible by backwards circuit traversal [6], but is geerally quite tedious. Further, sequetial circuits icludig arithmetic datapaths preset a obstacle to the efficiet represetatio. Related work i [9] partly overcomes these difficulties by usig uivariate realumber polyomial represetatios that ca deal with sequetial compoets. However, as oly real umbers ca be used i [9], represetatios are oly approximated. this paper we itroduce ew ways of geeratig the caoical descriptios of large datapath circuits. We propose techiques for compositioal verificatio of digital sigal processig (DSP) datapaths, cosistig of adders, multipliers, memories, etc., as i Figure 1. The goal of such verificatio is to assure correctess of the compositio of blocks. Blocks are either idividually verified, or iclude tellectual Property (P) cores that are oly give by their specificatios. Our method is based o Arithmetic Trasform (AT), which is a uderlyig represetatio used i word-level decisio diagrams, eablig the compact caoical descriptio of arithmetic circuits. The results are give i this paper i terms of AT, but also apply to graph represetatios. Sectio 3 we preset the extesios to AT that provide the cocise ad easily obtaiable descriptio of datapath arithmetic circuits, icludig sequetial oes. This allows us to develop the scheme for describig ad verifyig sequetial datapaths that have bee addressed maily with complex theorem provig or model checkig techiques [l], [7]. Sectio 5 we demostrate the efficiecy of our method at work o the example of highly sequetial Distributed Arithmetic (DA) circuits, that are well suited for field programmable gate array (FPGA) ad deep sub-micro circuit implemetatios. Figure 1 : A Datapath Example 2. ARTHMETC TRASFORM Arithmetic Trasform is a caoical polyomial represetatio of multi-output Boolea fuctios f : B" + B". To describe multi-output fuctios with a sigle polyomial, fuctio outputs are "grouped together" ito word-level (W) quatities, e.g. itegers, resultig i a pseudo-boolea fuctio f : B" W. Defiitio 1: Arithmetic Trasform (AT) of a pseudo- Boolea fuctio f : B" +W is a polyomial with arithmetic "+" operatio, word-level coefticiets c,,,~..,", biary iputs X,.., x ad biary expoets i,,...,i: that uiquely ad exactly iterpolatesf. The trasform coefficiet vector C = (c~,~~...~" } is obtaied by multiplyig the vector f of word-level fuctio /01$10.00 Q 2001 EEE 348

2 outputs with the trasform matrix T,,, C = T, * f, where T, is defied recursively by arithmetic Davio expasio: T, = [ 1, To =. (2) -',- T-1 To show that the polyomial with coefficiets geerated i this way recostructs exactly (iterpolates) a fuctio, ote that accordig to Equatio 1 AT is a liear polyomial i variables. For = 1, the coefficiets co ad C of a sigle-variable liear form f = co+clx are obtaied from cofactorsfo ad fl. By multiplyig the values with T, we get co=fo ad c =fi-fo, which is a more familiar form of Davio expasio. Matrix T, exteds this expasio recursively to -variable fuctios, oe variable at a time. Oce AT of a circuit implemetatio is geerated, the compariso to AT of the specificatio is straightforward. ts caoicity ad compact size for most arithmetic circuits, excludig the dividers, make AT very appropriate to use i equivalece checkig of datapaths. Further, the error correctig properties of AT facilitate its applicatio to verificatio by test vectors [8]. Hece, by usig AT, a cotiuum of verificatio methods ca be applied, icludig various combiatios of formal ad vector-based schemes. Additioally, as AT ca represet P core specificatios, verificatio of systems icludig proprietary P ca be performed as well. 2.1 Word Ecodig ad orm Fuctio AT accepts iputs as biary -tuples ad geerates outputs i the word-level form. A word-level ecodig is explicitly expressed by the umber orm fuctio 1: B" + W, which defies how a Boolea vector is iterpreted i the word-level domai. Table 1 cotais several commo iteger ad fractioal umber orms. Word umber orm 1x1 Usiged Sig Exteded 2's Complemet Lemma 1: Cosider a pseudo-boolea fuctio f:b"+w withaorm1 :B"+W.The, Wf 1 =f * Proof: By applyig the trasform to quatities i W, a iterpolatio polyomial is obtaied, such that for all iputs ATCf(xl, XZ.. x,)) = flxl, x2.... x,). 0 Example : AT of Multiplier. Let the iput bits to the usiged iteger multiplier be Xk ad Yk, k= 0,..., -1. ts AT is equal to the umber orm of the product: -1 AT(x*y)= xxk2k * zyk2k $X*y$X*y. + k=o k=o ote that the orm of the sum (product) of two umbers equals the sum (product) of their orms. Further, the orm of a arbitrary algebraic expressio is equal to the expressio applied to the orms of its compoets. 3. ARTHMETC TRASFORM EXTESOS We cosider the costructio of AT for the compositio of several blocks, Figure 2.a. To compose ATs of two blocks where the outputs of the first block are fed to the iputs of the secod oe, we must covert the word-level output of the first block ito a biary vector, Figure 2.b. The problem with this approach is that the biary ecodig has to be explicitly costructed at each iterface. o simple AT compositios are possible i this sceario. stead of usig the biary coversio, we propose the alterative solutio that allows the direct compositio of trasforms, as well as hadlig of sequetial circuits. To achieve these goals, we eed to itroduce two extesios to basic AT. - AT(B2(81(1))=? - a) AT of Block Compositio R =AT(Bl(l)) r T = RV S = AT(B20) c Table 1 : orm Fuctios for Commo Word Ecodigs Defiitio 2: Bialy ecodig (x,,x2...,x,) of a word w is the iverse ofthe orm fuctio, 1wl-l = (X, xq..., x, ). ote that there is o closed-form expressio for biary ecodig; istead, biary coversio algorithm must be applied to obtai w-'. Hece, there is o simple AT(1wl-l). Figure 2: aive Compositioal AT Costructio 3.1 First Extesio: Mixed Trasform Our first extesio facilitates the compositioal approach to represetig the complex datapaths. We allow the iputs to be a mix of biary, xi, ad word-level, wj, quatities, i.e., f(xl... x,,,w...wk). 349

3 Defiitio 3: Mixed AT (MAT) of fuctio J f : B" x W k + W is a polyomial with biary expoets il,... i ad el,... ek: that iterpolates$ We will use the MAT trasformatio whe some sets of iputs are kow to be word-level quatities, such as outputs of previous blocks. Lemma 2: The coeflciets of MAT ca be calculated usig the trasformatio give by Equatio 2, expaded aroud biary iput variables, with word-level iput variables uassiged, i.e., treated as symbols C(W,w2,-..wk)=T, * f. Pro03 Applicatio of the trasform to the quatities i B" results i a iterpolatio polyomial that, accordig to Lemma 1, is MAT(f(xl, x2,... x, W, w2,... wk)) = f( w1, w2,... wk)l. Assigig cocrete word-level values to uassiged word-level variables still preserves the orm fuctio, accordig to the orm properties. Hece, this trasform is equal to f which implies that the resultig MAT polyomial exactly iterpolates the fuctio. Example 2: MAT of MUX. A multiplexer (MUX) with iputs a, b ad the cotrol sigal x ca perform selectio of either bit- or word-level quatities a ad b. Arithmetic Davio expasio (Equatio 2) aroud variable x, leads to MAT(Mux) = a(1- x) + bx. This example also illustrates the use of MAT for a o-arithmetic fuctio. + MAT facilitates the compositio, by which the outputs of oe AT ca be directly used as iputs to MAT, Figure 3. For example, variables a ad b i Example 2 ca be give by ATs of previous blocks. To obtai the fial AT of the compositio, we eed to apply the followig coversio. r. -~ AT(B2(B1(1,),12)) MATB2) Proof: By usig orm of the quatities i W, we get a iterpolatio polyomial i biary iputs, with AT(f)= f. This is a correct ATU) accordig to Lemma 1. 0 Example 3: MAT of Adder. Cosider a usiged fractioal adder, where iput a is represeted at wordlevel, i.e., usiged fractioal, while iput b is treated as biary vector. The, by substitutig biary ecodig of a i the defiig MAT equatio, we obtai its AT as: MAT(a+b)=a+zbj2-' =z(a,+bj)2-' =AT(a+b). ote that "+" has the same meaig i AT ad MAT. To calculate AT of the whole combiatioal circuit, ATs should be geerated for each block fed by primary iputs, while MATS should be applied to all other blocks. The overall AT is created by substitutig AT trasforms for itermediate word-level quatities. 3.2 Secod Extesio: Sequetial Trasform To describe datapaths with sequetial compoets, we itroduce to MAT the otio of a timedfuctio. A timed fuctio A] represets the value off at the rh clock period. Defiitio 4: MAT Sequetial (MATS) is a MAT trasform MAT(f)[], of timed fuctio f at time istace. May datapath blocks are time ivariat. Hece, the timed trasform of arithmetic blocks will be exactly the same as the origial MAT trasform. The simplest role that the timed trasform plays is to represet the state iformatio kept i memory elemets. A defiig equatio for a memory is mour[] = mj,[- 1. Example 4: MATS of Add-Accumulate Loop. Cosider the additio i rh step, where oe of the summads is take from the primary iputs, while the other is supplied from the register storig the accumulated values of the previous -1 additios, Figure 4.a. Assume that the register has bee iitially reset. pdd dpaxulatelcq~ +,....-~-.... ' Figure 3: Use of MAT i Compositio of ATs V ail Lemma 3: AT(f) ca be obtaied from MAT of fuctio a) b) f : B" x Wk + W through the sytactical replacemets, Figure 4: Add- ad Multiply-Accumulate Loops word-level iput wi E is substituted by its To obtai MATS of the add-accumulate loop, cosider the biary ecodig -' : W + B", i.e., itermediate word-level fuctio A], represetig the iput to the register after additios. Assumig that the MAT( f (xi...,x,, wi -',..., wk -') = AT(f). free iput a[] is also a word-level quatity, the value of A] is give by the recurrece equatio: 350

4 f [] = ur] + f [- 13, f [O] = 0. The correspodig MATS is the: MATS( f )[] =a[] + MATS( f )[- 11, MATS( f )[O] = 0. After the rh additio, MATS of the add-ad-accumulate loop is obtaied as the followig solutio to the above recurrece equatio: = Ca[i]. + MATS (f>[] Lemma 4: MATS of a compositio of a combiatioal elemet described by fuctio f with sequetial blocks ca be obtaied from MATcf) by replacig each iput that is geerated by a sequetial block with its defiig MATS. Proof: Sice MAT describes the combiatioal fuctio of a block, with memory elemets discoected, the, by Defiitio 4, such a sytactical replacemet presets the correct fuctioality of the sequetial fuctio. 0 Corollary 1: MATS of sequetial fuctio f ca be obtaied from MAT of the combiatioal part off by replacig each MAT iput that is geerated by a memory elemet with its defiig MATS. Corollary 2: rf at least oe iput variable of combiatioal fuctio f is geerated by a sequetial block, the the trasform of the compositio, istead of MAT, eeds to be preseted as MATS:,,... wi..., w,)) = MAT( f (x,,... MATS(w,) MATS(( f ( x..., wk)) Lemma 5: MAT of a circuit at time istace ca be obtaied by solvig MATS as a recurrece equatio. Sequetial elemets eed to be iitialized. Proof: MATS represets the fuctio of a block at each time istace. By solvig the recurrece equatio, the circuit behavior at a give time istace is obtaied. Recurrece equatios describig sequetial elemets i datapaths posses forms that are easily solvable aalytically ad symbolically by tools such as Maple or Mathematica. Example 5: MATS of Multiply-ad-Accumulate (MAC) loop - a commo elemet of DSP datapaths. Cosider the trasformatio of the compositio performed over the MAC, Figure 4.b, usig previously derived MAT trasforms of its idividual blocks. puts to the MAC at the time istace i are -bit biary vectors x ad y, the output z is a biary vector of size 2. MATS of the multiplier block is defied for iputs occurrig at time istace i as: MATS(x*y)[i]= x~,[i]2~ * x ~ ~ [ =a[i]. i ] 2 ~ P=o The trasform of the accumulator-register loop, obtaied by solvig the same recurrece type as i Example 4 is: P=o Please ote that the above represetatio correspods to the MAC loop specificatio VERFCATO OF DATAPATHS A datapath of a typical DSP architecture, Figure 1, performs arithmetic ad logic operatios. ts mai buildig blocks are: register files, ROMs, shift registers, multiplexers, multipliers ad adders coected ito a MAC structure, as show i Figure 1. To verify the complete datapaths, we will rely o the verified implemetatios of its basic blocks, doe either through equivalece checkig [5], or vector-based methods [8]. For overall datapath verificatio, we ca use the library of datapath blocks, together with their trasforms. The trasform of each elemet oly depeds o its fuctioality, ad ot o the actual implemetatio. For example, AT of a adder is the same, for a ripple, lookahead or skip adder. The trasforms (AT, MAT or MATS) of the most commo arithmetic circuits were preseted i Examples 1-5. ext, we itroduce the algorithm to verify the datapath compositio from blocks. 4.1 Trasform of Complete Datapaths Havig defied trasforms of idividual blocks i a datapath, the automated costructio of the overall AT ca proceed by forward traversal from primary iputs, as show i Algorithm 1. For each block ecoutered, the trasform is costructed from its immediate iputs. Each combiatioal block depedig etirely o primary iputs requires oly AT descriptio (lie 4, Algorithm 1). Blocks with iputs geerated by previous blocks will be represeted i MAT form (lie 6, Algorithm 1) if oe of its iputs perform a sequetial fuctio, Corollary 2. Geerate MATS of the etwork of blocks 1. for each block B,i topological order Assig: iputs (6,) to output(predecessor(b,)) 4. if (combiatioa/(bj&& alliputs-primary) 5. f, = AT(6,); 6. if (combiatioa/(bj&& o-se9-iput) 7. f, = MAT(B,, assiged-iput-list); 8. else *sequetial(t3,)7 9. f, = MATS@,, assiged-iput-list); O. f, = reccurece-solve(f, ); 11. } 12. Overall-AT = f, Algorithm 1 : Compositio of Block Trasforms Every time a sequetial block is ecoutered, its recurrece equatio is solved symbolically. The outputs are the expressed i terms of the block iputs, MATS(w)[], at the time of their occurrece at the block iputs w. The iputs are the substituted by trasforms of 351

5 ~ ipits the previous blocks i the overall expressio. The process is repeated util all the blocks are traversed, ad all the outputs are expressed i terms of primary outputs of the circuit. 5. VERFCATO OF DSTRBUTED ARTHMETC CRCUTS Distributed Arithmetic (DA) refers to datapath architectures where the ier product of a vector by a costat is performed as a bit-serial operatio [lo]. DA leads to efficiet FPGA implemetatios of specialized DSP circuits like filters, but also of basic arithmetic fuctios, such as multipliers [3]. filter applicatios, the word-level quatities are usually fractios. Hece, the M-l siged umbers are represeted as: x = -xo + xi 2-', ad for usiged umbers, the sig digit xo is ot used. The calculatio of ier products of a vector of costats A& with iput vectors xk, k = 1, 2,...,h? M-l, y=ta,x,, where xj =-xjo+ cxj,2-' k= is performed bit-wise. stead of iputtig the whole M-bit xk vector i parallel, ad the executig the multiplicatio by a M-bit costat Ak, all vectors are serially shifted i. each cycle every shifted bit is "multiplied" i parallel by its costat Ak. Partial sums maitaied i this way do ot resemble the stadard partial results of ier product calculatios. The product: ( y=zajxj =CAj -x,;~ is trasformed by chagig the order of summatio ito Equatio 3 represets the form i which the ier product is calculated i the DA arithmetic. The multiplicatios i brackets, Equatio 3, do ot have to be calculated with multipliers. stead, bit products ca be pre-computed for all the possible combiatios of bits x,, of vectors x, ad stored i ROM. The, based o the actual combiatio of x,' amog all x,'s, the correspodig ROM locatio is addressed [lo]. Oe possible hardware implemetatios of the DA ier product of four 4-bit vectors is preseted i Figure Trasforms of Buildig Blocks of DA A typical DA circuit cosists of the followig blocks. Shift registers are used to serially iput the vector bits. ROMs store the pre-computed partial sums, ad addaccumulate loops maitai the partial results of the multiplicatio, Figure 5. + Trasforms of a few major datapath blocks were derived i Sectios 3.1 ad 3.2. ow, we preset the trasforms of the remaiig DA blocks. For presetatio purposes, we iitially assume that the sig bits are zero, or, equivaletly, that the usiged ecodig is employed. AT of ROM. The cotet of ROM represets the bit multiplicatio of a costat Ak by bit vector xk, k = 1,...,, Figure 5. t is easily verifiable from Figure 5 that, for the case = 4, AT of ROM is give by AT(ROM)=Aix, +A,x, +...+Ax = z A j ~ j, where each variable xj is oe-bit wide ad the coefficiets A,, j = 1,..., are fractioal umbers.... Figure 5: Distributed Arithmetic - ROM/Accumulator Structure MATS of Shift Registers. A shift register is a purely sequetial circuit, cosistig of a chai of storage cells. For each register, its discrete time defiig equatio is give as f[] = a[ - 11, where the iputs a[] are treated as bits. Buildig the shift register out of idividual storage cells amouts to composig the word-valued trasfer fuctios. For jrh shift register with M-1 stages, MATS at time k is MATS(SR(xj))[k] = xj(m-l-k). MATS of Add-Accumulate Sum with Delay Elemet. MATS of this block is calculated by costructig ad 1 solvig the recurrece: f[] = a[]+- f[ -11, f[o] = 0, 2 where variable a[] is a word-level ROM output quatity ad the iitial coditio i the register is 0. By solvig the recurrece equatio at time, we get: f[]=ca[i]*2'-" =Ca"]*2-'"-i', i=o 5.2 AT Descriptio of Complete Usiged DA The trasform of the complete circuit i Figure 5 is obtaied by forward traversal, followig Algorithm 1. The l=o 352

6 itermediate variables will be substituted i all the expressios durig the traversal. By substitutig the outputs of the shift registers to the ROM iputs, we obtai the followig timed expressio: MATS(ROM)[k]=xA.x. J j(m-1-k). ext, substitutig these variables, as the iputs to the addaccumulate sum results i: The overall fuctio AM-21 is completed at time istace M-2 as Equatio 4 at time M-2: M-2 AT(f) = MATS(f)[M -21 = CCAjXjcM-l-k,2-(M- -P). k=o The result is the same as i Equatio 3 (circuit specificatio) with the assumptio that the sig bits are zero. To verify that, we otice that by applyig the chage of idices of the first summatio, the fial AT is give by the expressio that is equivalet to Equatio 3: 5.3 AT Descriptio of Siged ad Ecoded DA The siged DA algorithm differs from the previous case i (M-Z) h step added at the ed of the executio, whe the sig bits are icorporated. The,f=AM-] is obtaied as AT(f) = MATS(f)[M - 11 = -ZAjxjo +MATS( f )[M This expressio is equal to Equatio 3; hece, the equivalece is prove. The same approach was used to prove the equivalece of additioal DA forms, icludig ecoded DA circuits from [O] that achieve the reductio i ROM sizes by alterative iteral umber ecodig. Each ew circuit ca have a differet, o-trivial DA implemetatio. The preseted method ca check the correctess of DA realizatio already o the algorithmic level. We implemeted Algorithm 1 i Mathematica, for its ease of itegratio with the recurrece solver rsolve (by M. Petkovsek), already icorporated i Mathematica. The obtaied represetatio is caoical ad compact. By comparig the sizes (measured i words) of the resultig AT with the sizes of ROMs employed i DA circuits, as i Table 2, we observe that the overall AT represetatio is logarithmic i the size of a ROM. The last colum presets worst case times spet o a 440MHz Ultra 10 workstatio with 128MB of mai memory i geeratig overall AT from ATs of DA compoets. As Mathematica is a iterpreter with lots of overhead, these times could be greatly reduced by compiled code. (4) # Terms Usiged Siged Ecoded Time ROM AT 1 ROM AT ROM AT [S k k 256 8k G 480 8G 512 Table 2: AT vs. ROM Sizes i DA mplemetatios 6. Coclusios We preseted two extesios to Arithmetic Trasform that facilitate the compositioal verificatio of sequetial datapaths. The first extesio makes the easy compositio of trasforms of idividual blocks possible, while the secod oe allows sequetial circuit represetatios. The compact caoical descriptios of large circuits ca be quickly obtaied by symbolic compositio of trasforms of idividual blocks. Verificatio of highly sequetial Distributed Arithmetic architectures was preseted usig these trasforms. We ited to apply the method to the larger classes of sequetial datapaths. 7. Refereces [l]m.d. Aagaard ad C-J. H. Seger, The Formal Verificatio of Pipelied Double-precisio EEE Floatig-poit Multiplier, Proc. EEEACM t l Co$ CAD, CCAD, pp. 7-10, [2] R. Amirtharajah, T. Xathopoulos ad A. Chadrakasa, Power Scalable Processig Usig Distributed Arithmetic, Proc. SLPED, pp , [3] A. Berkema, V. Owall, ad M. Torkelso, A Complex Multiplier with Low Logic Depth, EEE lt l. Co$ O Electroics, Circuits ad Systems, pp , [4] R.E. Bryat ad Y-A. Che, Verificatio of Arithmetic Fuctios with Biary Momet Diagrams, Proc. of 32 Desig Automatio Coferece, pp , [5] R. Drechsler, B. Becker ad S. Ruppertz, The K*BMD: A Verificatio Data Structure, EEE Desig ad Test of Computers, Vol. 14, o. 2, pp , April-Jue [6] K. Hamaguchi, A. Morita ad S. Yajima, Efficiet Costructio of Biary Momet Diagrams for Verificatio of Arithmetic Circuits, Proc. CCAD, pp.78-82, [7] J. D. Kim ad S-K. Chi, Assured VLS desig with formal verificatio, Proc. 12th Aual Co$ Computer Assurace, COMPASS, pp , [8] K. Radecka ad Z. Zilic, Usig Arithmetic Trasform for Verificatio of Datapaths via Error Modelig, Proc. of VLS Test Symposium, pp ,2000. [9] J. Smith ad G. De Micheli, Polyomial methods for allocatig complex compoets, Proc. Desig, Automatio ad Test i Europe, pp , [O] S.A. White, Applicatios of Distributed Arithmetic to Digital Sigal Processig: A Tutorial Review, EEE ASSP Magazie, pp. 4-19, July