APPENDIX A FOR SKEE3732 LABORATORY 1 SHEET

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1 APPENDIX A FOR SKEE3732 LABORATORY 1 SHEET Other documents that are referred within this document are located at the link The ATmega32/ATmega2A Architecture and Assembly Language A.1. Memory Specifications The AVR architecture (including Atmega32) has three main (block) memory spaces, the Data Memory and the Program Memory space. In addition, some most AVR (including the ATmega32) has an EEPROM Memory for data storage. All three memory spaces are separated from each other and each are addressed linearly (address is in incremental sequence). In this laboratory we are using only with the Data Memory and the Program Memory space in programs. Memory Map The memory map of a microcontroller is a diagram which gives the size, type and layout of the memories that are available in the microcontroller. The information use to construct the memory map is extracted from the datasheet of the microcontroller. The diagram below gives the memory map for three (3) blocks of memory spaces of the ATMega32. Figure A.1: ATmega32 (ATmega32A) Memory map A.2. The ATmega32 Architecture Importance of of knowledge of CPU Architecture CPU Architecture is needed by Assembly Language programmer to create effectively the codes of the program. To write the program, knowledge of the instruction set list is need to select what instruction to use. Instructions can be categorise by the function of the operation which are of different syntaxes for each different valid addressing mode of each category. 1

2 To use instructions, knowledge of valid CPU registers, memory map of available memory devices and Input/Output(peripherals device) registers, the valid addressing modes of each instruction that provide transfer of data between CPU registers, I/O registers and memory locations is needed. Some instruction requires implicit registers (not specified in instruction) and there are specific rule in using them, e.g. the MUL, BRxx, PUSH, POP, CALL and ROL instructions. To write functioning program, knowledge on CPU architecture is needed so that flow of program and access of data (from valid locations) are correctly implemented such that the locations and data size and sequence executions are validly implemented. ATmega32 and ATmega32A have the same architecture. Program data will be stored in the Application Program section (which is physically a flash RAM) and however non-volatile data can be stored in Program memory Space (Flash RAM) and volatile data can be stored in Data memory Space (which is physically a Static RAM or SRAM). RAM EEPROM Timers PROGRAM Flash ROM ALU PC: CPU Data Bus Program Bus Instruction dec. OSC Interrupt Unit Ports Other Peripherals I/O PINS Figure A.2: ATmega32 Built-up Architecture A.3. Program Memory The Atmega32 contains 32K (32768) bytes of On-chip In-System Reprogrammable Flash memory for program storage. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The figure below illustrates the Flash Memory. a. Instruction in Program Memory The Atmega32 instructions are 16 wide: when accessed by the CPU (using Program Counter) to address instruction, the Flash is organized as 16K x 16. Each addressed hold 2 bytes of data. The two bytes of each address are arranged in little endian order. 2

3 b. Data in Program Memory The Flash memory can also be used to store data (thus is non-volatile data not lost when power is removed). When accessed by the CPU (using Pointer Register Z), the Flash is organized as 32K x 8. Each addressed hold 1 bytes of data. So the absolute address to accessed byte size data is calculated by multiplying 2 with the physical Flash memory address: the lower byte of the word is the added with 1 (odd address). Addressing 16 bit Data Addressing 8 bit Data High Byte Low Byte $0000 Byte 0 Byte 1 $0000 Byte 0 $0001 Byte 2 Byte 3 $0001 Byte 1 $0002 Byte 4 Byte 5 $0002 Byte 2 $0003 Byte 3 $0004 Byte 4 $0005 Byte 5 $0006 $3FFE Byte Byte $3FFF Byte Byte Address of 8-bit data = Address of 16- bit data * 2 or Shift left value of address or (addr <<1). The high byte will take the even address (+0) and the high byte will take the odd address (+1) $7FFC Byte $7FFD Byte $7FFE Byte $7FFF Byte Only LPM and SPM instructions can be used used to access the program memory Figure A.3: Addressing 16 bit data and 8 bit data of the Program Memory. 3

4 c. Interrupt Vector Table Data in Program Memory In real application the address location 0x00 to 0x29 should be reserved for interrupt vector table as shown below. Table A.2 However program can be written on the vector table area, if its respective subsequent interrupt is not used (depending on application). Vector 1 is definitely at the initial instruction upon a RESET event. Address for vector 1 (a.k.a. RESET vector) is the initial value loaded into PC upon RESET. Reset is invoked on any of the following event: External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset. In this laboratory 1 and 2 RESET can be simulated as Power-on Reset (when Build and Run is executed in the Editor mode of the Atmel Studio) or External Pin (when Debug Reset menu is selected in the Debug Mode of the Atmel Studio) 4

5 d. Program setup for RESET The following are typical application of program setup for RESET when no other interrupt are used but we still want to reserve the vector table but completely use the rest of program memory.include m32adef.inc /*Register/Bit Definitions for the ATmega32A including names in Figure A.5(b). Sample file is in Reference Folder. However in Atmel Studio you do not need to declare this since it will be declared by the Atmel Studio Assembler. Atmel refers to the Device Selected (refer Section B.2(Step B3)) to determine the filename*/.cseg ;Start of Program Segment in Flash Memory jmp start ;Reset Handler.org 0x2a ;Set location counter to address $002A (for Atmega32) ;to skip around the interrupt vectors table start: ldi r20,high(ramend); Set Stack Pointer to top of RAM out sph,r20 ldi r20,low(ramend) out spl,r20 A.4. Data Memory Space Data Address Space $0000 $ $001F $ $005F $ General Purpose Registers Standard I/O Registers General purpose RAM (SRAM) 8 bit R0 R1 R2... R31 TWBR TWSR... SPH SREG I/O Address $00 $01 $3E $3F $FFFF Figure A.4 (1) 5

6 Figure A.4 (2) There are three category of devices mapped in the Data (SRAM) Memory Space. General Purpose Registers (GPR) Standard I/O Registers General Purpose RAM (Data Address Space) The first of the SRAM is reserved for General Purpose Registers in the ATmega32. These registers are connected to the ALU (Arithmetic Logic Unit) and are used to manipulate data. The registers are labelled R0 R31. The Register is divided into two group call Lower Registers and Upper Registers. A.5. Accessing devices mapped in Data Memory Space Mappings The GPRs and I/O Registers are mapped sequentially from address $0000 to address $005F in the Data Memory which is the RAM memory space is mapped from $0060 to $085F. The mapping of each respective register is as in shown Figure A.4 (2). a. The General Purpose Registers In normal case these GPRs are identified by their labels (R0, R1, R2,... R31). The lower 16 registers, R0 R15, work just the rest of the registers with the exception of loading immediate data. The upper 16 registers, R16 R31, have additional capabilities defined in Instruction Set Reference. These registers have access to the full range of the Data Memory, ALU, and additional peripherals. R16 R31 have access to immediate (constant) data using the LDI instruction. These registers will be the ones that get the most use throughout your program. To move data into or out of these registers, the various different Load and Store instructions are needed. All arithmetic instructions work on these registers. GPRs are used need as source or destination location when accessing I/O registers and SRAM and Program Memory data. Transfer of Data between I/O registers, SRAM locations and Program Memory locations require GPRs to be used as intermediate location. 6

7 Arithmetic, logical and bitwise operation of data on I/O registers and SRAM locations needed to be load to a GPR to implement the operation on the GPR as intermediate location being stored back to original location, or any other To access these registers you use Register Direct Addressing mode by using their labels, (Section A.7(b)) though you can use Data Memory Addressing Mode (Section A.7(c)) by using their Data memory address. b. I/O Registers Location The Labels of Special I/O registers, their I/O address (under I/O ) and their Data Space Address (under Mem ) in Figure A.5 (b): I/O registers are Special Function Registers are registers in the ATmega32 that either control or monitor the various components of the chip. Most of the Special Function Registers have read/write capabilities; check the datasheet for the ATmega32 for more details. These register reside in the ATmega32 I/O Memory and as such, require the IN and OUT instructions to read and write to these registers. The ATmega32 is equipped with 4 Digital I/O Ports labelled Port A through Port D. Each port has its own unique capabilities such as External RAM Addressing, PWMs, Timers, and Counters. Unfortunately, this document will only cover the basics that are common with each port. Digital I/O register will be used in Laboratory 2 thus explained more in Laboratory 2. Figure A.5 (b.1): I/O Registers Location on Pins of ATmega32 7

8 Figure A.5 (b.2): I/O Registers Location on I/O Memory and Data Memory of ATmega32 c. Internal SRAM (Data Memory) The memory space is addressed from 0x60 to 0x085f. To access these memory spaces you must use any of the five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, Indirect with Postincrement. In the General Purpose Register file, registers R26 to R31 feature the indirect addressing pointer registers (X, Y, and Z). To access Data memory locations, you must use Data Memory Addressing Mode(Section A.6(c). A.6. Processor registers In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers: PC: 16-bit program counter SP: 16-bit stack pointer SREG: 8-bit status register X, Y, and Z pointer registers: 8-bit segment registers that are prepended to 16- bit addresses. a. Program Counter The Program Counter (PC) is a register that is a part of all central processing unit (CPU) or microprocessor. All microcontrollers contain a microprocessor and thus has a program counter. The purpose of the program counter is to hold/store (to point to) 8

9 the address of the next instruction to be executed by the microcontroller's microprocessor. The PC is automatically incremented to hold/store (to point to) the address of the next instruction after execution of the current instruction. When the program begins, the PC must contain the address of the first instruction in the program which is the RESET event. When a RESET event occurs, the content of the reset vector is loaded into PC. A JMP instruction at the reset vector address can be set to jump the bootloader program starts. Program instructions are stored in consecutive program memory locations. To jump elsewhere in the program, Program Flow Control (branch/jump/call/return) instruction is used. Note: These are jump instructions that can modify the PC (e.g., the PC must change when calling or returning from some other routine). The CPU clock determines the execution time of instructions which a series of execution can be calculated to generate a required delay. b. Status Register (SREG) The Status Register or SREG contains the important information about the ALU such as the Carry Bit, Overflow Bit, and Zero Bit. These bits are set and cleared during ALU instructions. This register becomes extremely useful during branching operations. The following table details the bit assignments within the SREG. Status Register are: Figure A.5 (c) Is 8 bits wide. Contains information associated with the results of the most recent ALU operation. Carry flag (C) set if CY from most signficant bit (MSB) or a borrow occur on subtracts. 9

10 Often used when adding numbers that are larger than 8 bits. Here we need to use an add with carry instruction (ADC) to add the next most significant byte. Zero flag (Z) set if result is zero. BREQ instruction says branch if zero flag is set. BRNE instruction says branch if zero flag is not set. Negative flag (N) set if MSB is one. A copy of the most significant bit of an arithmetic result. Arithmetic instructions change the flags Data transfer instructions do not change the flag. The instruction set documentation identifies which flags each instruction may modify. Overflow flag (V) set if 2's complement overflow occurs. An overflow occurs if you get the wrong sign for your result, e.g., = ( = ). Note: whenever the carry into the MSB and the carry out don't match, we have an overflow. Sign bit (S) s = N EXOR V, and shows the true sign of a comparison. Half carry flag (H) is set when carry occurs from b 3 to b 4. Used with binary coded decimal (BCD) arithemtic. This is an internal carry from additions. T Bit copy. Special bit used by load (BLD) and bit store (BST) instructions use this bit. I Interrupt flag. Set when interrupts are enabled. c. The AVR Stack Pointer The AVR ATmega32 stack pointer (SP) consist of two I/O register SPL (Stack Pointer Low) and SPH (Stack Pointer High). The size of the stack pointer depends on the amount of the ATmega32 data memory. The stack pointer is 16-bits wide but is accessed through the two register, SPH:SPL. Stack Pointer points to the location where the next data can be stored in the CPU stack. CALL, RCALL, PUSH and POP instructions uses and modify the Stack Pointer when executed. Figure A.5 (b) d. The Pointer Registers: X, Y and Z-Registers The last six of the General Purpose Registers have additional functionality. They serve as the pointers for indirect addressing. The ATmega32 has a 16-bit addressing scheme that requires two registers for the address alone. The AVR RISC structure supports this scheme with the X, Y, and Z-Registers. These registers are the last six General Purpose Registers (R26-R31). The following table details the register assignments: 10

11 Figure A.5 (d) A.7. Addressing Modes An addressing mode specifies how to determine/calculate the effective memory address of an operand by using information held in registers and/or constants contained within an instruction or elsewhere. Instruction formats are of 3 types: Implicit: No operand specified in the instruction, but the instruction execute a defined function on one or more of a defined GPRs, Pointer Registers, CPU register or Memory location. E.g. NOP and RET Single Operand: E.g. INC R0 Two operand: LDI R16,0x20, STS 0x200,R0 and MOV R0,R20. Operand can be of a constant or variable. There are four types of variables that can be declared as operand: GPRs, I/O registers, Data SRAM (GPRs, I/O registers and Data Memory are mapped in here too) and program Memory. Each of these devices are accessed by each specific individual mode. As for GPRs and I/O registers, though the have the own individual mode, the can be accessed by using the Data Memory Addressing mode because they are mapped in the Data Memory space. Addressing mode define the operand of the instruction (Refer section A.7) and for each operand, there is a specific instruction that that is defined to use each of these individual modes. All addressing mode is instruction specific which can be identified by their operands specification in the Instruction Set Summary (Section A.7) a. Immediate Addressing Mode The Immediate addressing mode is only valid as source operand (mandatory) only and is a constant. The destination operand must be of any the upper 16 GPRs (R16 thru R31). E.g LDI R16,0x30 or CPI R31,3 Where: Source is an 8 bit constant that taken as the data. Immediate addressing mode can be identified by the operands Rd,K and Rdl,K. b. GPRs Addressing mode There are two modes: (a) Register Direct or Single Register Rd (Single operand or Implicit Operand Instructions) E.g. INC R0 Single Register addressing mode can be identified by the operands Rd. (b) Register Direct, Two Registers Rd and Rr (Two Operand Instructions) E.g. MOV R0,R16 Register addressing mode can be identified by the operands Rd,R. c. Data Memory Addressing Modes There five different addressing modes for the data memory: 11

12 1. Direct or Data Direct Direct addressing mode can be identified by the operands Rd,k or k,rr which are used in instruction LDS and STS respectively. k is taken as the absolute address where data can be taken from (for LDS Rd,k instruction), or written to (for STS k,rr instruction). 2. Indirect Indirect addressing mode can be identified by the operands Rd,X, Rd,Y, Rd,Z, X,Rr, Y,Rr or Z,Rr which are used either in instruction LD and ST only. X, Y and Z are pointer registers The content of the specified pointer register in the instruction is taken as the address where data can be taken from (for LD instruction), or written to (for ST instruction). 3. Indirect with Displacement Indirect with Displacement addressing mode can be identified by the operands Rd,X+q, Rd,Y+q, Rd,Z+q, X+q,Rr, Y+q,Rr or Z+q,Rr which are used either in instruction LDD and STD only. X, Y and Z are pointer registers The content of the specified pointer register in the instruction after being added with q, is taken as the address where data can be taken from (for LDD instruction), or written to (for STD instruction). 4. Indirect with Pre-decrement Indirect with Pre-decrement addressing mode can be identified by the operands - X,Rr, -Y,Rr or -Z,Rr which are used either in instruction ST only. X, Y and Z are pointer registers The content of the specified pointer register in the instruction after being decremented by 1, is taken as the address where data taken from Rr can be written to (for ST instruction). 5. Indirect with Post-increment. Indirect with Post-increment addressing mode can be identified by the operands Rd,X+, Rd,Y+ or Rd,Z+ which are used either in instruction LD only. X, Y and Z are pointer registers The content of the specified pointer register in the instruction is taken as the address where data can be taken from (for LD instruction) to be written to Rd. After the transfer the pointer register will be incremented by 1. In the Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the X, Y or Z register. All instructions that use Data Memory Addressing Modes take two operands and one of the operand must be a GPR. When using indirect addressing modes with pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented by the execution of the instruction. The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of internal data SRAM in the ATmega32 are all accessible through all these addressing modes d. I/O Memory Addressing Modes The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. 12

13 I/O Registers within the address range $00 - $1F are directly bit accessible using the SBI and CBI instructions. These addresses are Equates to labels in m32def.inc. The valid names are given in Figure A.5(b). In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as data space using LD and ST instructions, $20 must be added to these addresses. All instructions that uses I/O Memory Addressing Modes takes two operands, and one of the operand must be a Register Direct Addressing Modes. e. Program Memory Addressing mode There are three modes: (a) Program Memory Constant Addressing using the LPM and SPM Instructions (b) Program Memory with Post-increment using the LPM Z+ Instruction f. Direct Program Addressing Mode The operand in JMP and CALL instruction is Direct Program Addressing. E.g. JMP k and CALL k. PC k g. Indirect Program Addressing Mode The implicit operands in IJMP and ICALL Indirect Program Addressing. These instruction have no operands. The source operand is the Z register and the destination operand is the PC (Program Counter). PC Z h. Relative Program Addressing Mode The operand in RJMP and RCALL instruction is Relative Program Addressing. E.g. BRNE k, RJMP k, and RCALL k There is only one operand which is the source operand and is a 12-bit constant. The destination operand is implicit and it is the PC (Program Counter). PC PC k A.8. AVR Instructions SET Instructions of a processor when executed determine what task the processor should do. A group of instructions which is arranged to perform a certain algorithm becomes a useful program. Instruction must be written according to its format following its hardware design which is specified in the processors in the instruction set reference manual. The references for the AVR 8-bit microcontroller is in file Atmel AVR 8-bit Instruction Set manual 2014.pdf (but refer to Atmega32 Reference manual.pdf pp for list of instruction supported on ATmega32/ATmega32A), which is categorised as below: 1. Arithmetic and Logic Operation Instructions 2. Data Transfer Instructions 3. Bit and Bit Test manipulation Instructions 4. Branch instructions a.k.a. Program Flow Control Instructions 13

14 a. Arithmetic and Logic Operation Instructions Instruction from this category allows 8-bit arithmetic or logic operation on a GPR (the destination operand). Instructions are specific for source operand which can be either Immediate (a constant) or Register Direct. Result from instruction in this category is stored in Status Register (either of the H, S, C, V and Z flag) can be used by the conditional Branch Instruction to determine the flow of a program. Table A8(a): Arithmetic and Logic Operation Instructions b. Data Transfer Instructions Except for LDI Instruction, instruction from this category allows transfer of 8-bit data between GPRs and Data Memory, I/O Memory or Program Memory. If data need to me transferred between Data Memory, I/O Memory or Program Memory, a GPR has to be used as the intermediate storage to implement the transfer. 14

15 Table A8(b): Data Transfer Instructions 15

16 c. Bit and Bit Test manipulation Instructions Instruction from this category allows specified bits of an 8-bit Number on a GPR or the Status Register (the destination operand) to be changed or tested. Result from instruction in this category is stored in Status Register (either of the H, S, C, V and Z flag) can be used by the conditional Branch Instruction to determine the flow of a program. Table A8(b): Bit and Bit Test manipulation Instructions 16

17 d. Branch instructions (Program Flow Control Instructions) Instruction from this category when executed, changes the Program Counter, either conditional or unconditional thus allowing a program to executes with a decision whether to jump or not. By using proper decision making in the codes, structured block (IF, IF-Then-Else, While Loop, Do-While loop, For Loop, Repeat Loop and Switch- Case) can be implemented. Table A8(d): Branch instructions (Program Flow Control Instructions) 17

18 e. Instruction Format The Instruction format of an ATmega32 microcontroller is specified in Instruction Set Summary (refer Section A.7). The Instruction must have an Opword specified from the Instruction Set s Mnemonics and may be followed with one of the following operand specification depending on the Opword: 1) No Operand (Example Instruction s Opword Mnemonics: NOP, CLC) 2) One Operand (Example Instruction s Opword Mnemonics: CLR R0, INC R1, JMP here) Depending on the instruction the operand may be the: a. The destination b. The source and destination operand. c. Source to an implicit destination 3) Two Operand (Example Instruction s Opword Mnemonics: MOV, LDI, STS) The valid source and destination operand is determined from the Instruction s Opword specified in Instruction Set Summary (refer Section A.7) In this Laboratory, we will not use all but only some basic instruction which will be used to help us understand a few of the Addressing Modes for the ATmega32 microcontroller. 18

19 A.9. Basic Assembler Directive The Assembler supports a number of directives. The directives are not translated directly into opcodes. Instead, they are used to adjust the location of the program in memory, define macros, or initialize memory and so on. Assembler-Directives control the assembler, they don't create any own code. The leading dot must be in column 1 of the line. An overview of the basic directives is given in the following table. Table A9(d): Basic Assembler Directive Segment Directive Description Header Code EEPROM SRAM Everywher e.device Defines the type of the target processor and the applicable set of instructions (illegal instructions for that type trigger an error message, syntax:.device AT90S8515).DEF Defines a synonym for a register (e.g..def MyReg = R16).EQU.SET.INCLUDE.CSEG.DB.DW.LISTMAC.MACRO.ENDMACRO.ESEG.DB.DW.DSEG.BYTE.ORG.LIST.NOLIST.INCLUDE.EXIT Defines a symbol and sets its value (later changes of this value remain possible, syntax:.equ test = , internal storage of the value is 4-byte- Integer) Fixes the value of a symbole (later redefinition is not possible) Includes a file and assembles its content, just like its content would be part of the calling file (typical e.g. including the header file for device ATmega32:.INCLUDE "m32adefdef.inc") Start of the code segment. All valid declaration using.db and.dw only that follows is assembled to the code segment and will be stored the program memory space(flash Memory). Inserts one or more constant bytes in the code segment (could be numbers from , an ASCII-character like 'c', a string like 'abcde' or a combination like 1,2,3,'abc'. The number of inserted bytes must be even, otherwise an additional zero byte will be inserted by the assembler.) Insert a binary word in the code segment (e.g. produces a table within the code) Macros will be listed in the.lst-file. (Default is that macros are not listed) Beginning of a macro (no code will be produced, call of the macro later produces code, syntax:.macro macroname parameters, calling by: macroname parameters) End of the macro Assemble to the EEPROM-segment (the code produced will go to the EEPROM section, the code produces an.eep-file) Inserts one or more constant bytes in the EEPROM segment (could be numbers from , an ASCII-character like 'c', a string like 'abcde' or a combination like 1,2,3,'abc'.) Inserts a binary word to the EEPROM segment (the lower byte goes to the next adress, the higher byte follows on the incremented address) Assemble to the data segment (here only.byte directives and labels are valid, during assembly only the labels are used). All valid declaration that follows is assembled to the data segment and will be stored the DATA memory space(sram) Reserves one or more bytes space in the data segment (only used to produce correct labels, does not insert any values!) Defines the address within the respective segment, where the assembler assembles to (e.g..org 0x0000) Switches the listing to the.lst-file on (the assembled code will be listet in a readable text file.lst) Switches the output to the.lst-file off, suppresses listing. Inserts the content of another source code file, as if its content would be part of the source file (typical e.g. including the header file:.include "C:\avrtools\appnotes\8515def.inc") End of the assembler-source code (stops the assembling process) 19

20 Refer to or file AVR Assembler User Guide.pdf for examples. A.10. Assembly Language An assembly language is a low-level programming language for computers, microprocessors, microcontrollers, and other programmable devices. It implements a symbolic representation of the machine codes and other constants needed to program a given CPU architecture. This representation is usually defined by the hardware manufacturer, and is based on mnemonics that symbolize processing steps (instructions), processor registers, memory locations, and other language features. An assembly language is thus specific to certain physical (or virtual) computer architecture. An assembler converts each assembly language statement into the corresponding machinelanguage statement. Assembly language is an alphanumeric representation of machine code. Below is an example of a AVR assembly code written in assembly language. Each line of the code is an instruction telling the microcontroller to carry out a task. ADD R16, R17 ; Add value in R16 to value in R17 DEC R17 ; Minus 1 from the value contained in R17 MOV R18, R16 ; Copy the value in R16 to R18 END: JMP END ; Jump to the label END The instructions used in writing programs in assembly language are not general but specific to the microcontroller. Each company provides a set of instructions for there microcontrollers. AVR 8-bits microcontrollers have a common instruction set. Refer to file Atmel AVR 8-bit Instruction Set manual 2014, the datasheet for complete reference on AVR 8-bits microcontrollers. Please note that not all instructions are available to all microcontrollers. The set available to each AVR microcontroller is given in the specific device datasheet. For ATmega32/ATmega32A valid instructions are given between pp A.11. The Editor Assembler programs are written with an editor. The editor just has to be able to create and edit ASCII text files. Some features of the editor are that it can detect errors (usually syntax errors): Errors, that the assembler later detects, are reported along with the line number in the text file. Line numbers is useful for reference when discussing your code with someone else. Typing errors are largely reduced, if those errors are marked with colours. It is a nice feature of an editor to highlight the components of a line in different colours. The Atmel Studio 6 is integrated with an editor that recognizes instructions automatically and uses different colours (syntax highlighting) to signal user constants and typing errors in those instructions (in black). Storing the code in an.asm file provides nearly the same text file; colours are not stored in the file. A.12. Assembler & Source Files The Assembler works on source files containing instruction mnemonics, labels and directives. The instruction mnemonics and the directives often take operands. Code lines should be limited to 120 characters. 20

21 Every input line can be preceded by a label, which is an alphanumeric string terminated by a colon. Labels are used as targets for jump and branch instructions and as variable names in Program memory and RAM. An input line may take one of the four following forms: 1. [label:] directive [operands] [Comment] 2. [label:] instruction [operands] [Comment] 3. Comment 4. Empty line A comment has the following form: ; [Text] Items placed in braces are optional. The text between the comment-delimiter (;) and the end of line (EOL) is ignored by the Assembler. Labels, instructions and directives are described in detail in the following sections. A.13. Good Practice to Organize Code When writing AVR assembly programs it is a good practice to organize code in four columns as shown in the code below. This has the benefit of your program being easier to read/debug by you and others. ;Col_1 Col_2 Col_3 Col_4 ADD R16, R17 ; Add value in R16 to value in R17 DEC R17 ; Minus 1 from the value contained in R17 MOV R18, R16 ; Copy the value in R16 to R18 END: JMP END ; Jump to the label END Column 1 (Col_1) is used for labels. Labels are basically markers use by the programmer when indicating to the microcontroller to jump to a specific location in the code. Column 2 (Col_2) is used for the microcontroller instructions. Column 3 (Col_3) is used for arguments operated on by the instruction in column 2. Column 4 (Col_4) is used for comments. Note here that a semi-colon ";" is put in front of each comments. That is the semi-colon indicate that the statement that follows it in the same line is a comment. Note: There are no restrictions with respect to column placement of labels, directives, comments or instructions. A.14. Comments A comment starts with a semicolon, double slash or enclosed by the \* and the *\ character. All that follows behind on the same line will be ignored by the assembler. If you need to write a comment over multiple lines, start each line with a semicolon. So each assembler program may start like this: \* *\ Prog.asm, Program to do for this Lab 1 Written by Zuraimi bin Yahya, last change: Put comments around all parts of the program, be it a complete subroutine or a table. Within the comment mention the special nature of the routine, pre-conditions necessary to call or run the routine. Also mention the results of the subroutine in case you later will 21

22 have to find errors or to extend the routine later. Single line comments are defined by adding a semicolon or double slash behind the comments on the line. Like this: ;Comments using semi-colon LDI R16,0x0A ;Here something is loaded //Comments using double slash MOV R17,R16 //and copied somewhere else A.15. The Assembler The Atmel Studio Assembler assembles error free codes written in Assembly Language into Machine Language which are stored in the.hex file and.eep file which may be used to dounload the assembled codes to AVR s Flash Memory or EEPROM of the AVR chip using a suitable programmer, when required (will be covered in Laboratory 2). The myfile.lst will be generated if selected which allow you to see the machine code together with the assembly language, but Atmel Studio provide a better altenative by providing the Disassembley View (refer section B.4 of Appendix B) which allow you to see both machine code and assembly language as you debug the program (refer section B.9 of Appendix B). Among advantage of disassembly view is that you will be able to see the absolute values of labels used in the Assembly Language which sometime is needed to determine address of locations or immediate values of labels. EDITOR PROGRAM myfile.asm ASSEMBLER PROGRAM myfile.eep myfile.hex myfile.map myfile.lst myfile.obj DOWNLOAD TO AVR s EEPROM DOWNLOAD TO AVR s FLASH 22

23 About ATmega32 Digital I/) ports 23