ΕΠΛ 605 Εργαστήριο 5. Παναγιώτα Νικολάου 11/10/18. Slides from: Rajagopalan Desikan, Doug Burger, Stephen Keckler, Todd Austin

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1 ΕΠΛ 605 Εργαστήριο 5 Παναγιώτα Νικολάου 11/10/18 Slides from: Rajagopala Desika, Doug Burger, Stephe Keckler, Todd Austi

2 Simulators Simulatio is the process of desigig a model of a real system ad coductig experimets with this model for the purpose of either uderstadig the behavior of the system ad/or evaluatig various strategies for the operatio of the system. A architectural simulator is: Itroductio to Simulatio Usig SIMAN (2d Editio) a tool that reproduces the behavior of a computig device Why we use a simulator? Leverage a faster, more flexible software developmet cycle Fuctioal simulators implemet the architecture. Perform real executio Implemet what programmers see Performace simulators implemet the microarchitecture. Model system resources/iterals Cocer about time Do ot implemet what programmers see 2

3 What is Sim-Alpha? sim-alpha: executio-drive simulator Executio-drive simulatio is the most accurate simulatio techiue Detailed simulatio of the memory system ad the processor pipelie are doe simultaeously. It models the implemetatio costraits ad the performace low-level features i Alpha

4 EV6 Pipelie 4

5 Pipelie stages Fetch stage & Slot stage : Istructio cache access Fetch_width umber of istructios per cycle (default:4) Static assigmet of istructios Cotrol istructios access the brach predictor. Map stage: Idetifies the iput ad output registers Checks for availability of reorder buffer etry, iteger or floatig poit issue ueue etry, physical output register ad load or store ueue etry (if istructio is load or store). If iput physical registers are ready, istructio is placed i ready ueue. Issue stage: Picks istructios from ready ueues, checks the availability of fuctioal uits ad issues the istructio to FUs. Register read latecy is charged here. Evets are set up for ueue etry release ad istructio completio. 5

6 Pipelie Stages (Cot.) Writeback stage: Wakes up the depedet istructios whe a producig istructio completes. Load istructios access the D-cache Mispredictios are idicated i the correspodig reorder buffer etry Commit stage: Retires istructios from reorder buffer Examies the head of reorder buffer for mispredictios ad flushes the pipelie i these cases. 6

7 Basic structures The mai loop of the simulator, located i simulate.c File: fetch.c Accesses the istructio cache ad fetch a umber of istructios (fetch_width) per access

8 Basic structures The mai loop of the simulator, located i simulate.c File: slot.c Static assigmet of istructios to either upper or lower subclusters Cotrol istructios access the brach predictor

9 Basic structures The mai loop of the simulator, located i simulate.c File: map.c Idetifies the iput ad output registers Checks for availability of reorder buffer etry, iteger or floatig poit issue ueue etry, physical output register ad load or store ueue etry (if istructio is load or store). If iput physical registers are ready, istructio is placed i ready ueue

10 Basic structures The mai loop of the simulator, located i simulate.c File: issue.c Picks istructios from ready ueues, checks the availability of fuctioal uits ad issues the istructio to FUs. Register read latecy is charged here. Evets are set up for ueue etry release ad istructio completio.

11 Basic structures The mai loop of the simulator, located i simulate.c File: writeback.c Wakes up the depedet istructios whe a producig istructio completes. Load istructios access the D-cache Mispredictios are idicated i the correspodig reorder buffer etry

12 Basic structures The mai loop of the simulator, located i simulate.c File: commit.c Retires istructios from reorder buffer Examies the head of reorder buffer for mispredictios ad traps ad flushes the pipelie i these cases.

13 Basic structures The mai loop of the simulator, located i simulate.c File: evet.c Schedule the memory code At the begiig of each cycle this fuctio checks for memory operatios completig this cycle

14 Code Structure Code for each pipelie stage i a separate.c file Each.c file has correspodig.h file cotaiig fuctio prototypes, costats, ad exter statemets for global variables. 14

15 Usig sim-alpha List of some optios foud i sim-alpha o o o o o o o -cofig Cofiguratio file to use -max:ist Maximum umber of committed istructios to simulate -fastfwd Number of istructios to fast forward (Caches are ot kept warm durig this phase) Processor core cofiguratio -mach:fre Freuecy of simulated machie fetch:width Number of istructios to fetch each cycle slot:width Number of istructios which ca be slotted per cycle -cache:defie - <ame>:<sets>:<bsize>:<subblock>:<asso>: <repl>:<lat>:<tras>:<#resources>:<rescode> 15

16 Small example of a cofiguratio file (small part) #CPU Freuecy-mach:fre # Set issue ad commit widths -issue:itwidth -issue:fpwidth -commit:width 4 # Iteger ist issue width(i ists) 2 # fp ist issue width(i ists) 4 # commit width(i ists) # cache cofiguratio -cache:defie -cache:defie -cache:defie DL1:256:64:0:4:l:3:vipt:0:1:0:Obus IL1:256:64:0:4:l:1:vivt:0:1:0:Obus L2:4096:64:0:8:l:12:pipt:0:1:0:Membus -prefetch:dist 0 # Number of blocks to prefetch o a icache miss -res:delay 0 # flush caches o system calls -cache:flush false # defies ame of first-level data cache -cache:dcache DL1 # defies ame of first-level istructio cache -cache:icache IL1 # umber of regular mshrs for each cache -cache:mshrs 8 16

17 How to use Sim-Alpha(cot..) -cofig -max:ist -fastfwd Most commo Optios Cofiguratio file to use Maximum umber of committed istructios to simulate Number of istructios to fast forward before start simulatio. Note the caches are ot kept warm durig this phase Example:../alpha-sim/sim-alpha -cofig cof.cfg -max:ist /cpu2006_434.zeusmp_kehoste_Alpha_gcc411_O