SRI VENKATESWARA COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION VLSI Design (EC2354) QUESTION BANK UNIT I Part A(2 marks)

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1 SRI VENKATESWARA COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION VLSI Design (EC2354) QUESTION BANK UNIT I Part A(2 marks) 1. State any two differences between CMOS and Bipolar technology 2. Compare CMOS and BICMOS logic. (Dec 2013) 2. Draw the stick diagram for an n type enhancement mode transistor 3. What is latch up problem in CMOS CIRCUIT? 4. What is the advantage of SOI CMOS process? 5. List any two layout design rules. (May 20 14) 6. How do you prevent latch up problem 7. What is LOCOS.Draw the energy band diagram of the components that make the MOS? ( MAY 20 11) 8. What is silicide 9. What is Polycide 10. What are the steps involved in manufacturing of IC? 11. What are the processes involved in photolithography. 12. What are the various CMOS technologies? 13. What is the special feature of Twin Tub process. 14. What is meant by Interconnect.What are the types of Interconnect. 15. What is stick diagram 16. What are the cells available in primitive library? 17. what is channel Ion implantation. 18.wy tunneling current higher for NMOS than PMOS.(Dec 2012) 1For an NMOS with vt=0.7v and if vgs=2v,vds=3v.whether it works in saturation region? (dec 2011) 19.what is DRC and LVS rule 20.What is layout editor? 21.Define threshold voltage 22. How inversion layer is formed 23. Draw the symbol of n-mos and draw I-V characteristics of MOS. (May 20 12) 24. Define Noise margin. 25. What is body effect? (Dec 2011) 26. Define rise time. 27. Draw the symbol transmission gate 28. Draw the symbol of tristate inverter 29. What are the three modes of n-mos enhancement transistor. (May 20 12) 30.What is Impact Ionization? 31 What is sub threshold current 32.What is drain punch through effect 33. What is static power dissipation? 34. Write an expression for power dissipation in CMOS inverter

2 36. Give the expression for rise time and fall time in CMOS inverter.draw DC transfer characteristics of CMOS inverter.(dec 2013) 37. Compare nmos and pmos device.what are CAD issues. (May 20 13) 38.write the equation of channel length modulation. (May 20 11) 39.Draw I-V characteristics of MOS. (May 20 13) 40.What are non ideal effects of MOS? (May 20 14) PART-B(16 marks) 1.Explain the various steps in fabrication of N-channel MOSFET. ( MAY 20 11) 2.(a) Explain N-well process with neat diagrams. (Dec 20 12) (b)explain source drain and isolation steps of cmos. (May 20 11) 3. Explain with neat diagram Twin tub process 4. Explain SOI process with neat diagram. and its advantage.(nov-2012) 5. Draw the layout and stick diagram of (i) NAND GATE (ii) NOR GATE(ii)Buffer(iv)xor gate 6. Explain latch up and methods to prevent it. Write short notes on a) Design hierarchies b) CAD tools sets 7. What are the various interconnect methods? Explain with diagram. 8. With neat diagram explain the steps involved in the p-well process of CMOS fabrication 9. Discuss the lambda based design rules for CMOS transistor. (May 20 12) 10. Implement the function y=[ab(b+c)] using cmos technology 11. Explain the working principle of n-mos enhancement transistor with various modes of operation. (May 20 12) 12. Derive the equation for threshold voltage of a MOS transistor and threshold voltage in terms of Flat band voltage 13. Derive the Drain to source current in the non saturated and saturated regions of operation of an n-mos transistor. (Dec,May 20 11,2014) 14. Briefly explain about drain punch through and fowler Nordheim tunneling and Impact on ionization 15. Explain pass transistor and transmission gate. 16. Calculate the threshold voltage for a transistor at 300K for a process with a silicon substrate with NA=1.80x10 16, silicon dioxide thickness 200A,assume Φms=-.9v,Qfc=0 17. Explain the switching characteristics of CMOS inverter with neat sketches 18.Explain with neat layout diagram the design rules of CMOS inverter. (AU 20 11) 19.Write short note on(a) channel length modulation. (may 20 11) (b)sub threshold current,narrow channel effect. (May 20 11) (c)body effect,short channel effect. (May,Dec20 11,2012) (d) velocity saturation and mobility degradation.

3 20. Explain the CMOS inverter DC characteristics. (Dec,May 20 11,2012,Nov-2013) 21. Write short notes on transmission gate 22.Explain the various CMOS process enhancement. (May,Dec 20 11,2014) 23.Discuss the lambda based design rules for NMOS transistor and draw the layout for a three input NAND gate 24.With a neat diagram explain the C-V Characteristics MOS gate and diffusion capacitance model. (Dec20 14) 24.Explain electrical properties of MOS transistor in detail.(nov-2013) 25.Define and derive the transconductance of nmos transistor. 26.For an NMOS with vt=0.16vv,tox=0.2x10-6 cm,εox=3.4,εsi=11.7,vsb=2.5v, ni=1.5x10 10 /cm 3,na=3x10 16 /cm3.determine the shift in threshold voltage caused by body effect.(dec 2012). 27. NMOS transistor with vt=0.7vv,tox=10nm,εox=3.9,mobilitu=520,w/l=8. Calculate Ids for vgs=2v,vds=1.2v.(dec 2011). UNIT-II PART-A 1. State the difference between constant field scaling and lateral scaling.(may 2013) 2. Define logical effort. 3. Define effort delay,parasitic delay,contamination delay and propagation delay 4. Define edge rate 5. Draw the RC model of PMOS and NMOS 6. Define wire pitch and aspect ratio 7. Define power dissipation.(dec 2013) 8. What is the effect of supply voltage and temperature variation on CMOS system performance.(dec 2012) 9. What is sheet resistance. What is cross talk delay 10. What is electro migration and self heating 11. What is soft error 12. What is the cause of charge sharing(refer circuit pitfall topic) 13. What is minority carrier injection and back gate coupling(refer circuit pitfall topic) 14. What are the effects of delay and power on scaling? (May 20 11) 15. Write tphl and tplh expression. (May20 11) 16. What is the use of monte carlo simulation(refer PSPICE topic) 17. What are the various levels of device model in pspice(level1,level2,level3) (May 20 13) 18. Define elmore delay model 19. Define scaling and mention its type.(dec 2013) 20. Define linear delay,effort delay and electrical effort. 21. Define path electrical effort,path effort,path delay 22. What is dynamic power and static power dissipation.mention the causes for dissipation.(dec 2012)

4 23. Define activity factor. 24. What is the effect of cross talk delay. Define hot carriers 25. What is latch up effect(may20 12) 26. What is the cause of supply noise voltage 27. What is design margin. (Dec20 13) What is device modeling. (May 20 13) 29. Calculate path effort for the given cuircuit 27.calculate path effort for the given circuit 28. What are the effects of delay and power on scaling? (may20 11) PART-B 1.Estimate the rising and falling propagation delays of a 2-input NAND gate and 2 input NOR gate using the elmore delay model. (may 20 13) 2..Estimate the rising and falling propagation delays of a CMOS-Inverter(Nov-2013) 3a).Write short notes on (i)design margin (ii) Latchup effect and methods to prevent it. (may,dec 20 11,2014) 4.calculate the logical effort for NAND gate, NOR gate and Inverter 5. calculate the parasitic delay for NAND gate, NOR gate and Inverter 6.Briefly discuss about transistor scaling, lateral scaling, interconnect scaling field and voltage scaling. (AU 20 11,2012) 7.Design a CMOS inverter and MOS transistor using P-SPICE. 8.write a pspice program to calculate the(i) fanout of 4-inverters(ii)To measure power and energy of cmos inverter. 9.Explain about device and circuit characterization(refer p-spice topic)

5 10.write short notes on reliability,transistor sizing and circuit pitfalls. (may,dec 20 11,14,Nov-2012) 11.write a pspice program to calculate gate capacitance 12.Explain dynamic and static power dissipation and methods to reduce it. (Nov-2013) 13.Briefly discuss about the interconnect layer s performance in modern VLSI systems. 14. Estimate the minimum delay of the path from A to B in Fig. (shows below) and choose transistor sizes to achieve this delay. 15. A metal wire in 180 nm has 5 mm long 0.32µm wide and sheet resistance 0.05Ω/square,cpermicron =0.02fF/ µm.construct 3 segment π model for this metal wire. 16.Expalin device model and characterization. (May 20 14) 17.Explain parasitic capacitance model in PSPICE. (Dec20 12) 18.Explain pspice interconnect simulation and circuit simulation in pspice. (Dec2014) 19.Discuss the principle of constant field and lateral scaling.write the effects of scaling methods on device characterization.(nov-2012) 20.Discuss the equation to model Ids equation and diffusion capacitance of MOS(Dec 2012). UNIT-III PART-A 1. Implement y=ab+cd using AOI22 gate 2. What is Hi skew inverter and L0 skew inverter 3. Implement a D- flipflop using CMOS logic. 4. What are the qualities of an ideal sequencing method.(dec 2012) 5. Write the advantages of dynamic circuit family 6. What is monotonicity problem in dynamic circuit 7. What is the use of keeper circuit in domino logic 8. What is the speed advantage of VLSI family.(dec 2012) 9. Write the rules for combining timing types(refer static sequencing element) 10. What is the advantage of skew tolerant domino cicuit when compared to traditional domino circuit.(may 2014) 11. Draw the diagram of CMOS bistable element and its time domain behavior.(may 2011) 12. What is stable clock,valid clock,qualified clock in two phase timing types. 13. What is the use of synchronizer. (May 20 13)

6 14. What is metastable state 15. What is time borrowing concept 16. What is arbiter circuit and draw its circuit 17. Draw transmission gate diagram. (Dec 20 11) 18. State various sequencing methods 19. What is jamb latch 20. Draw the circuit diagram of sense amplifier 21. Draw pseudo nmos inverter. (May20 11) 22. Write advantages of flipflop. (May20 11) 23. What are the criteria for low power design.(may 2014) 24. Design i bit dynamic register using pass transistor logic.(dec 2013) 25. What is bubble pushing concept 26. Part B 1. Discuss about sequencing methods and compute the maximum and minimum delay timing constraints of sequential circuits. 2. Briefly discuss about synchronizer circuit.explain how synchronizer is used to communication between asynchronous systems 3. Compare traditional sequencing and skew tolerant domino circuits.(may 11) 4. Write short notes on two phase timing type 5. Discuss about pulsed latch 6. Disuss about conventional CMOS flip flops and pulsed and resettable latches. (AU 20 14,Nov 2012) 7. Explain the dynamic logic and domino logic with examples. 8. Explain (a)(i)cvsl (ii) pseudo nmos logic (May 20 11) (iii)dual rail domino logic(iv)pass transistor logic (b) dynamic logic and NP-domino logic. (Dec20 11) 9. Briefly discuss about the following with an example i)cvsl (ii) pseudo nmos logic (iii)dual rail domino logic(iv)pass transistor logic 10. Briefly discuss about the following with an example(i)dynamic logic(ii)p/n ratio logic(iii)np-domino logic(iv)modl(multiple output domino logic(nov-2012) 11. Explain skewed gates and find gu(logical effort-rising transition),gd for NAND gate and NOR gate 12. Explain BICMOS logic, SSDL LOGIC, ECDL LOGIC 13. Draw the transistor level schematic of one bit full adder circuit and explain.(dec 11) 14. Write the principles of low power logic design. (May 20 11) 15. Explain negative edge triggered Master slave Dflip flop. (May 20 12) 16. Explain pipelining concept in sequential circuit. (Dec 20 13) 17. Explain the design of latches and flip flop. (Dec 20 14) 18. Compare various circuit families. (May 20 14) 19. Explain the methods to reduce Static and dynamic power dissipation in CMOS circuits.(nov-2012) 20. Write notes on sequencing dynamic circuits.(nov-2012) 21. Implement Y=(A+B)(C+D) using CMOS logic and NAND gate using Pseudo - NMOS logic(nov-2013).

7 22. Explain the design of D-latches using transmission gates(nov-2013) 23. Implement 2-bit non-inverting dynamic shift register usingbpass transistor logic.(nov-2013) Unit IV Part A. 1. What is schooming process? 2. Mention the levels at which testing of a chip can be done.(dec 2012) 3. Mention the physical defects that occur in a chip? 4. What is meant by fault models? 5. What is stuck at -1fault and stuck-at-0 fault? (May 20 12) 6. What is meant by controllability and observability? 7. What is fault grading? 8. What are the approaches in design for testability? 9. Mention the common techniques involved in ad hoc testing? 10. What are the scan-based test techniques? (May 20 11) 11. What are the self-test techniques or BIST? (Dec 20 11) 12. What is known as IDDQ testing? (May 20 11) 13. What is logic verification?( (May 20 13) 14. What is Boundary scan? 15. What is the Test Access Port? 16. Write guidelines on MUX partition technique. (Dec 20 11) 17. What is the TAP controller? 18. State the need for testing. (May 20 14).Draw the boundary scan input logic diagram. 19. What is the aim of Adhoc test technique? 20. Compare functionality test and manufacturing test. (Dec 20 11) 21. What are text fixtures. (May 2012, 14) 22. Differentiate testers and test fixtures.(dec 2012). PART-B 1. Explain manufacturing test principles. (May 20 11,Nov 2013)) 2. write short notes on controllability,observability,fault model,atpg,fault grading,delay fault testing (Nov-2012) 3. With neat diagram describe the design strategies for testing(dft) the CMOS device or explain adhoc,scan based,built in self testing (AU 20 11,2012,Nov-2012) 4. Explain in detail on system level testing technique or boundary scan testing. (May 20 13,2014,Nov-2013) 5. Discuss about the various scan based testing. (serial scan,parallel, random, LSSD)

8 6. Briefly discuss about BILBO(Dec 20 13) 7. Write short notes on test fixtures and test program 8. Disuss about silicon debug principle. (May 20 12,Nov-2012) 9. Explain stuck at faultand ATPG with example 10. Explain built in self testing and IDDQ testing(may 20 11) 11. What is PRBS.Explain with an example. (Dec 20 12) 12. Explain how to detect a stuck at fault with examples.(nov-2012) UNIT-V PART-A 1.Give the difference between continuous and procedural assignment in Verilog 2.Why do you require sensitivity list 3.What is task in verilog 4.What are the data types in verilog 5.What is net in verilog 6.Define port 7.Define logic synthesis 8.Give the difference between blocking and non blocking statements.(dec 2013) 9.What are the values in verilog.(dec 2013) 8.What are gate primitives(may 20 13) 9.What is design hierarchy 10.Write the verilog coding for half adder. (May,Dec 20 11,2012) 11. Give the syntax for (i) array declaration (ii) case statement with example 12.Define module and give the syntax for it with example. 13.write gate delay specification. (May 20 11) 14..What are thee design models in verilog 15.Name the types of timing control in verilog 16.Give the syntax for initial block and always block with example 17.Compare structural and switch level model in verilog. (May 20 13) 18.What are procedural assignment in verilog.( (May20 14) 19.Give an example of implicit continuous assignment in verilog.(dec2012). 20.Name various system task in verilog. PART-B 1.With a neat flow chart explain the VLSI design flow 2.Explain the syntax of conditional statements in verilog HDL with example 3.Explain in detail behavioral and RTL modeling(may20 14) 4.Write the verilog program for a full adder circuit using the three models 5.Write a verilog program for 3 to 8 decoder in gate level description 6.Write a verilog program for 4 bit/8 bit ripple carry adder using full adder(nov-2013) 7.Give brief account of timing control and delay in verilog. (Dec,May 2012, 20 14)

9 8.Give a verilog structural gate level and behavioural description of two bit comparator. 9.Explain about data flow model and delay specification synatx in assign statement with example.(dec 2012) 10.Explain switch level model with example 11. write behavarial model verilog code for 1x8 demux(may 20 14) 12.Write a switch level verilog program for 2x1 multiplexer 13. Write a switch level verilog program for 2x1 multiplexer using two input NOR gate (May 20 11) 14. Write a switch level verilog program for CMOS inverter(dec 20 11) 15. Write a switch level verilog program for two input Nand gate(dec20 11) 16.Explain for loop,while loop,repeat and forever loop and if else statements with example. (May 20 14) 17.Write a verilog program for(i) equality detector(ii)d-flip flop (iii) 4x1 multiplexer using 2x1 muliplexer 18.Design 4x1 mux using case statement and conditional operator 19. (a)expalin verilog operators (b)write verilog code for 4x1 mux using Nand gate. (May20 13) 20. Write short notes on Implicit continuous assignment. (May 20 13) 21. Write verilog code of Dlatch,Positive edge triggered flipflops. (AU 20 11,Nov-2013) 22.Write verilog code for (a)priority encoder (b) 4 bit equality detector(dec,may 20 13) 23.Write verilog code for (a)2 bit comparator (May 2013) 24.Implement 4x1 mux in data flow model. (Dec 20 12) 25Draw an active high 2/4 decoder using NOR gates and write verilog gate level implementation. (Nov 2012) 26.Describe the three ways of specifying delays in continuous assignment statement(nov 2012) 27.Write the data flow model for 4x1 mux using verilog(nov 2012) 28.Implement 2x4 decoder using NOR logic and write verilog code.(dec 2012). 29.Implement 8 bit shift register using positive edge trigered dff and write verilog code.(dec 2013) 30.Design 4x16 decoder using 3x8 decoder.