Outline of today s lecture. EEL-4713 Computer Architecture Designing a Multiple-Cycle Processor. What s wrong with our CPI=1 processor?

Transcription

1 Outline of today s lecture EEL-7 Computer Architecture Designing a Multiple-Cycle Processor Recap and Introduction Introduction to the Concept of Multiple Cycle Processor Multiple Cycle Implementation of R-type Instructions What is a Multiple Cycle Delay Path and Why is it Bad? Multiple Cycle Implementation of Or ediate Multiple Cycle Implementation of Load and Store Putting it all Together EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross Abstract view of our single cycle processor What s wrong with our CPI= processor? op Main Arithmetic & Logical Inst Reg File mux mux Reg File n_sel Next fun Instruction Fetch Equal Register Fetch Src Ext ctr control Mem Mem Access RegDst Reg. Wrt Data Mem Result Store Load Inst Reg File mux Data Mem mux Critical Path Store Inst Reg File mux Data Mem Branch Inst Reg File cmp mux Long Cycle Time All instructions take as much time as the slowest Reg File looks like an FSM with as state EEL-7 Ann Gordon - Ross Real memory is not so nice as our idealized memory cannot aays get the job done in one (short) cycle EEL-7 Ann Gordon - Ross

2 Drawbacks of this single cycle processor Overview of a multiple cycle implementation Long cycle time: Cycle time is much longer than needed for all other instructions. Examples: R-type instructions do not require data memory access Jump does not require operation nor data memory access Need for multiple functional units Can t share functional units for multiple operations in the same instruction E.g., instruction/data memory, adders (,, branch target, etc.) EEL-7 Ann Gordon - Ross The root of the single cycle processor s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle 6 EEL-7 Ann Gordon - Ross - Cycle time: time it takes to execute the longest step - All the steps have similar length This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete (for now) - Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction What and when: When designing multi-cycle implementations, you must think about: What to do on each cycle When results are ready for next cycle What to do on each cycle: Aays need to fetch instruction Aays need to decode instruction (know what to do next) Next need to perform actual operation (varies from instruction to instruction) E.g.: - Load will require address calculation, memory read, reg write - Branch will require comparison and update - R-type will require operation, reg write Overview: State Diagram Read mem. with address calculated above Computes rs+imm Fetch and store in IR =+ LWmem Latch data read from memory in rt or Write rt to memory address calc. above Decode operation Index registers Register operands In busa, busb RExec ype has inputs and control set, can compute Latch computed result in rd Finish branch Calculate the Target address Select mux, Write Exec has inputs and control set, can compute Latch computed result in rt Finish 7 EEL-7 Ann Gordon - Ross 8 EEL-7 Ann Gordon - Ross

3 Clk,,, Op, Func ctr Example: the five steps of a Load instruction 9 EEL-7 Ann Gordon - Ross Clk-to-Q New Value Old Value Instruction Access Time New Value Delay through Logic New Value Old Value New Value busa busb Old Value Instruction Fetch Instr Decode / Old Value Old Value New Value Src Old Value New Value Old Value Reg. Fetch Delay through er & Old Value Address Data Register File Access Time New Value New Value Delay Address Old Value New Value Data Access Time busw Old Value New Reg Wr Register File Write Time Multicycle datapath Similar to the single-cycle datapath; use latches for instruction and branch target address signals generated for multiple clock cycles per instruction - FSM Wr= WrCond= =x BrWr= =x = IRWr= RegDst=x = = Target Rb busa Reg File WrAdr busw busb << Beq Op ype 6 Func SelB= 6 6 : = EEL-7 Ann Gordon - Ross Overview: State Diagram Read mem. with address calculated above Computes rs+imm Fetch and store in IR =+ LWmem Latch data read from memory in rt or Write rt to memory address calc. above Decode operation Index registers Register operands In busa, busb RExec ype has inputs and control set, can compute Latch computed result in rd Finish branch Calculate the Target address Select mux, Write Exec has inputs and control set, can compute Latch computed result in rt Finish Cycle : Fetch : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross

4 Instruction fetch cycle: beginning Every cycle begins right AFTER the clock tick: mem[] <:> + Instruction fetch cycle: end Every cycle ends AT the next clock tick (storage element updates): IR <-- mem[] <:> <-- <:> + Clk Clk You are here! Wr=? One Logic Clock Cycle Use the main Wr= One Logic Clock Cycle You are here! Clk =? WrAdr Dout Din IRWr=? Clk op=? Clk = IRWr= WrAdr Din Dout Clk Op = Add EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross Instruction Fetch Cycle: Overall Picture. Latch IR=mem[] Fetch and. Set =+ store in IR : Wr, IRWr =+ x: WrCond RegDst, MemR Others: s Wr= WrCond=x = BrWr= = = IRWr= = Target busa WrAdr busb SelB= Cycle : Register fetch, decode : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : EEL-7 Ann Gordon - Ross 6 EEL-7 Ann Gordon - Ross

5 Register Fetch / Instruction Decode busa <- RegFile[rs] ; busb <- RegFile[rt] ; can be also be used to compute branch target address (next slide) in this cycle (latch target); register compare done on next cycle Wr= =x WrCond= = WrAdr Go to the 7 EEL-7 Ann Gordon - Ross Op Func IRWr= 6 6 RegDst=x 6 = Rb busa Reg File busw busb =x =x SelB=xx Op=xx Register Fetch / Instruction Decode (Continue) busa <- Reg[rs] ; busb <- Reg[rt] ; Target <- + SignExt(6)* Generate control signals Wr= =x Beq ype WrCond= = WrAdr 8 EEL-7 Ann Gordon - Ross : IRWr= Op 6 Func 6 RegDst=x 6 = : BrWr, SelB= x: RegDst,, Others: s = Rb busa Reg File busw busb << =x = Decode operation Index registers Register operands In busa, busb SelB= BrWr= Target Cycle : Branch completion : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, 9 EEL-7 Ann Gordon - Ross :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Branch Completion if (busa == busb) Wr= <- Target =x WrCond= = WrAdr EEL-7 Ann Gordon - Ross IRWr= RegDst=x 6 =x Op=Sub SelB= x:, MemReg RegDst, : WrCond = Rb busa Reg File busw busb << Finish branch Calculate the Target address Select mux, Write = = SelB= BrWr= Target Op=Sub

6 Cycle : ype execution : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : R-type Execution has Output <- busa op busb RExec : RegDst inputs and control set, Jump SelB= Op=ype can compute x:, Wr= WrCond= =x BrWr= =x = IRWr= RegDst= = = Target JumpAddr Rb busa Reg File WrAdr busw busb << Funct 6 =x =x Op=ype SelB= EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross Cycle : ype completion : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Latch R-type Completion computed Op=ype result in R[rd] <- Output : RegDst, rd sela SelB= Wr= WrCond= x:, =x BrWr= =x = IRWr= RegDst= = = Target Rb busa Reg File WrAdr busw busb << 6 =x = Op=ype SelB= EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross

7 Cycle : execution : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Execution Op=Or Op=Or Exec : output <- busa or Ext[6] :,, Wr= WrCond= =x BrWr= =x = IRWr= RegDst= = = Target Rb busa Reg File WrAdr busw busb << 6 = =x Op=Or EEL-7 Ann Gordon - Ross 6 EEL-7 Ann Gordon - Ross Cycle : completion : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Completion Latch Finish Op=Or computed result in Reg[rt] <- output x:, rt : Wr= WrCond= =x BrWr= =x = IRWr= RegDst= = = Target Rb busa Reg File WrAdr busw busb << 6 = = Op=Or 7 EEL-7 Ann Gordon - Ross 8 EEL-7 Ann Gordon - Ross

8 Cycle : Address calculation : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: 9 EEL-7 Ann Gordon - Ross : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Address Calculation : Computes rs+imm output <- busa + SignExt[6] Wr= WrCond= =x BrWr= =x = IRWr= RegDst=x = = Target Rb busa Reg File WrAdr busw busb << EEL-7 Ann Gordon - Ross 6 = =x Cycle : access, store : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Write rt Access for Store : SWmem to memory address calc. mem[ output] <- busb above Wr= WrCond= x:,regdst =x BrWr= =x = IRWr= RegDst=x = = Target Rb busa Reg File WrAdr busw busb << 6 = =x EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross

9 Cycle : access, load : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: EEL-7 Ann Gordon - Ross : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Access for Load : LWmem Read mem., with address calculated Mem Dout <- mem[ output] above Wr= WrCond= =x BrWr= = = IRWr= RegDst= = = Target Rb busa Reg File WrAdr busw busb << EEL-7 Ann Gordon - Ross 6 = =x Cycle : access, load : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, EEL-7 Ann Gordon - Ross :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Write Back for Load Latch data read from :, memory in rt Reg[rt] <- Mem Dout x: Wr= WrCond= =x BrWr= =x = IRWr= RegDst= = = Target Rb busa Reg File WrAdr busw busb << 6 EEL-7 Ann Gordon - Ross 6 = =

10 Wr Putting it all together: Multiple Cycle Datapath WrCond BrWr IRWr RegDst Target WrAdr 6 Rb busa Reg File busw busb << SelB Op Putting it all together: State Diagram : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem, :, x: : x:,regdst : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Op=Or Finish x:, : 7 EEL-7 Ann Gordon - Ross 8 EEL-7 Ann Gordon - Ross Note: there is a multiple-cycle delay path There is no register to save the results between: IRWr ) Register Fetch: busa <- Reg[rs] ; busb <- Reg[rt] ) R-type Execution: output <- busa op busb ) R-type Completion: Reg[rd] <- output Register here to save outputs of Rfetch? busa Rb Reg File busw busb selb sela Op Register here to save outputs of RExec? A Multiple Cycle Delay Path (Continue) Register is NOT needed to save the outputs of Register Fetch: IRWr = : busa and busb will not change after Register Fetch Register is NOT needed to save the outputs of R-type Execution: busa and busb will not change after Register Fetch signals, SelB, and Op will not change after R-type Execution Consequently output will not change after R-type Execution In theory, you need a register to hold a signal value if: () The signal is computed in one clock cycle and used in another. () AND the inputs to the functional block that computes this signal can change before the signal is written into a state element. You can save a register if Cond is true BUT Cond is false: But in practice, this will introduce a multiple cycle delay path: - A logic delay path that takes multiple cycles to propagate from one storage element to the next storage element 9 EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross

11 Pros and Cons of a Multiple Cycle Delay Path Pros and Cons of a Multiple Cycle Delay Path (Continue) A -cycle path example: IR (storage) -> Reg File Read -> -> Reg File Write (storage) Advantages: Register savings We can share time among cycles: - If takes longer than one cycle, still OK as long as the entire path takes less than cycles to finish Disadvantage: Static timing analyzer, which ONLY looks at delay between two storage elements, will report this as a timing violation You have to ignore the static timing analyzer s warnings busa Rb Reg File busw busb selb busa Rb Reg File busw busb selb EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross Summary logic Disadvantages of the Single Cycle Processor Long cycle time Cycle time is too long for all instructions except the Load Review of Finite State Machine (FSM) control From Finite State Diagrams to Microprogramming Multiple Cycle Processor: Divide the instructions into smaller steps Execute each step (instead of the entire instruction) in one cycle Do NOT confuse Multiple Cycle Processor with multiple cycle delay path Multiple Cycle Processor executes each instruction in multiple clock cycles Multiple Cycle Delay Path: a combinational logic path between two storage elements that takes more than one clock cycle to complete It is possible (desirable) to build a MC Processor without MCDP: Use a register to save a signal s value whenever a signal is generated in one clock cycle and used in another cycle later EEL-7 Ann Gordon - Ross EEL-7 Ann Gordon - Ross

12 Overview may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control Initial Representation: Finite State Diagram 8 : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem 6, : x:,regdst : 7, 9: Jump x: See Fig C.. : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : EEL-7 Ann Gordon - Ross 6 EEL-7 Ann Gordon - Ross Sequencing : Explicit Next State Function Interface in detail Logic and Next State Logic Inputs O u t p u t s Multicycle Datapath Opcode State Reg Next state number is encoded just like datapath controls 7 EEL-7 Ann Gordon - Ross 8 EEL-7 Ann Gordon - Ross

13 Logic Representation: Logic Equations Next state from current state State -> State State -> S, S6, S8, S State -> S, S State -> State State ->State State -> State State 6 -> State 7 State 7 -> State State 8 -> State State 9-> State State -> State State -> State 9 EEL-7 Ann Gordon - Ross Alternatively, prior state & condition S, S, S7, S8, S9, S -> State State -> State State & op = -> State State & op = -> State State -> State State & op = -> State State & op = R-type -> State 6 State 6 -> State 7 State & op = -> State 8 State & op = jmp -> State 9 State & op = ORi -> State State -> State See Fig. C.. Implementation Technique: Programmed Logic Arrays Each output line: the logical OR of logical AND of input lines or their complement; AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op Op Op Op Op Op S S S S = 6 = = 7 = = 8 = = 9 = = = = = EEL-7 Ann Gordon - Ross R = = = = ori = jmp = Op=any S= Next= NS NS NS NS Implementation Technique: Programmed Logic Arrays Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op Op Op Op Op Op S S S S = 6 = = 7 = = 8 = = 9 = = = = = EEL-7 Ann Gordon - Ross = = R = ori = = jmp = NS NS NS NS Multicycle Given numbers assigned to FSM, can in turn determine next state as function of the inputs and current state Can turn these into Boolean equations for each bit of the next state lines Implement easily using PLA (programmable logic array) or ROM storing truth tables See Figs. C..6 and C..8 for tables showing outputs and next state as function of current state and opcode What if many more states, many more conditions? State machine gets too large; very large ROMs/PLAs What if need to add a state? May need to increase address for ROM, number of inputs for PLA gates Or just implement FSM in VHDL EEL-7 Ann Gordon - Ross

14 Next Iteration: Using Sequencer for Next State Sequencer-based control unit Before: Explicit Next State; Next try variation step from right hand side Few sequential states in small FSM: suppose added floating point? Still need to go to non-sequential states: e.g., state =>, 6, 8, Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control EEL-7 Ann Gordon - Ross Logic Outputs Inputs State Reg Adder Address Select Logic Opcode EEL-7 Ann Gordon - Ross Multicycle Datapath A processor on its own Set state to Dispatch (state & ) Incremented state number ( micro ) and micro branches specify whether to increment or select another state based on opcode Sequencer-based control unit Sequencer block diagram Adder Logic Outputs Inputs State Reg Address Select Logic Multicycle Datapath AddrCtrl control for select logic : reset state register (next instruction) : select next using next-state ROM for state : select next using next-state ROM for state : increment state Fig. C.. Before: 6bit opcode + -bit state -> -bit NS Now: -bit state -> -bit AddrCtrl AddrCtrl= (fetch) AddrCtrl= (decode) AddrCtrl= (/) AddrCtrl= () AddrCtrl= () AddrCtrl= () AddrCtrl= (r-type) AddrCtrl= (r-type) AddrCtrl= (branch) AddrCtrl= (ori) AddrCtrl= (ori) Dispatch ROM (Indexed by opcode) -> -> R-type -> ori -> branch -> EEL-7 Ann Gordon - Ross Opcode 6 EEL-7 Ann Gordon - Ross ROM: -> ->

15 Initial Representation: Finite State Diagram 8 : Wr, IRWr x: WrCond RegDst, MemR : Others: s or : LWmem 6, : x:,regdst : 7, 9: Jump x: See Fig C.. : BrWr, SelB= x: RegDst,, Others: s ype RExec : RegDst SelB= Op=ype x:, Op=ype : RegDst, sela SelB= x:, Op=Sub SelB= x:, MemReg RegDst, : WrCond Exec Op=Or :, Finish Op=Or x:, : Next Iteration: Using Microprogram for Representation Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control ROM can be thought of as a sequence of control words word can be thought of as instruction: microinstruction 7 EEL-7 Ann Gordon - Ross 8 EEL-7 Ann Gordon - Ross Microprogramming is the hard part of processor design Datapath is fairly regular and well-organized is highly regular is irregular and global Microprogramming: -- A particular strategy for implementing the control unit of a processor by "programming" at the level of register transfer operations Macroinstruction Interpretation Main execution unit ADD SUB AND... DATA User program plus Data this can change! one of these is mapped into one of these Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer CPU control memory AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Aner(s) 9 EEL-7 Ann Gordon - Ross 6 EEL-7 Ann Gordon - Ross

16 Microprogramming Pros and Cons Summary: Multicycle Ease of design Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets (just more control memory) Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. Compatibility Many organizations, same instruction set Costly to implement Slow Microprogramming and hardwired control have many similarities, perhaps biggest difference is initial representation and ease of change of implementation, with ROM generally being easier than PLA Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control 6 EEL-7 Ann Gordon - Ross 6 EEL-7 Ann Gordon - Ross