UNITS:III. PART A Question

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1 Subject: CPLD & FPGA ARCHITECTURES AND APPLICATIONS 1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer International Edition. UNITS:III 1. a) Given f (T,U,V,W, X,Y ) =VWX +UVWY +TVWY. Show how f can be realized using a single 4000 series, logic cell. b) Explain the implementation of petrinet with an example c) What is metastability? Explain the metastability behavior using a Flip flop with appropriate waveforms. 2. a)explain state machine chart using micro programming linked state machine. b) Explain hot state machine with an example c) Explain how multiplexer based approach is useful for the design of an ALU d) Explain the operation of a small petrinet controller. 3.a) Explain the use of ASMS in one hot design b) Explain about the state machine designs centered around shift registers. c) Explain about the alternative realization for state machine using micro programming. d) Explain about the top-down design approach of state machine with an example. PART B Question 1.a) Explain about one hot state machine with state table and state diagrams. b) Develop one hot state diagram for a sequence checker whose output is 1 whenever the sequence 0101 is detected. Also specify its Transition Table. 2. a) Explain the data path and functional partition of FSM system level design. b) Explain about linked state machine. 3. Write short notes on any TWO a) Speed performance of PLDS. b) Parallel Controller c) Top down design of FSM 4.a) Explain the basic concepts and properties of petrinets for state machine. b) Give the description of a traffic light controller using the petrinet. 5. The SM charts for three linked machines are given below. All state changes occur during the falling edge of a common clock. Complete a timing chart including ST, Wa, A, B, C and D. All state machines start in the state with an asterisic (*) 1

2 6.a) Explain the extended petrinets for parallel controllers b) Explain about linked state machine for a dice game. 7.a) Explain about the datapath and functional partition of FSM system level design b) Design a binary multiplier control using one-hot method.

3 Subject: CPLD & FPGA ARCHITECTURES AND APPLICATIONS 1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer International Edition. UNITS:IV 1. a) Explain the salient features of FPGA Advantage Tool. How many types of design entries are allowed in FPGA advantage? Explain them briefly. b) Draw and explain different design stages involved in the FPGA design flow. c) Explain the implementation of a parallel adder using XILINX s FPGA. d) Explain the implementation of a decade counter using a 3020 FPGA. 2. a)write a brief note on ASIC design flow using EDA tools. b) Explain the front end and dsign tools for FPGA. c) Explain the design flow using FPGA's. d) Write short notes on the following i) Design of parallel adder cell. ii) Sequential circuit. iii) Parallel controllers. PART B Question 1. Explain the complete design flow to implement a 4 bit Ripple-carry adder circuit on to FPGA using an EDA tool. Also explain the timing simulation for the same. 2. Write a brief note on any two: a) Floor plan b) Optimized reconfigurable cell array. c) Speed performance of different CPLDs.

4 Subject: DIGITAL SYSTEM DESIGN UNITS:III 1. a) It is necessary to determine the final state of the machine shown below when the initial state is unknown and only output sequences from the machine are available to the experiments. Derive the procedure to determine the final state of the machine. b) Explain the properties of a successor tree. 2. a)apply COMPACT algorithm to fold the PLA column wise for the given SSR table for columns. Column SSR A 3,6,8 B 1,2,4,5,9,11 C 1,3,6,7,9,10 D 2,5,7,8,12 E 1,3,6,11 F 4,6,7,8,10 G 1,3,5,7,9 H 6,8,12 b) Minimize the following function by II SC algorithm. f = How many cubes have been processed to get the final result? PART B Questions 1. Explain how incompletely specified machines are simplified? 2. a) Show the eight exit paths in ASM block emitting from the decision boxes that check the eight possible binary values for three control variables x, y and z. b) Design ASM chart for a binary multiplier and show the PLA control block diagram. 3. a) Draw & Explain the Basic model of sequential circuit.

5 b) Give a state assignment without critical races to each of the followingasynchronous machine shown in figure Consider the machine whose transition table is given in table shown in Fig Design a checking experiment for this machine Design a Mealy sequential circuit which investigates an input sequence X and will produce an output Z=1 for any input sequence ending in 0010 or 100 X= ; Z=

6 Subject: DIGITAL SYSTEM DESIGN UNITS:IV 1. a) For the circuit shown below generate test pattern for locating a α, an S-a-0 at point P1 using D-algorithm. b) For the circuit shown below generate the test pattern to detect β an S-a-1 fault at P2 using path sensitization. c. Define the terms failure and fault? Discuss the different fault models? 2. a) Explain the Boolean difference method with an example. b) A two level AND-OR circuit has four AND gates feeding one OR gate. The four AND gates realize the product terms x1x3 x4, x2x4, x1 x3 x4 and x1x2x3 respectively. Derive the a and b - tests for detecting multiple stuck at faults. c) Explain PODEM with an example. d) Explain transition count testing with an example

7 PART B Questions 1. Using the path-sensitization method and Boolean difference method find the test vectors for SA0 fault on input line 1 and SA1 fault on the internal line 2 of the circuit shown in figure 2. a) Explain about the fault model of PLA, with an example and derive the test vector set for the example. b) Explain the EPC theorem that is used in IISC algorithm to minimize the function to be implemented on PLA. 3. a) In the gate network shown, only wires m, n, p and q may become either SA0 or SA1. Construct a fault table and find a minimal cover of the table and use it to determine a minimal fault detection experiment. b) 4. What are the different faults present in PLA and how to test these faults? 5.a) What is PODEM? Explain how PODEM algorithm is used to test faults. b) How a transition count is used to test faults? 6.a) What are the different types of faults and give some examples for each type? b) Find the faults at e and h of the following circuit shown in figure using Boolean difference method.

8 7. a) Find all the tests to detect h SA0 and k SA1 faults by applying path sensitization technique to the given circuit below. b) Apply D-algorithm to detect SA0 fault at point h in the given circuit shown in figure 2 and derive the test vectors. c) Apply signature analysis to the above circuit and generate the signatures using 4-bit LFSR with a feed back from 3 rd flip flop. 7.a) Explain the different types of fault models and fault types in a PLA. b) Plot the following PLA on the map. Identify the undetectable faults. Determine a minimal test set for detectable faults. x x x x Z1Z a) Draw the portion of an ASM chart that specify a conditional operation to increment register (r) during state t1 and transfer to state t2 if control inputs z and y are equal to 1 and 0 respectively. b) Design an ASM chart for a serial adder with accumulator and show the control block diagram.

9 Subject: DIGITAL SYSTEM DESIGN UNITS:V 1. a) Discuss about any one method of fault diagnosis in sequential circuits using an example? b) Define a diagnosable sequential machine and how it can be constructed. 2. a)explain how to test a PLA circuits? b) Apply PLA maximization procedure and obtain the minimized expression to be implemented on PLA. F = c) Obtain the minimum test vector set for the above function F in question 6 (a). PART B Question 1. a) Design a flow table for a fundamental mode sequential circuit with two inputs, x1 and x2 and one output z. z=1 if both equal to 0, but only if x1 becomes 0 before x2. b) For the given reduced flow table, find an assignment which contains no critical races and requires a minimum of secondary variables. 2. Explain the procedure of designing a fault detection experiment for a sequential circuit with the help of an example. 3. Explain the procedure of designing a fault detection experiment with the help of an example. 4. Construct a fault-detection experiment for the machine of the following table. That is entirely preset, that is with no initial adaptation part.

10 5. Write short notes on the following. a) Capabilities and limitations of FSM b) Transition check approach in sequential circuits. c) Bridging fault model. 6. Each of the following specification, describe a fundamental mode sequential circuit with two inputs x 1 and x 2 and one output z. Show a primitive and reduced flow table for circuit if z = 1 if both x 1 and x 2 are equal to 1 but only if x 1 becomes before x 2.

11 Subject:VLSI TECHNOLOGY & DESIGN 1. Essentials of VLSI Circuits and Systems, K. Eshraghian Eshraghian. D, A. Pucknell, 2005, PHI. 2. Modern VLSI Design Wayne Wolf, 3rd Ed., 1997, Pearson Education. UNITS:III 1.a) What is barrel shifter? How to use it in VLSI design? b) How to list a combinational logic networks? Give some simulation tools. c) Design a 4x4 bit Carry-Save Multiplier. 2. a) Give routing techniques to equalize channel utilization. b) Distinguish between clock skew and signal skew with an example. c) Explain the different types of simulation of combinational logic networks with suitable examples in detail. PART B Questions 1.a) Explain how to optimize the power in combinational logic networks. b) What is clock skew? How to calculate in logic circuit? 2. Design a parity generator and explain the functioning of it with a transistor schematic and layout. 3. Explain how two-phase clock system is designed for sequential circuits and compare it with single-phase clock system. 4. Consider the circuit shown in figure. i) Determine the logic function F. ii) Design a circuit to implement the same logic function using NOR gates. iii) Draw a transistor level schematic and use CMOS technology.

12 Subject:VLSI TECHNOLOGY & DESIGN 1. Essentials of VLSI Circuits and Systems, K. Eshraghian Eshraghian. D, A. Pucknell, 2005, PHI. 2. Modern VLSI Design Wayne Wolf, 3rd Ed., 1997, Pearson Education. UNITS:IV 1.a) Draw a circuit diagram for 4 transistor SRAM cell and explain how it stores data? b) Write short notes on the clocking discipline for sequential systems. 2. a) What is clock skew? How it is calculated? b) Explain how to optimize power for sequential circuits? PART B Questions 1.a) What is one-phase and two-phase clocking systems? Compare them. b) How to validate the design of sequential circuits? 2.a) Explain how capacitive coupling lead to crosstalk. b) Discuss graph model for path delay through combinational logic in the combinational network delay.

13 Subject:VLSI TECHNOLOGY & DESIGN 1. Essentials of VLSI Circuits and Systems, K. Eshraghian Eshraghian. D, A. Pucknell, 2005, PHI. 2. Modern VLSI Design Wayne Wolf, 3rd Ed., 1997, Pearson Education. UNITS:V 1.a) What is mean by floor planning? Explain the different methods of floor planning. b) Design a circuit for input pad connectivity and explain its necessity in chip design c) Explain the various Architectures to reduce the power. d) Explain how scheduling determines time cost. 2. a)explain Floor-Planning methods for a chip in detail. b) Write short notes on i) Resistive and inductive interconnect delay. ii) High level Synthesis. PART B Questions 6.a) Explain the Global and detail routing in floor planning. b) What are the different tools available for layout synthesis? c) What is SOCs? Give some examples of it? 7. Write short notes on: a) Off-chip connections b) Chip design methodologies. 8.a) Explain the process steps in floor planning. b) How Architecture of chip can be tested? Give some example. 9. Write short notes on: a) Scheduling and printing b) Hardware/Software Co-design. 10. a) Explain briefly how the hardware/software co-simulation and co- synthesis issues are addressed. b) Write notes on Architecture Testing related to VLSI Design? 11. Write notes on any two of the following: a) Testing of sequential circuits b) Floor planning methods c) Wires and Vias 12. What is routing? Explain with some suitable example. How it is optimized? 13. Write short notes on: a) Power optimization for combinational circuits. b) Static complementary gates.

14 Subject: CMOS ANALOG INTEGRATED CIRCUIT DESIGN UNITS:III 1. what is frequency response of a circuit. With necessary equations explain the concept of active load inverter and explain small signal model. 2. Explain current source inverter with suitable diagram. Derive equations for Vout, small signal voltage gain, Rout and Cout and small signal analysis. 3. Find the performace of a current sink inverter shown below. The current sink inverter is shown, assume W1=2µm, L1=1 µm, W2=1 µm, L2=1 µm, VDD=5V, VGG1=3 V, and consider the parameters for M1 and M2 also capacitor values (Cgd1=Cgd2). Calculate the output swing limit s and the small signal performance. 4. Expalin the concept of push-pull inverter with neat diagram, derive the small signal voltage gain and find the zero in plane. 5. How can we analyse the noise analysis of a inverter. Derive the equation for equivalent input volage-noise spectral density of the push-pull inverter. 6. Briefly explain the differential amplifiers. With necessary equation give the large signal analysis of CMOS differential amplifies. 7. With neat sketch explain the concept of differential amplifier with current mirror load 8. Explain CMOS differential amplifier using p-channel input MOSFETs with necessary equations(small signal analysis). 9. Assume that Vdd varies from 4 to 6 V and that Vss=0 and use standard values under worst case condition to calculate the input common mode range for figure shown below. Assume that ISS 100µA, W1/L1=W2/L2=5,

15 W3/L3=W4/L4=1 and VDss(sat)=0.2 V. Include worst-case variation in K. 10. With necessary equations and diagrams explain the small signal analysis of differential amplifiers. PART B Question 1. Explain the concept of intuitive analysis of CMOS differential amplifier with necessary equations and diagram. 2. Explain the slew rate and noise for p-channel differential amplifier with necessary equations. 3. With neat sketch explain the concept of current source load differential amplifier. 4. Explain the design aspects of current mirror load differential amplifier. 5. Design a CMOS current mirror load differential amplifier. 6. With neat sketch explain the simple cascode amplifier. And derive the output voltage for simple cascode amplifier. 7. With necessary equations explain small signal characteristics of cascode amplifier 8. With necessary equations explain frequency response of a cascode amplifier 9. Explain the concept of Miller effect. 10. Explain the design aspects of cascode amplifier and design a simple cascode amplifier 11. What is a current amplifier? Explain single ended input current amplifier and differential input current amplifier with necessary equations and diagrams. 12. With neat sketch explain how can we use simple current mirror as current amplifier. 13. Implement a current amplifier using self-biased cascode current mirror. 14. With neat sketch explain differential input current amplifiers. 15. Briefly explain the concept of output amplifiers. Explain load line analysis of class A amplifier. 16. Design a simple class-a output stage amplifier. 17. Briefly explain the concept of following : a) source followers b) Push-pull common source amplifiers.

16 Subject: CMOS ANALOG INTEGRATED CIRCUIT DESIGN UNITS:IV 1. Explain with neat sketch of the ideal characteristics of basic two stage Op-Amp. 2. With neat sketch explain the following a) characterization of Op-Amp. B) classification of Op-Amp. 3. Explain in-detail design aspects of OP-amp. 4. Explain the following with respect to compensation of Op-Amps: a) small signal dynamics of two stage opamps b) Miller compensation of two stage Op-Amp. c) Feed forward compensation. 5. Explain the design procedure for two stage CMOS Op-Amp with an n-channel input pair. 6. Explain the design procedure for un buffered CMOS Op-Amp with an n-channel input pair. 7. Design an amplifier shown below, the meets the following specifications with a phase margin of assume the channel length is to be 1µm. 8. With neat sketch and necessary equation explain the concept of nulling resistor compensation of two stage CMOS Op-Amp. PART B Question 1. Explain the following for 2-stage CMOS Op-Amp with necessary equations and diagrams: a) Positive PSSR b) Negative PSSR. 2. A)What are the advantages by using cascoding of first stage for 2-stage CMOS Op-Amp. b)what are the advantages by using cascoding of first stage for 2-stage CMOS Op-Amp.

17 3. With neat sketch and necessary equations explain the concept of folded cascode Op-Amp. Give the small signal analysis. 4. Design a folded cascade op-amp: see Text book -1, page 307.

18 Subject: CMOS ANALOG INTEGRATED CIRCUIT DESIGN UNITS:V 1. Explain in detail the characteristics of comparators with necessary equations and diagrams. 2. Find the propagation delay time of an open-loop comparator that has a dominant pole at 10 3 rad/s a dc gain of 10 4, slew rate of 1 V/µS, an binary output voltage swing of 1 V. Assume the applied input voltage is 10mV. 3. With neat sketch and necessary equations explain the concept of two stage comparator. 4. Evaluate V OH, V OL, A V (0), V in (min), p1 and p2 for the two stage comparaor shown below. Assume that this comparator is the circuit with o compensation capacitor, C0 and minimum value of V gs -0v. Also, assume that C1=0.2pF and Cu=5pF. 5. With neat sketch and necessary equations explain the Design aspect of a two stage open loop comparator for linear response. 6. With neat sketch and necessary equations explain the Design aspect of a two stage open loop comparator for slewing response. PART B Question 1. Explain the following with neat sketch: a) Push-Pull output comparators b) comparators that can drive large capacitive loads. 2. Explain the following terms with neat sketch: a) Auto zeroing technique b) comparator using hysteresis. 3. Explain the following terms with neat sketch: a) Switched capacitor comparators b) Regenerative comparators 4. See all the example problems in this unit, they will be asked in the exam.

19 Subject: CMOS DIGITAL INTEGRATED CIRCUIT DESIGN UNITS:III 1. A) Briefly discuss about sequential logic with neat sketch. b)classify the logic circuits based on their temporal behavior. 2. Briefly discuss the behavior of the bistable elements. Derive the expression for the time domain behavior of the diverging process until reaches stable points. 3. With neat sketch explain the following operation modes: a) CMOS SR latch circuit based on NOR2 gates b) CMOS SR latch with lumped load capacitances at output nodes. 4. With neat sketch explain the following operation modes: a) CMOS SR latch circuit based on NAND2 gates b) Depletion-load nmos NAND-bassed SR latch circuit. 5. Briefly discuss the following: a) Gate level clocked NOR based SR Latch with input and output waveforms. B)CMOS AOI based implementation of the clocked NOR-based SR latch circuit. C) Gate level clocked NAND based SR Latch with active high inputs. 6. Briefly discuss the following: a) Gate level clocked NAND based JK Latch. B)CMOS AOI based implementation of the clocked JK latch circuit. C) Gate level clocked NOR-basedJK Latch. PART B Question 1. With neat sketch explain the concept of master slave flip-flop consisting of NAND based JK latch with input and output waveforms. 2. With neat sketch explain the concept of master slave flip-flop consisting of NOR based JK latch 3. Briefly explain the concept of the following with neat sketch: a) gate level schematic of D-Latch b) CMOS implementation of the D-latch. C) simplified schematic view of CMOs D-Latch with setup time and hold time. 4. With neat sketch explain the following CMOS negative edge-triggered master-slave D flip-flop. Explain NAND3 based positive edge triggered D flip-flop

20 Subject: CMOS DIGITAL INTEGRATED CIRCUIT DESIGN UNITS:IV 1. A)What is dynamic logic and explain the advantages. b) Basic principles of Pass Transistor Circuits. 2. With necessary equations explain the following: a) Logic 1 transfer b) Logic 0 transfer c) charge storage and Charge leakage. 3. Explain the concept of voltage bootstrapping with necessary equations and circuit diagrams. 4. Explain Synchronous Dynamic circuit techniques (or) 4. Explain the following with neat sketches: a)multi-stage pas transistor logic driven by two non overlapping clocks b) 3 stage depletion load nmos dynamic shift register driven with 2-phase clocking c) enhancement load dynamic shift register (ratioed logic). 5. Explain the general circuit structure of ratioed synchronous dynamic logic and ratioless synchronous dynamic logic. With neat sketch explain enhancement-load dynamic shift register(ratioless logic). PART B Question 1. With an example explain CMOS transmission gate logic. 2. With neat sketch explain the concept of dynamic CMOS Precharge-Evaluatelogic. 3. Explain the concept of Domino CMOS logic and cascaded domino CMOS logic with an example. 4. Explain the concept of cascaded domino CMOS logic with static CMOS logic gates with an example. 5. With neat sketch explain the concept of NORA CMOS logic (NP-Domino Logic) with an example. 6. Explain the following with neat sketch: a) Zipper CMOS circuits b) true single Phase Clock (TSPC) Dynamic CMOS

21 Subject: CMOS DIGITAL INTEGRATED CIRCUIT DESIGN UNITS:V 1. Explain various classification of semiconductor memories. 2. With neat sketches explain the equivalent circuits of memory cells and RAM array organization. 3. Explain dynamic RAM configuration and DRAM cell types. Explain the operation of 3-transistor DRAM cell. 4. With timing diagram explain the DRAM operation Modes. 5. With neat sketch explain the following: a) Leakage currents in DRAM cell and Refresh Operation b) DRAM input and output circuits. PART B Question 1. Explain the concept of static RAM. With neat sketches explain various configurations of static RAM cell. 2. Briefly explain the operation of SRAM memory structure with read and write circuitry. Explain timing diagrams. 3. What is Non volatile Memory. How can we design row and column decoders for ROM. 4. What is flash memory, explain various configurations and implementation of flash memory.

22 Subject: MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN UNITS:III 1. Explain the terms Thumb and thumb instruction decoding. 2. How can we use Thumb register? Explain ARM-Thumb Internetworking. 3. Explain the branch instruction in ARM Version. PART B Question 1. With examples explain the ARM Data Processing Instructions. 2. Explain the following with examples: a) Single-Register Load-Store Instructions b) Multiple-Register Load- Store Instructions. 3. Explain the following with examples: a)stack Instructions b) Software Interrupt Instructions.

23 Subject: MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN UNITS:IV 1. Explain the overview of C compilers and Optimization. 2. A) Explain ARM Basic C data types b)local Variable Types with examples c) function argument types d) Signed vs Unsigned types with examples. 3. Explain the following with examples: a) Loops with a fixed number of Iterations b) Loops using a Variable number of iterations c) Loop Unrolling. 4. Explain the following for ARM with examples: a) Register allocation b) Function calls 5. Explain the following for ARM with examples: a) Pointer aliasing b)structure arrangement. 6. Explain the following for ARM with examples: a) Bit Fields b) Unaligned Data and Endianness. 7. Explain the Division instruction representation in ARM : a)repeated unsigned division with remainder b) Convert in divides into multiples c) unsigned division by constant d) Signed division by a constant. 8. Explain the following for ARM with examples: a) floating point b) Inline Functioons and Inline assembly. C) Portability issues. PART B Question 1. Write any 3 example programs in basic ARM assembly language code. 2. Explain the following for ARM with examples: a) Register allocation b) Allocation variable to register numbers c) Using more than 14 Local variables d) Making the most of available registers. 3. Explain the conditional execution in ARM. 4. Explain indetail looping constructs in ARM 5. With examples explain the following : a) Profiling and cycle counting b) Instruction scheduling c) Scheduling of load instructions d) load scheduling by preloading e) Load scheduling by unrolling.

24 Subject: MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN UNITS:V 1. With neat sketch explain ARM s memory hierarchy. 2. With neat sketch explain Cache Architecture. 3. Explain the following with necessary diagrams and example: a) Set Associativity b) Write buffers c) measuring cache efficiency 4. Explain in detail concepts involved in Cache policy 5. A) How can we flush ARM cached cores. Explain with an example. b) How can we clean he D-cache. Explain with an example. 6. Explain the following with an example: a) cleaning the D-cache using way and set index addressing. B)Cleaning he D-cache using the Test clean command. C) Cleaning the D-cache in Intel Xscale SA-110 and Inter strong ARM cores. PART B Question 1. Explain how virtual memory works. 2. Explain the following for ARM with examples: a)defining regins using pages b) multitasking and MMU. c ) memory organization in the virtual memory system. 3. A) Explain the concept of page tables. B) level-1 page table entries c) L1 translation table base address. D) Level 2 page table entries e) selecting a page size for you embedded system. 4. A) Explain translation lookaside buffer. B) single-step page table walk c) two step page table walk.. d) TLB operations. 5. Explain briefly the domains and memory access permissions. 6. Explain in-detail the fast context switch extension.