ASSERTION SUPPORT IN HIGH-LEVEL SYNTHESIS DESIGN FLOW. 351 crs de la Libération, Talence, France

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1 SSERTION SUPPORT IN HIGH-LEVEL SYNTHESIS DESIGN FLOW urélen Rbon, Bertrand Le Gal, Chrstophe Jégo and Domnque Dallet Unversté de Bordeaux, Laboratore IMS, CNRS UMR 528, IPB, 35 crs de la Lbératon, Talence, France BSTRCT The ncreasng complexty of System-On-Chp applcatons ncreases the challenge of the desgn task, and specfcally the verfcaton process. sserton-based Verfcaton s one of the key nnovatons to smplfy RTL verfcaton and facltate desgn reuse. However, current desgn automaton tools do not take nto account assertons found n behavoral source codes durng the Hgh-Level Synthess (HLS) process. Ths work focuses on a methodology for automatc detecton and transformaton of behavoral untmed assertons from a transacton-level descrpton nto temporal RTL assertons. Ths process s ntroduced as a partcular task of a HLS desgn flow. RTL montors are generated ether n PSL or VHDL language, for smulaton purpose. Therefore, ths approach contrbutes to IP-reuse methodologes as nput transacton assertons (checkng the correctness of data provded by the system) can be exploted n automatcally generated IPs. Index Terms BV, archtecture, asserton, desgn, HLS, IP, montor. INTRODUCTION The recent fast Integrated Crcut (IC) capacty growth affects not only the scale of current desgns, but also ther complexty. Whle t enables effcent archtectures to solve today s computaton and communcaton problems, the cost of relablty has never been so hgh. Latest studes evaluate that up to 70% of desgn tme s spent n testng and debuggng processes []. Therefore, a number of verfcaton methodologes have been developed and adopted at the Regster Transfer Level (RTL) durng the last decades [2]. One of these technques s called sserton-based Verfcaton (BV) [3]. ssertons are the formal translaton of desgn specfcatons. BV conssts n desgnng archtectures by embeddng asserton statements nto the RTL source code. s a consequence, they ncrease the productvty of system debug and the effcency of desgns. Ths approach speeds up the debug process by allowng smulators and formal verfcaton tools to dentfy errors at ther source, or close to ther source. Ths greatly reduces the tedous task of back tracng errors to ther root cause. Thus, bugs that could have gone undetected can be exposed. Moreover, embeddng assertons wthn the RTL code facltates the reuse of soft Intellectual Property (IP) blocks by ensurng ther proper use n the archtecture durng smulatons. The debug of the ntegraton task s made easer thanks to the dentfcaton of errors close to ther source. However, to our knowledge, current Electronc Desgn utomaton (ED [4,5,6]) tools that automatcally generate RTL archtectures from behavoral descrpton do not support assertons durng ther synthess process. s a consequence, there s no propagaton of behavoral assertons to the generated RTL descrptons. Ths dsables any possblty of later asserton-based verfcaton. In ths paper, we explan why we consder that the propagaton of Boolean assertons from untmed behavoral descrptons to RTL temporal assertons s of utmost mportance. We also propose a methodology that takes nto account assertons durng the HLS synthess process. It ams at generatng RTL montors, for smulaton purpose only, from two knds of assertons:. The Boolean assertons found n the behavoral untmed descrpton, 2. The temporal assertons mpled by some synthess constrants gven by the desgner. Generated montors are descrbed ether as Property Specfcaton Language (PSL, a dedcated RTL verfcaton language) statements or as ndependent non-syntheszable VHDL processes that act as wrappers around VHDL asserton statements. Ths way, there s no penalty on the crcut behavor and ts performances. Generated montors are used to enable easer desgn reuse through the valdaton of transactons. Ths methodology s bult around the Synthess-for-Verfcaton [7] paradgm Ths paper s organzed as follows: secton 2 explans the motvaton of ths work. Secton 3 detals the dfferent types of assertons supported by ths work. The proposed methodology s descrbed n secton 4 and theoretcally developed n secton 5. Fnally, expermental results are related n secton 6. Last secton draws a concluson and provdes some perspectves.

2 2. MOTIVTION OF THIS WORK 2.. ssertons and desgn reuse ssertons-based verfcaton s an effcent technque when t comes to check component transacton durng smulatons. Indeed, assertons can be used as formal contracts to ensure that the data sent to or receved by a component follow the specfcatons. Ths programmng pattern s referred as Desgn-By-Contract (DbC) [8]. Whle t has been n use for many years now wth success n the software development world, ts consderaton for hardware desgn s just emergng. Desgn-By-Contract approach defnes three man asserton constructons, as llustrated n Fgure : Precondtons, whch check data sent to the component, Postcondtons, whch valdate output data, Invarants, whch have to be verfed at any tme. By followng the Desgn-By-Contract paradgm, a desgner can facltate easly mplement ts IP nto a foregn system. Frstly, precondtons make sure that the foregn system follows the nput specfcatons of the IP. Secondly, the ntegrator can rely on the postcondtons to valdate the behavor of the IP. ll ncorrect data sent to or receved by the component s caught by the smulator thanks to asserton ponts. Ths behavor heavly facltates the reuse of IPs n complex systems, by means of more effcent debug task. Snce ntegrators have to make sure that every ntegrated IPs are correctly used by the system, well placed assertons defned n the IPs mmedately report any bad transacton data durng functonal smulaton. It s smlar to software development: functon calls can check ther passed parameters through assertons, and drectly stop the applcaton executon f somethng wrong s detected Hgh-Level Synthess and asserton transformaton Hgh-Level Synthess (HLS) tools provde a hgher level of nt lnearze(nt x) { } // nvarant () assert ( current_mode == LINER ); // precondton assert ( X_MIN <= x && x <= X_MX ); nt k = x * CONST_ + CONST_B; // nternal asserton assert ( k > 0 ); nt y = k >> ; // postcondton assert ( y > 0 ); // nvarant (2) assert ( current_mode == LINER ); return y; Fg.. Desgn-By-Contract constructons desgn abstracton [6,7]. Thus, a desgner can adapt ts desgn to a wde range of targeted devces and applcaton contexts. Indeed, through the defnton of hardware-related constrants such as targeted platform, clock frequency or avalable hardware resources, a same behavoral descrpton can be used to synthesze dfferent dedcated RTL archtectures. Such desgn flow s llustrated n Fgure 2. We thnk that sserton-based Verfcaton can greatly help HLS processes to generate more robust archtectures. It can also facltate archtecture ntegraton nto dfferent system hosts. ctually, ths methodology s a handshake between a system ntegrator and a desgner: Precondtons let the desgner be sure that the syntheszed archtecture s correctly used by the system, Fg. 2. Hgh-Level Synthess desgn flow

3 Postcondtons and nvarants would assure the ntegrator that the archtecture behavor, and ndrectly the algorthm specfcaton, s correct and does not suffer any cornercase msconcepton. In a theoretcal pont of vew, an asserton defned n the behavoral model could be manually hand-coded nto the HLS-generated RTL archtecture. But n practce, t s far from beng so straght-forward. Indeed, HLS tools usually apply many optmzaton technques such hardware resource sharng mergng regsters and operators to be as much as possble resource-effcent. ctually, f a behavoral asserton has to be manually transformed nto ts RTL counterpart, resource-constraned nformaton s necessary. Such nformaton would nclude regsters where varables are stored, fnte-state-machne states when asserted operatons are executed and the executon cycle when the asserton statement must be trggered. Fgure 3 llustrates the transformaton of an asserton from a behavoral descrpton to ts RTL counter-part. More nformaton has to be added durng the synthess process, such as regster names and tmng data. Ths nformaton can only be found by reverseengneerng the (few hundreds of thousands) lnes of code of the generated archtecture or thanks to the HLS tool. For all these reasons, t s necessary that HLS tools handle the assertons present n the nput behavoral models, and automatcally transform them n temporal assertons at the RTL level to enable asserton-based verfcaton Related works To our knowledge, only a few recent works dealng wth asserton preservaton across multple abstracton layers have been publshed. Guarehbagh et al. [9] propose a system-level asserton language and a methodology to automatcally convert them nto software or hardware montors durng the synthess of pplcaton Specfc Instructon-set Processors (SIP). Currer et al. [0] transform behavoral assertons nto syntheszable montors through a translaton from a behavoral assert statement nto an f-then block understandable by the Impulse-C HLS compler. Therefore, ths work dffers from exstng ones because t s applcable to vrtually every HLS tool and behavoral applcaton, and allows a complete control over the asserton treatments before RTL generaton. C++ PSL t[34] = sqrt(2 * x b); assert (t[34] < a); assert always (state = s85) -> prev(reg36, 63) < prev(nput, 85) Fg. 3. Untmed C++ asserton and ts temporal PSL transformaton 3. SUPPORTED SSERTION TYPES The presented methodology supports two types of assertons: those stated n behavoral descrptons and HLS mplct assertons. Indeed, assertons stated n behavoral descrptons are not suffcent to montor the correct behavor of the archtecture. In a HLS process, a desgner has to make some choces durng the defnton of the constrant set. Some of them may lead to ssues n the behavor of the generated archtecture, especally n the case of desgn-reuse. For nstance, archtectures processng 8 bt data may have to be connected to a 32 bt system bus. In ths case, the consequences of such decsons have to be verfed. nother example would be the montorng of system hangs or throughput breaks. Ths verfcaton can be done through the automatc generaton of specfc assertons n the RTL archtecture descrpton. We refer to these assertons as mplct assertons. Therefore, ths work also targets the automatc analyss and generaton of some useful mplct assertons. 3.. Behavoral assertons No preprocess task s necessary n ths case. However, the only requrement s that the HLS compler let them be part of ts nternal abstract representaton of the behavoral descrpton Implct checkng of nput ranges Some archtecture nput ports may be lmted to specfc data value ranges that do not drectly map on the port bt-wdths. These ranges are typcally used to reduce the resource szes n the datapath []. Therefore, t s mpled that nput ports never receve data that overflow these ranges. To ensure ths constrant, nput ranges are retreved from suppled constrants. Then, an asserton s bult for each operaton assgned on the constraned nput port. These assertons ensure the port magntude lmtaton Implct montorng of unsafe operators When constranng any applcaton resource consumpton, two cases can be dstngushed for nternal resource btwdth selecton: Worst case scenaro: regster bt-wdths grow wth the requred computatons, doublng for each multplcaton operaton. Truncated bt-wdths scenaro: ntermedate results are truncated accordng to ther range estmates. They may also take nto account probablty densty functons for computatons that are not relablty crtcal []. Sometmes, they are just set to a same pre-defned arbtrary bt-wdth.

4 In a desgn and reuse context, constrant hypotheses are not always acheved. s a result, truncatng ntermedate results bt-wdths may lead to some unwanted behavor appearng wth overflowng operators. Thus, for each operator that may overflow (accordng to the computed nput data ranges), an asserton s generated. Ths asserton performs the computaton mpled by the montored operator and checks f the result s bound to the specfed range Implct constrant of archtecture throughput The throughput of the generated archtecture s often constraned by the desgner. Ths constrant s used durng allocaton and schedulng steps. However, even f the syntheszed archtecture meets the requred throughput, some nterfaced components may ntroduce unexpected latences. For nstance, f the archtecture nput part contans references to FIFOs, then channel behavors can be unpredctable. s a result, a specfc pre-processng s necessary f a throughput s specfed. It conssts of two dfferent approaches: If the generated archtecture does not embed nterface channels (.e. FIFOs nstantatons are not part of the archtecture), an asserton s generated to count clock cycles between frst and last states of the state machne. If FIFOs are drectly part of the archtecture, one asserton per FIFO s generated. These assertons check that the s_empty flag of each FIFO component s not rased more than a specfc number of tmes durng runtme. 4. PROPOSED METHODOLOGY FOR SSERTION SUPPORT The methodology descrbed n ths secton ams at handlng the assertons specfed n the prevous secton. Note that the desgner can choose to nsert all the mplct assertons, part, or none of them. Ths methodology s composed of heght tasks; each one can be seen as an extenson of the conventonal HLS tool that modfes the nternal abstract representaton. Most Hgh-Level Synthess tools part ther synthess process nto many actvtes, at least ncludng: Complaton: a lexcal analyss of the behavoral descrpton. n abstract representaton, usually an bstract Syntax Tree (ST) [2], s generated from the orgnal specfcaton. Varous transformatons can be appled on t. From ths representaton, a Control-Data- Flow Graph (CDFG) [3] s bult. Ths graph represents the model data propagaton and the operatons that have to be performed. Resource selecton and allocaton: resources for the RTL mplementaton are chosen from avalable hardware lbrares. Moreover, the number of regsters and operators are computed wthout takng nto account hardware reusng. Schedulng and bndng: operatons and data are scheduled accordng to the allocated resources and tme constrants (latency and throughput). Then, CDFG elements are lnked to hardware resources. However, to authors knowledge, asserton support s not part of academc and ndustral tools. For ths reason, asserton support s undefned and they are ether skpped, or are treated as common functons and mplemented usng hardware resources n an unpredctable way. The proposed methodology s a way to get around ths lmtaton. It ams at removng all the asserton branches from the HLS tool nternal model but also at mplementng them as temporal RTL montors dedcated to smulaton or formal verfcaton. If assertons were not removed from the nternal graph, they would be mplemented usng hardware resources, and would degrade crcut performances. The steps nvolved, shown n Fgure 4, are as follows:. Pre-processng: system mplct assertons are dentfed accordng to the supported types descrbed n secton 5.. Correspondng asserton branches for nput range checkng, operator overflow montorng and throughput valdaton are added to the CDFG representaton. 2. sserton branch dscovery: the CDFG s analyzed and asserton branches are dentfed. 3. sserton branch adaptaton: overlappng asserton branches are separated to buld a set of ndependent branches. 4. sserton branch removal: asserton branches are removed from the graph, and then the HLS process syntheszes the RTL archtecture over an asserton-free graph. 5. Bndng: hardware nformaton comng from the HLS process after the schedule-and-bnd task s used to bnd asserton branches to hardware resources. 6. sserton sortng: asserton executon dates are computed n order to follow the behavoral model defned sequences. 7. Montor generaton: montors at the RTL level are fnally generated from the asserton branches. The montor descrpton can be ether n PSL or VHDL (asserton statements are wrapped nto ndependent VHDL processes). 8. RTL embeddng: generated montors are embedded nto the RTL descrpton of the syntheszed archtecture. 5. THEORETICL DEVELOPMENT s prevously explaned, most HLS tools manpulate abstract representatons of applcaton source codes as a drected acyclc graph (DG). Frstly, a graph s a par G = (V, ) where V s a set of vertces (also called nodes) and

5 P C n: n V : n, n n: n V : n, n 2 2 (2) Fnally, we defne a set comprsng the applcaton prmary outputs, referred as V out. The followng sectons detal some of the proposed methodology steps. 5.. sserton branch dscovery The set of nodes that are part of at least one asserton branch s defned as V, wth V V. Ths set s llustrated n Fgure 5. Smlarly, V pure, descrbed n eq. 3, refers to the set of nodes that are only part of asserton branches, wth V pure V V. V pure : n V : C n V (3) Fg. 4. Proposed methodology n a HLS flow s a set of ordered pars of vertces, called arcs or drected edges. n arc a = (x, y) s composed of a head x and a tal y. Secondly, as the graph s acyclc, we can defne a set of entry nodes E and a set of snk nodes S (see eq. ). E : S : n V : n V, n n V : n V, n n, n, n, n n, n Thrdly, for every node n V, we defne P(n) as the set of every parent of n and C(n) the set of every chld of n. These defntons are formally descrbed n eq. 2. () Furthermore, as the Boolean result of every asserton statements s an output, we defne a subset of S that contans the nodes correspondng to asserton snks. Ths set s referred as S. The dentfcaton of an asserton branch starts from an asserton output node n 0 S. The branch dentfcaton algorthm s repeated for every asserton output. Ths algorthm scans the graph by gong from a node to ts parents recursvely. It adds the encountered nodes to the current asserton branch untl a border node s found. Those border nodes, defned n eq. 4, consst of nputs (Border ), nternals (Border 2 ) and outputs (Border 3 ). Border : V out n n, Border : n V : P Border : n V : c C 2 3 Border c V E (4) Example algorthm assert(a!= 0); assert(a - b > 2); y = (a + b) >> ; Fg. 5. Illustraton of the V and V pure sets from an example algorthm.

6 Border 2 values depend on the set V, but V also depends on Border 2. Ths leads to a dead-end. workaround for testng f a node n s n Border 2 reles n retrevng a set of nodes S(n) S, as defned n eq. 5 (Paths(n, n j ) s the set of all paths from n to n j ). Nodes from S(n) are graph outputs that are reachable from n. For each n V, S(n) snce G s a drected acyclc graph. n: n S : Paths n n S (5), Therefore, Border 2 can be obtaned thanks to the followng expresson: Border n nv n S n : (6) 2, s a consequence, for each checked node n, the algorthm retreves the set S(n) and verfes that n s part of Border 2 wth the equalty stated n eq. 6. The recursve algorthm s gven n Fgure 6. ddtonally, B s defned as the set of all nodes that are part of the asserton wth d. n asserton d s a number assgned to an asserton branch from the poston of the asserton statement n the behavoral descrpton. Once an asserton branch (wth d ) s found, the sets B, V and V pure s totally or partally populated by the nodes of ths branch. Ths populaton pattern s expressed as follows: ll nodes from the branch are added to B and V, Nodes verfyng eq. 7b are added to V pure. In ths getssertonbranch(node n) () (2) (3) (4) (5) (6) (7) (8) (9) (0) () (2) (3) (4) (5) (6) (7) branch = new lst of nodes add n to branch f P(n) = or n Vout then return branch end f S compute S(n) := {n S : Paths(n, n) } for n S(n) do f n S then return branch end f end for for p P(n) do f p branch then branch = branch getssertonbranch(p) end f end for return branch Fg. 6. lgorthm of the research of asserton branches equaton, Csts refers to all nodes that represent a constant. more formal defnton of ths set s gven n eq. 7a. n B, Csts : E (7a) V n Pn B n Csts n Vpure 5.2. sserton branch adaptaton (7b) sserton branches can overlap wth each other. Ths behavor comes from the codng style of the applcaton behavoral model. For nstance, some asserton statements may share a varable that s created explctly for these statements. Therefore, the lfetme of ths varable does not exceed the asserton computatons. For ths reason, t s canddate for beng part of V pure. If ths overlap greatly reduces the number of nodes n the whole graph, n counterpart t makes further perasserton optmzatons much harder to perform. It also reduces the flexblty of a potental selecton of mportant assertons to be kept whle others are dscarded for the archtecture generaton. s a consequence, ths step s meant to suppress any asserton overlap. node verfyng eq. 8 s part of multple asserton branches, and has to be duplcated. pure N n V n B (8) Two asserton branches B and B j overlap f and only f they verfy eq. 9. B B V (9) 5.3. sserton branch removal j pure Once branches have been solated, they can be safely broken up from the rest of the man graph. For each asserton branch B, a new graph G = (V, ) s defned. Nodes from B V pure are drectly removed from V and put nto V whle nodes from B V \V pure are duplcated and left n V. The relaton between a node n V and ts clone n V s kept n an assocaton table. We defne the functons Clone and Clone - (see eq. 0) to retreve a clone n V from a node n V and vce-versa. Clone : V V Clone : V Clones ( S) V n V : Clone n S (0)

7 Smlarly, Clones (S) s a set composed by clones of S elements. G s defned n eq.. G : V : V, B V Clones B V V x, y : x, y : x V pure V : y V Clone y x, pure 2 () 5.4. Bndng asserton graphs to hardware resources Ths step does not requre any computaton. It only conssts n retrevng nformaton assgned durng the archtectural synthess. Indeed, the latter properly works on the assertonfree graph after the prevous step. Schedulng and allocaton tasks, as well as any optmzaton, s safely trggered. Then, hardware resources assgned to the graph nodes are assocated (bnded) to the correspondng nodes n the multple asserton graphs sets (V ). Requred nformaton s: RTL regster names: t corresponds to the names that hold an asserton nput data durng each tme. Data avalablty date: the date (clock cycles) when prevously mentoned regsters hold the data correspondng to a gven asserton nput varable. By ths way, asserton graphs (G ) contan enough nformaton to generate the montors. However, ths generaton needs one more step sserton graphs sortng sserton graphs need to be sorted. Desgners usually defne sets of assertons n a specfc and relevant order. For nstance, before assertng that a dvson s bound to a partcular range, the dvson result has to be checked to ensure that t s not equal to zero. Therefore, the latter would be asserted frst and the former secondly. s a consequence, asserton branches have to respect ther defnton order, whch s sequental n the applcaton behavoral model. For ths purpose, an executon date s added to each asserton branch. The default executon date s the date when every asserton nput varable has been read. Ths date s stored n a table. fter every default executon date s determned, the table s sorted by asserton executon order as defned by the behavoral model. Ths process s as follows: the table s browsed lnearly and f an executon date s found to be lesser than the prevous one, t s changed to ths prevous date Montor generaton Montors are generated ether as VHDL processes or as PSL assertons, from the nformaton backed by asserton graphs. These montors are passve and resource-free. They do not modfy the archtecture characterstcs. VHDL montor descrptons are useful for smulators whch are not PSLready. Consderng ether PSL or VHDL montor generaton, regster or nput data are read as defned durng the bndng step, and asserton checks are trggered at a specfc clock cycle. On the one hand, PSL generaton makes heavy use of the bult-n prev(arg [,N]) functon to retreve data stored n regsters at defned clock cycles. On the other hand, VHDL montors are bult n two dfferent ways: usng mult-process or sngle-process descrpton. Mult-process approach wraps each montor nto a dedcated process whle the other approach bulds a sngle process that contans all the montor statements. Wth the latter approach, mantanablty s harder, but the smulaton tme overhead ntroduced by the montors s much lower. 6. EXPERIMENTL RESULTS The proposed methodology has been mplemented n the GraphLab HLS tool [4]. Expermentatons have been done to evaluate the correctness of the generated montors as well as the smulaton runtme mpact of montors. The cost of generated PSL/VHDL lnes has been also consdered. pplcatons are: an 8x8 2D Dscrete Cosne Transform (DCT) wth two dfferent latency constrant sets, a standard 8x8 D DCT and a JPEG compresson standard. The number of behavoral assertons ranges from 6 for the D DCT, up to 896 for the JPEG transformaton, n order to reflect some real-case uses. VHDL archtecture smulatons were performed usng ModelSm SE rev 6.6. Tmng results (see Table ) are provded for 300 teratons of each applcaton. The dfferent tests were dvded n two categores: Frst, randomzed stmul were appled both on the behavoral model and the generated RTL descrpton to valdate the correctness of the generated montors. Such valdaton s only possble f every asserton falure happens n both cases. Then, stmul were constraned to fulfll the algorthm precondtons n order to measure the smulaton runtme overhead. Indeed, snce an asserton falure would stop the smulaton, no falure should happen durng a complete measure pass. Results show that the smulaton runtme overhead s lmted (< 5%), and that embeddng every montor nto a sngle VHDL process has vrtually no mpact on the smulaton. Nevertheless, usng one process per asserton

8 pplcaton TBLE. Expermental results (smulaton tmes are for 300 teratons) # behavoral # PSL montor # VHDL Smulaton # assertons Smulaton mode asserton lnes lnes montor lnes tme 8x8 D DCT 6 8 (usng loops) x8 2D DCT (Low Latency) 8x8 2D DCT (Hgh Latency) JPEG Transformaton (Low Latency) JPEG Transformaton (Hgh Latency) (usng loops) (usng loops) (usng loops) (usng loops) Normal 0.28s Overhead VHDL Sngle-process 0.285s +.49% VHDL Mult-process 0.289s +2.85% Normal s VHDL Sngle-process s +0.46% VHDL Mult-process s +2.30% Normal 25.56s VHDL Sngle-process s +0.58% VHDL Mult-process s +4.20% Normal 83.89s VHDL Sngle-process s +0.40% VHDL Mult-process s +.35% Normal 3.25s VHDL Sngle-process 32.09s +0.74% VHDL Mult-process s +2.76% checker ncreases the overhead sgnfcantly. s expected, hgher montor mantanablty goes wth lower smulaton performances. 7. CONCLUSION ssertons-based Verfcaton can greatly speed up the debug process of the ntegraton or the reuse of an IP. Therefore, the automatc propagaton of behavoral assertons to the RTL level durng an HLS synthess leverages the debug possbltes wth a mnmal effort. The methodology defned n ths paper enables HLS generaton of archtectures that are more sutable for drect functonal verfcaton and n-crcut transacton verfcaton. Future works wll target drect behavoral asserton transformaton nto fully syntheszable montors n a sngle archtecture (computaton data path and montors), n order to enhance verfcaton durng the mplementaton steps for emulaton or slcon-debuggng purposes. 8. REFERENCES [] Bortolam J., Leveragng system models for RTL functonal verfcaton. (2007). [2] Bhadra J., badr MS., Wang L-C., Ray S., Survey of Hybrd Technques for Functonal Verfcaton. IEEE Desgn and Test of Computers, vol. 24, pp (2007) [3] Foster H., Lacey D., Krolnk., sserton-based Desgn. 2nd ed. Norwell, M, US. Kluwer cademc Publshers (2003) [4] Lavagno L., Martn G., Scheffer L., Electronc Desgn utomaton for Integrated Crcuts Handbook - 2 Volume Set. Boca Raton, FL, US. CRC Press, Inc. (2006) [5] Coussy P., Takach., Specal Issue on Hgh-Level Synthess. IEEE Desgn and Test of Computers, vol. 26 (2009) [6] Martn G., Smth G., Hgh-Level Synthess: Past, Present, and Future. IEEE Desgn and Test of Computers, vol. 26, pp (2009) [7] Kundu S., Lerner S., Gupta R., Hgh-Level Verfcaton. IPSJ Transactons on System LSI Desgn Methodology, vol. 2, pp (2009) [8] Meyer B., pplyng Desgn by Contract. Computer IEEE, vol. 25, pp (992) [9] Gharehbagh a, Yaran B, Hessab S, Goudarz M, n asserton-based verfcaton methodology for system-level desgn. Computers & Electrcal Engneerng, vol. 33, pp (2007) [0] Currer J., Sttt G., George D., Hgh-level synthess technques for n-crcut asserton-based verfcaton. In: Parallel & Dstrbuted Processng, Workshops and Phd Forum (IPDPSW), pp. --8 (200) [] Carreras C., López J., Neto-Taladrz O., Bt-Wdth Selecton for Data-Path Implementatons. In: Proc. 2th ntl. symposum on System synthess, pp 4--9 (999) [2] ho V., Lam MS., Seth R., Ullman JD., Complers - Prncples, Technques, and Tools (2nd Edton). ddson Wesley (2006) [3] Kav KM., Buckles BP., Bhat U., formal defnton of data flow graph models. IEEE Transactons on Computers vol. 00, pp (2006) [4] Le Gal B., Casseau E., Word-Length ware DSP Hardware Desgn Flow Based on Hgh-Level Synthess. Journal of Sgnal Processng Systems, Sprnger. Onlne, pp --7 (200)