Memory Interface. More Realistic Block Diagram: Issue memory request. Is it a read or a write? Memory asks CPU to wait

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Marilynn Chandler
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1 CPU Design

2 Memory Interface More ealistic Block Diagram: Issue memory request Is it a read or a write? PC I equest ead/write Wait M Memory Memory asks CPU to wait LD/ST Data Instructions M B Memory Buffer egister Decouple memory system from internal processor operation

3 Memory Interface No common clock between CPU and memory Follow asynchronous 4-cycle handshake request/wait (ack( ack) protocol 1. equest sserted equest 2. Wait Unasserted ead/write 3. equest Unasserted Data From Memory To Memory 4. Wait sserted Wait ead Cycle Write Cycle Hi-to-Lo transition on Wait implies that data is ready (read) or data has been latched by memory (write)

4 Memory Interface State Diagram Fragments for ead/write Cycles ead Cycle Wait M ddressbus; 1 ead/write; 1 equest; DataBus MB; Wait Write Cycle M ddressbus; 0 ead/write; 1 equest; MB DataBus; Wait Wait Wait 0 equest; Wait 0 equest; Wait Wait State 1: drive address bus assert read request catch data into MB State 2: unassert request hold in state until Wait reasserted Normal Convention: If register transfer op NOT asserted, it need not be mentioned in state diagram

5 Bussing Strategies egister-to-egister Coummunications Point-to-point Single shared bus Multiple special purpose busses Tradeoffs between datapath/control complexity and amount of parallelism supported by the hardware Case study: Four general purpose registers that must be able to exchange their contents Swap instruction must be supported: SWP(i i, j) i -> j; j -> i;

6 Bussing Strategies Point-to-Point Connection Scheme Four registers interconnected via 4:1 Mux's and point-to-point connections Edge-triggered N bit registers controlled by LDi signals N x 4:1 MUXes per register, controlled by Si<1:0> signals S0<1:0> MUX S1<1:0> MUX S2<1:0> MUX S3<1:0> MUX LD0 0 LD1 1 LD2 2 LD3 3 egister transfers 1 -> 0 and 2 -> 3 01 > S0<1:0>; 10 > S3<1:0>; 1 > LD0; 1 > LD3; Enable path from 1 to 0 Enable path from 2 to 3 ssert load for 0 ssert load for 3

7 Bussing Strategies When control signals are asserted and when they take place: X Y 01 S0<1:0>; 10 S3<1:0>; 1 LD0; 1 LD3; Enter state X: Multiplexer control signals asserted 1 outputs arrive at 0 inputs 2 outputs arrive at 3 inputs LD signals asserted Do not take effect until next rising clock On entering state Y: LD signals are synchronous and take effect at the same time as the state transition! Moore Machine State Diagram

8 Bussing Strategies Point-to-Point Scheme Pluses and Minuses: + transfer a new value into each of the four registers at the same time + register swap implemented in a single control state - 5 gates to implement 4:1 MUX 32 bit wide datapath implies (32 bits/registers) x (5 gates/bit) x (4 registers) = 640 gates! very expensive implementation

9 Single Bus Interconnection Bussing Strategies S<1:0> MUX Single Bus LD0 0 LD1 1 LD2 2 LD3 3 per register MUX block replaced by single block 25% hardware cost of previous alternative shared set of pathways is called a BUS Single bus becomes a critical resource -- used by only one transfer at a time

10 Bussing Strategies Example: 1 -> 0 and 2 -> 3 State X: (1 > 0) 01 > S<1:0>; 1 > LD0; State Y: (2 > 3) 10 > S<1:0>; 1 > LD3; Datapath no longer supports two simultaneous transfers! Thus two control states are required to perform the transfers

11 SWP Operation Bussing Strategies special TEMP register must be introduced ("egister 4") MUX's become 5:1 rather than 4:1 State X: (1 > 4) 001 > S<2:0>; 1 > LD4; Three states are required rather than one! plus extra register and wider mux State Y: (2 > 1) 010 > S<2:0>; 1 > LD1; More More control control states states because this this datapath supports less less parallel parallel activity activity State Z: (4 > 2) 100 > S<2:0>; 1 > LD2; Engineering choices made based on how frequently multiple transfers take place at the same time

12 Bussing Strategies lternatives to Multiplexors : Tri-state buffers LD0 S<1:0> D E C O LD1 1 LD2 2 LD3 3 Only one register's contents gated to shared bus at a time

13 Multiple Busses Bussing Strategies eal datapaths are a compromise between the two extremes egister Transfer Diagram Single Bus Design Memory ddress Bus M P C I C BUS B M B Memory Data Bus egister transfer operations: PC > PC > BUS I > BUS C > BUS MB > BUS LU esult > BUS BUS > PC BUS > I BUS > C BUS > MB BUS > LU B BUS > M C > LU ("hardwired")

14 Bussing Strategies egister Transfer for Single Bus Design Instruction Interpretation for "DD Mem[X]" Fetch Operand Cycle 1: I<operand address> > BUS; BUS > M; Cycle 2: Memory ead; Databus > MB; Perform DD Cycle 3: Write esult Cycle 4: MB > BUS; BUS > LU B; C > LU ; DD; LU esult > BUS; BUS > C; equires latch for LU esult 4 cycles are needed

15 Multiple Busses Bussing Strategies Three Bus Design -- Supports more parallelism ddress Bus esult Bus Memory ddress Bus M P C I C B M B Memory Data Bus Memory Bus Single bus replaced by three busses: Memory Bus (MBUS) esult Bus (BUS) ddress Bus (BUS)

16 Bussing Strategies Instruction Interpretation for "DD Mem[X]" Fetch Operand Cycle 1: I<operand address> > BUS; BUS > M; Cycle 2: Memory ead; Databus > MB; Perform DD and Write esult Cycle 3: MB > MBUS; MBUS > LU B; C > LU ; DD; LU esult > BUS; BUS > C; Implemented in three cycles rather than four dvantage of separate BUS: overlap PC > M with instruction execution

17 Processor Specification Instruction Format: Load from memory: Mem[XXX] -> C; Store to memory: C -> Mem[XXX]; dd from memory: C + Mem[XXX] -> C; Op Code 00 = LD 01 = ST 10 = DD 11 = BN Branch if accumulator is negative: C < 0 -> XXX -> PC; ddress Memory Interface: M M B 14 equest ead/write Wait 16 Memory 14 [0:2-1] <15:0>

18 Deriving the State Diagram and Datapath First pass state diagram eset Instruction Fetch Instruction Decode LD ST DD BN Instruction Execution

19 ssume Synchronous Mealy Machine: Transitions associated with arcs rather than states eset State (State 0) and Instruction Fetch Sequence On eset: zero the PC Mem equest unasserted Mem asserts Wait signal Instruction Fetch: issue read request 4 cycle handshake on Wait signal Note: No explicit mention of the busses being used to implement register transfers! eset/ 1 ead/write, 1 equest, M Memory ES IF0 IF1 eset/ PC M, PC + 1 PC eset/0 PC M Memory, 1 ead/write, 1 equest Mem MB IF2 MB I

20 Instruction Decode State ID I<15:14>= LD0 ST0 D0 B0 Four Way Next State Branch based on opcode bits Load (Memory ead) Sequence Store (Memory Write) Sequence dd Sequence Branch Sequence

21 Load (Memory ead) Sequence like IFetch,, except that operand address comes from I and data should be loaded into C 1 ead/write, 1 equest, M Memory ID LD0 LD1 I<15:14>=00/ I<13:0> M M Memory, 1 ead/write, 1 equest Mem MB LD2 MB C ES

22 Store (Memory Write) Sequence ID 0 ead/write, 1 equest, M Memory, MB Memory I<15:14>=01/ I<13:0> M, C MB ST0 M Memory, MB Memory, 0 ead/write, ST1 1 equest ST2 ES

23 dd Sequence Similar to Load sequence dd MB, C rather than simply transfer MB to C ID I<15:14>=10/ I<13:0> M 1 ead/write, 1 equest, M Memory D0 D1 M Memory, 1 ead/write, 1 equest Mem MB D2 ES MB + C C

24 Branch Sequence ID I<15:14> = 11/ B0 C<15> = 1/ I<13:0> PC C<15> = 0/ eplace PC with Operand ddress if C < 0 ES Otherwise, do nothing

25 evised/complete State Diagram Simplify Wait Looping Eliminate some Wait states t this point, Wait must be asserted, so why loop on Wait? ES IF0 IF1 IF2 ID eset LD0 ST0 D0 B0 Why loop on Wait when resync will take place at state IF0? LD1 ST1 D1 LD2 D2

26 State Machine Inputs and Outputs so far: Inputs: eset Wait I<15:14> C<15> Outputs: 0 > PC PC + 1 > PC PC > M M > Memory ddress Bus Memory Data Bus > MB MB > Memory Data Bus MB > I MB > C C > MB C + MB > C I<13:0> > M I<13:0> > PC ead/write equest

27 Processor Signal Flow Memory eset Wait Mem ddr Bus Mem Data Bus C O N T O L ead/write equest 0 PC PC + 1 PC PC M M Memory ddress Bus Memory Data Bus MB MB Memory Data Bus MB I MB C C MB C + MB C I<13:0> M I<13:0> PC I<15:14> C<15> D T P T H

28 Mapping onto datapath operations Specification so far is independent of bussing strategy Implied transfers (point-to-point connection scheme) : Operand Fetch IFetch Branch Store dd Memory ddress Bus M P C I C dd IFetch B dd Load M B Memory Data Bus Observe that instruction fetch and operand fetch take place at different times This implies that I, PC, and M transfers can be implemented by single bus (ddress Bus) Combine MB, I, LU B, and C connections (Memory Bus) Combine LU, C, and MB connections (esult Bus) --> Three bus architecture

29 ddress Bus esult Bus Memory ddress Bus M P C I C B M B Memory Data Bus Memory Bus C has two inputs, BUS and MBUS (Other registers except MB have single input and output) Dual ported configuration is more complex Better idea: reuse existing paths where possible MB > C transfer implemented by PSS B LU operation

30 Detailed implementation of register transfer operations More detailed control operations are called microoperations One register transfer operation = several microoperations Some operations directly implemented by functional units: e.g., 0 -> PC, PC + 1 -> PC Some operations require multiple control operations: e.g., PC -> M implemented as PC -> BUS and BUS -> M ddress Bus M PC LD PC BUS CL CNT Load Input BUS M Tri-state Control 0 PC PC + 1 PC PC implemented by counter with COUNT and CLE inputs

31 Timing of State Changes and Microoperations CLK ES IF0 IF1 Deferred till next clock edge Takes place immediately Deferred till next clock edge eset 0 PC PC + 1 PC PC BUS BUS M PC gets 0 PC on BUS M latches BUS PC gets PC + 1

32 elationship between register transfer and microoperations: egister Transfer Microoperations 0 -> PC 0 -> PC (delayed); PC + 1 -> PC PC -> M M -> ddress Bus Data Bus -> MB MB -> Data Bus MB -> I MB -> C PC + 1 -> PC (delayed); PC -> BUS (immediate), BUS -> M (delayed); M -> ddress Bus (immediate); Data Bus -> MB (delayed); MB -> Data Bus (immediate); MB -> MBUS (immediate), MBUS -> I (delayed); MB -> MBUS (immediate), LU PSS B (immediate), LU esult -> BUS (immediate), BUS -> C (delayed);

33 egister Transfer Microoperations C -> MB C -> LU (immediate), LU PSS (immediate), BUS -> MB (delayed); C + MB -> C C -> LU (immediate), MB -> MBUS (immediate), MBUS -> LU B (immediate), LU DD (immediate), LU esult -> BUS (immediate), BUS -> C (delayed); I<13:0> -> M I -> BUS (immediate), BUS -> M (delayed); I<13:0> -> PC I -> BUS (immediate), BUS -> PC (delayed); 1 -> ead/write ead (immediate); 0 -> ead/write Write (immediate); 1 -> equest equest (immediate); Special microoperations for MB -> MBUS, MBUS -> LU B, C > LU, and LU esult > BUS not strictly necessary (hardwired)

34 evised microoperation signal flow Memory eset Wait Mem ddr Bus Mem Data Bus C O N T O L ead/write equest 0 PC PC + 1 PC PC BUS I BUS BUS M BUS PC M Memory ddress Bus Memory Data Bus MB MB Memory Data Bus MBUS I LU PSS BUS C BUS MB LU DD LU PSS B D T P T H 5 inputs 15 datapath control lines 2 memory control lines I<15:14> C<15>

Moore EECS150. Implement of Processor FSMs. Memory-Register Interface Timing. Processor / Memory Interface. Processor Signal FLow

Moore EECS150. Implement of Processor FSMs. Memory-Register Interface Timing. Processor / Memory Interface. Processor Signal FLow Moore RES PC EECS5 IF PC MR, PC + PC Section Controller Implementations Fall Note capture of MBR in these states IF IF IF3 O MR Mem,,, Mem MBR MBR IR = = = IR MR, L IR MR ST C MBR MR Mem, MR Mem, L, ST,,,