Moore EECS150. Implement of Processor FSMs. Memory-Register Interface Timing. Processor / Memory Interface. Processor Signal FLow

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Moore RES PC EECS5 IF PC MR, PC + PC Section Controller Implementations Fall Note capture of MBR in these states IF IF IF3 O MR Mem,,, Mem MBR MBR IR = = = IR MR, L IR MR ST C MBR MR Mem, MR Mem, L,

Time-State Method Partition FSM into multiple communicating FSMs Exploit MSI Functionality: Counters, Multiplexers, ecoders Microprogramming: ROM-based methods irect encoding of next states and

1 Moore RES PC EECS5 IF PC MR, PC + PC Section Controller Implementations Fall Note capture of MBR in these states IF IF IF3 O MR Mem,,, Mem MBR MBR IR = = = IR MR, L IR MR ST C MBR MR Mem, MR Mem, L, ST,,, Mem MBR MBR Mem = IR MR BR = = MR Mem, BR, IR PC, Mem MBR L MBR C MBR + C C EECS5 - Fall -4 Implement of Processor FSMs Classical Finite State Machine esign ivide and Conquer pproach: Time-State Method Partition FSM into multiple communicating FSMs Exploit MSI Functionality: Counters, Multiplexers, ecoders Microprogramming: ROM-based methods irect encoding of next states and outputs EECS5 - Fall - Memory-Register Interface Timing WIT Mem Bus Latch MBR IF IF IF IF IF3 Invalid ata Latched Invalid ata Latched Valid ata Latched Valid data latched on IF to IF3 transition because data must be valid before can go low ata Valid EECS5 - Fall -5 Processor / Memory Interface Processor Signal FLow Problem: The processor and memory often do not share the same clock. Solution: Use appropriate handshaking EECS5 - Fall -3 EECS5 - Fall -

2 Moore Machine iagram Clock IR<5> IR<4> C<5> Next State State Output PC PC + PC BUS MR MR Memory ddress Bus Memory ata Bus MBR MBR Memory ata Bus MBUS IR MBUS LU B MBUS C RBUS C states, 4 bit state register Next State : 9 Inputs, 4 Outputs Output : 4 Inputs, 8 Outputs These can be implemented via ROM or PL/PL Next State: 5 x 4 bit ROM Output: x 8 bit ROM EECS5 - Fall -7 Synchronous Mealy Machines Standard Mealy Machine has asynchronous outputs These change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges One approach: non-overlapping clocks Synchronizer Circuitry at at Inputs Inputs and and Outputs Q ' Q ' Output STTE STTE STTE ' Q Output Output EECS5 - Fall - Q ' Moore Machine State Table IR<5> IR<4> C<5> Current State Next State Register Transfer Ops X X X X X RES () X X X X RES () IF () PC X X X X IF () IF () PC MR, PC + PC X X X IF () IF () X X X IF () IF () X X X IF () IF () MR Mem, Read, X X X IF () IF3 () {, Mem MBR X X X IF3 () IF3 () MBR IR X X X IF3 () O () X X O () L () X X O () ST () X X O () () X X O () BR () X X X X L () L () IR MR X X X L () L () MR Mem, Read, X X X L () L (){, Mem MBR X X X X L () IF () MBR C X X X X ST () ST () IR MR, C MBR X X X ST () ST () MR Mem, Write, X X X ST () IF (){, MBR Mem X X X X () () IR MR X X X () () MR Mem, Read, X X X () (){, Mem MBR X X X X () IF () MBR + C C X X X BR () IF () X X X BR () BR () X X X X BR () IF () IR PC EECS5 - Fall -8 Synchronous Mealy Machines Case I: Synchronizers at Inputs and Outputs cycle cycle cycle S / S ' S ' asserted in Cycle, becomes asserted after cycle delay! This is clearly overkill! EECS5 - Fall - State Transition Table Observations: Extensive use of on't Cares Inputs used only in a small number of state e.g., C<5> examined only in BR state IR<5:4> examined only in O state Some outputs always asserted in a group ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step Synchronous Mealy Machine Case II: Synchronizers on Inputs cycle cycle cycle S S / S S ' '/ asserted in Cycle, follows in next cycle Same as using delayed signal (') in Cycle! EECS5 - Fall -9 EECS5 - Fall -

3 Synchronous Mealy Machines Case III: Synchronized Outputs cycle cycle cycle S / S ' asserted during Cycle, ' asserted in next cycle Effect of delayed one cycle EECS5 - Fall -3 Time State (ivide & Conquer) Time State FSM Most instructions follow same basic sequence iffer only in detailed execution sequence Time State FSM can be parameterized by opcode and C states Instruction State: stored in IR<5:4> Condition State: stored in C<5> = = IR = = L ST BRN C<5>= C (L + ) C < T7 C<5>= EECS5 - Fall - T T T T3 T4 T5 T BRN C / (L + ST + ) BRN + (ST )/ Synchronous Mealy Machines Implications for Processor FSM lready erived Consider inputs:,, IR<5:4>, C<5> Latter two already come from registers, and are sync'd to clock Possible to load IR with new instruction in one state & perform multiway branch on opcode in next state Best solution for and : synchronized inputs Place flipflops between these external signals and the control inputs to the processor FSM Sync'd versions of and delayed by one clock cycle Time State (ivide & Conquer) eneration of Microoperations PC: PC + PC: T PC MR: T MR Memory ddress Bus: T + T (L + ST + ) Memory ata Bus MBR: T + T (L + ) MBR Memory ata Bus: T ST MBR IR: T4 MBR C: T7 L C MBR: T5 ST C + MBR C: T7 IR<3:> MR: T5 (L + ST + ) IR<3:> PC: T BRN : T + T (L + ) : T ST : T + T (L + ST + ) EECS5 - Fall -4 EECS5 - Fall -7 Time State ivide and Conquer Overview Classical pproach: Monolithic Implementations lternative "ivide & Conquer" pproach: ecompose FSM into several simpler communicating FSMs Time state FSM (e.g., IFetch, ecode, Execute) Instruction state FSM (e.g., L, ST,, BRN) Condition state FSM (e.g., C <, C ) Jump Counter Concept Implement FSM using MSI functionality: counters, mux, decoders Pure jump counter: only one of four possible next states N HOL LO CLR N+ XX Single "Jump State" function of the current state Hybrid jump counter: Multiple "Jump States" function of current state + inputs EECS5 - Fall -5 EECS5 - Fall -8

4 RES Pure Jump Counter Inputs Implementation Example IF Count, Load, Clear Clear Load Count CLOCK Jump State Synchronous Counter State Register NOTE: No inputs to jump state logic State assignment attempts to take advantage of sequential states L 5 IF IF 3 O 4 ST 8 BR 3 L ST 9 blocks implemented via discrete logic, PLs/PLs, ROMs L 7 EECS5 - Fall -9 EECS5 - Fall - Problem with Pure Jump Counter ifficult to implement multi-way branches O L ST BR al State iagram Extra States: O 7 L ST 4 O 5 8 O BR 9 Pure Jump Counter State iagram EECS5 - Fall - Implementation Example, Continued = (s + s5 + s8 + s) + (s + s3) + (s + s + s9 + s) = (s + s3) + (s + s + s9 + s) CLR = + s7 + s + s3 + (s9 ) CLR = s7 s s3 (s9 + ) L = s4 Contents of Jump State ROM ddress Contents (Symbolic State) (L) (ST) () (BR) EECS5 - Fall -3 Hybrid Jump Counter Inputs Count, Load, Clear Clear Load Count CLOCK Jump State Synchronous Counter State Register Load inputs are function of state and FSM inputs EECS5 - Fall - /S9 Implementation Example, continued Cnt PL /S S Implement /S9 S9 using active lo /S S 5 7 HOL /S5 PL /S3 S /S4 /S S 3 5 /S3 7 /S S P 4 /S 3 9 T 3 /S 5 RCO 8 /S Jump State 9 /S9 3 Q 8 9 /S8 IR5 IR<5> 5 C QC C 7 8 /S7 IR<4> 4 B QB 3 B 7 /S IR4 3 Q /S /S4 /S4 LO / 3 4 /S3 CLR 3 /S7 /S OR N /S /S /S /S3 / / NOTE: ctive lo Implement CLR outputs from EECS5 - Fall decoder -4

5 Jump Counter Branch Sequencers CLR,, L implemented via Mux CLR = CLRm + CLR = CLRm + /CLRm / /CLR Jump State 3 IR5 IR<5> IR4 IR<4> /L / /CLR / P T 3 RCO Q C QC B QB Q LO CLR 54 C B \S3 \S \S \S \S9 \S8 \S7 \S \S5 \S4 \S3 \S \S \S I n p u t s 4 Way Branch Sequencer Mux Mux β α a a a a3 a4 a5 x x x x 4 Word ROM Z Y X W C S o i n g t n r o l a l s N W X Y Z ctive Lo outputs: hi input inverted at the output Note that is active hi on counter so invert MUX inputs! S3 S S S S3 S S S S3 S S S E4 E4 E4 + + E E E E E E E E E E9 / E9 E9 EOUT EOUT EOUT E7 E7 /CLRm E7 E E E E4 E4 + E4 E E E / E E E E E E EECS5 - Fall -5 /L state Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states EECS5 - Fall -8 Microoperation implementation PC = PC + PC = S PC MR = S MR Memory ddress Bus = (S + S + S5 + S + S8 + S9 + S + S) Memory ata Bus MBR = (S + S + S) MBR Memory ata Bus = (S8 + S9) MBR IR = S3 MBR C = S7 C MBR = IR5 IR4 S4 C + MBR C = S IR<3:> MR = (IR5 IR4 + IR5 IR4 + IR5 IR4) S4 IR<3:> PC = C5 S3 = (S + S + S5 + S + S + S) = (S8 + S9) = (S + S + S5 + S + S8 + S9 + S + S) :, CLR, L function of current state + Why not store these as outputs of the Jump State ROM? Make and Current State part of ROM address 3 x as many words, 7 bits wide EECS5 - Fall - Branch Sequencer Processor CPU esign Example S3 S S S s<3> s<> s<> s<> S3 S S S 5 5 E4 E4 C<5> C<5> E E E E E E E9 E9 EOUT E7 EOUT \α E7 E E IR<5> E4 IR<4> E4 E E E E + E + E lpha, Beta multiplexer input setup EECS5 - Fall -9 \β Branch Sequencers Concept Implement Next State via ROM ddress ROM with current state and inputs Problem: ROM doubles in size for each additional input Note: Jump counter trades off ROM size vs. external logic Only jump states kept in ROM Even in hybrid approach, state + input subset form ROM address Branch Sequencer: between the extremes Next State stored in ROM Each state limited to small number of next states lways a power of Observe: only a small set of inputs are examined in any state EECS5 - Fall -7 Example Processor FSM ROM RESS ROM CONTENTS (, Current State, a, b) Next State Register Transfer Operations RES X X (IF) PC MR, PC + PC IF (IF) (IF) MR Mem, Read, IF (IF) MR Mem, Read, (IF) Mem MBR IF (IF) (O) MBR IR O (L) IR MR (ST) IR MR, C MBR () IR MR (BR) IR MR L X X (L) MR Mem, Read, L (L) Mem MBR (L) MR Mem, Read, L X X (RES) MBR C ST X X (ST) MR Mem, Write,, MBR Mem ST (RES) (ST) MR Mem, Write,, MBR Mem X X () MR Mem, Read, () () MR Mem, Read, X X (RES) MBR + C C BR (RES) (RES) IR PC EECS5 - Fall -3

6 Branch Sequencers α and β MUX Control Horizontal Microprogramming lternative Horizontal Implementation 3 n- n- n- n- atapath Control Signals Horizontal Branch Sequencer α, β Mux bits 4 x 4 Next State bits Control operation bits I N P U T S M α U M X U X β n bit state register 3 4: MUX bit Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be :! bit n : MUX bit dding length to ROM word saves on bits vs. doubling words Vertical format: (4 + 4) x 4 = 5 ROM bits Horizontal format: (4 + 4 x 4 + ) x = 5 ROM bits EECS5 - Fall -3 α mux β mux 4 bits total Next States MBR BUS RBUS C C LU MBUS LU B LU PSS B MR ddress Bus MBR ata Bus BUS IR BUS MR ata Bus MBR PC PC + PC C RBUS LU Result RBUS 3 EECS5 - Fall -34 Microprogramming How to organize the control signals Implement control signals by storing 's and 's in a ROM Horizontal vs. vertical microprogramming Horizontal: ROM output for each control signal Vertical: encoded control signals in ROM, decoded externally some mutually exclusive signals can be combined helps reduce ROM length EECS5 - Fall -3 Horizontal Microprogramming Moore Processor ROM Current State (ddress) RES () IF () IF () IF () IF3 () O () L () L () L () ST () ST () () () () BR () BR () α mux β mux Next States 3 MBR BUS RBUS C C LU MBUS LU B LU PSS B MR ddress Bus MBR ata Bus BUS IR BUS MR ata Bus MBR PC PC + PC C RBUS LU Result RBUS lpha inputs: =, = IR<5> Beta inputs: = C<5>, = IR<4> EECS5 - Fall -35 Microprogramming Register Transfer/Microoperations 4 Register Transfer operations become Microoperations: MBR BUS RBUS C C LU MBUS LU B LU PSS B MR ddress Bus MBR ata Bus BUS IR BUS MR ata Bus MBR PC PC + PC C RBUS LU Result RBUS Horizontal Microprogramming dvantages: most flexibility -- complete parallel access to datapath control points isadvantages: very long control words -- + bits for real processors NOTE: Not all microoperation combinations make sense! Output Encodings: roup mutually exclusive signals Use external logic to decode Example: PC, PC + PC, mutually exclusive Save ROM bit with external :4 ecoder EECS5 - Fall -33 EECS5 - Fall -3

7 Horizontal Microprogramming Partially Encoded Control Outputs C O N T R O L R O M LU PSS B MR ddress Bus MBR ata Bus BUS MR C RBUS RBUS C C LU MBUS LU B LU Result RBUS MBR BUS BUS IR PC :4 PC + PC EC :4 EC ata Bus MBR EECS5 - Fall -37 ROM RESS SYMBOLIC CONTENTS BINRY CONTENTS RES RT PC MR, PC + PC IF RT MR M, Read BJ =, IF IF RT MR M, M MBR, Read BJ =, IF IF RT MBR IR BJ =, IF RT IR MR O BJ IR<5>=, O BJ IR<4>=, ST L RT MR M, Read L RT MR M, M MBR, Read BJ =, L L RT MBR C BJ =, RES BJ =, RES EECS5 - Fall -4 More extensive encoding to reduce ROM word length Typically use multiple microword formats: Horizontal microcode -- next state + control bits in same word Separate formats for control outputs and "branch jumps" may require several microwords in a sequence to implement same function as single horizontal word In the extreme, very much like assembly language programming ROM RESS SYMBOLIC CONTENTS BINRY CONTENTS ST RT C MBR RT MR M, MBR M, Write ST RT MR M, MBR M, Write BJ =, RES BJ =, ST O BJ IR<4>=, BR RT MR M, Read RT MR M, M MBR, Read BJ =, RT C + MBR C BJ =, RES BJ =, RES BR BJ C<5>=, RES RT IR PC BJ C<5>=, RES EECS5 - Fall words x ROM bits = 3 bits total versus x 38 = 8 bits horizontal EECS5 - Fall -4 Vertical Programming Branch Jump Compare indicated signal to or Register Transfer Source, estination, Operation ROM Bits Branch Jump Format Condition Select Type Condition Compare Next ddress = = C<5> = IR<5> = IR<4> Register Transfer Format Source estination Operation : NO OP : NO OP : NO OP : : RBUS C : : : MBUS IR : LU PSS B : : BUS MR : PC : MR M : M MBR : PC + PC : Read : C RBUS : : Write : LU Res RBUS : : MBR M EECS5 - Fall -39 Controller Block iagram ROM ddress T SRC ST OP LU PSS B PC 3:8 3 EC 4 PC + PC 5 Read Write Enb 7 RBUS C BUS IR BUS MR 3:8 3 M MBR EC 4 5 Enb 7 MBR M 3:8 3 MBR BUS EC 4 MR M 5 C RBUS LU Res RBUS Enb 7 L CLR C<5> Cond µpc IR<5> Clk IR<4> EECS5 - Fall -4

8 Condition Condition Selector C<5> IR<5> IR<4> 4: MUX Condition Comparator Microinstruction Type Microinstruction Type L EECS5 - Fall -43 Writeable Control Store Part of control store addresses map into RM llows assembly language programmer to implement own instructions Extend "native" instruction set with application specific instructions Requires considerable sophistication to write microcode Not a popular approach with today's processors Make the native instruction set simple and fast Write "higher level" functions as assembly language sequences EECS5 - Fall -44

Alternative controller FSM implementation approaches based on:

Alternative controller FSM implementation approaches based on: Overview lternative controller FSM implementation approaches based on: classical Moore and Mealy machines jump counters microprogramming (ROM) based approaches branch sequencers horizontal microcode vertical