6.2 Instruction Set Summary

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1 6.2 Instruction Set Summary This section summarizes the instruction set and instruction set opcodes for the C5x. Table 6 4 through Table 6 10 alphabetically list the C5x instructions within the following functional groups: Accumulator memory reference instructions (Table 6 4) Auxiliary registers and data memory page pointer instructions (Table 6 5 on page 6-13) Parallel logic unit (PLU) instructions (Table 6 6 on page 6-14) TREG0, PREG, and multiply instructions (Table 6 7 on page 6-15) Branch and call instructions (Table 6 8 on page 6-17) I/O and data memory operation instructions (Table 6 9 on page 6-20) Control instructions (Table 6 10 on page 6-21) The number of words that an instruction occupies in program memory is specified in the Words column of the table. Several instructions specify two values in the Words column because different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies one word when the operand is a short immediate value or two words if the operand is a long immediate value. The number of cycles that an instruction requires to execute is in the Cycles column of the table. The tables assume that all instructions are executed from internal program memory (ROM) and internal data memory (RAM). The cycle timings are for single-instruction execution, not for repeat mode. Additional information is presented in Section 6.3, Instruction Set Descriptions on page Bold typeface indicates instructions that are new for the C5x instruction set. A read or write access to any peripheral memory-mapped register in data s 20h 4Fh will add one cycle to the cycle time shown. This occurs because all peripherals perform these accesses over the TI Bus, which requires an additional cycle. Note that all writes to external memory require two cycles. Reads require one cycle. Any write access immediately before or after a read cycle will require three cycles (refer to Chapter 8). In addition, if two pipelined instructions try to access the same 2K-word single-access memory block simultaneously, one 6-8

2 extra cycle is required. For example, the DMOV instruction when used with the RPT instruction, requires one cycle in the dual-access RAM but requires two cycles in the single-access RAM. Wait states are added to all external accesses according to the configuration of the software wait-state registers described in Section 9.4, Software-Programmable Wait-State Generators, on page Table 6 4. Accumulator Memory Reference Instructions Mnemonic Description ABS Absolute value of ACC; zero carry bit ADCB Add ACCB and carry bit to ACC ADD Add data memory value, with left shift, to ACC Add data memory value, with left shift of 16, to ACC SHFT IAAA AAAA IAAA AAAA 6-32 Add short immediate to ACC kkkk kkkk 6-32 Add long immediate, with left shift, to ACC SHFT 6-32 ADDB Add ACCB to ACC ADDC ADDS ADDT AND Add data memory value and carry bit to ACC with sign extension suppressed Add data memory value to ACC with sign extension suppressed Add data memory value, with left shift specified by TREG1, to ACC AND data memory value with ACCL; zero ACCH IAAA AAAA IAAA AAAA IAAA AAAA IAAA AAAA 6-44 AND long immediate, with left shift, with ACC AND long immediate, with left shift of 16, with ACC SHFT ANDB AND ACCB with ACC BSAR Barrel-shift ACC right SHFT 6-83 Peripheral memory-mapped register access Assembly Language Instructions 6-9

3 Table 6 4. Accumulator Memory Reference Instructions (Continued) Mnemonic Description CMPL 1s complement ACC CRGT CRLT Store ACC in ACCB if ACC > ACCB Store ACC in ACCB if ACC < ACCB EXAR Exchange ACCB with ACC LACB Load ACC to ACCB LACC Load data memory value, with left shift, to ACC SHFT IAAA AAAA Load long immediate, with left shift, to ACC SHFT LACL LACT LAMM Load data memory value, with left shift of 16, to ACC ACCL; zero ACCH Load short immediate to ACCL; zero ACCH Load data memory value, with left shift specified by TREG1, to ACC Load contents of memorymapped register to ACCL; zero ACCH IAAA AAAA IAAA AAAA kkkk kkkk IAAA AAAA or IAAA AAAA NEG Negate (2s complement) ACC NORM Normalize ACC IAAA AAAA OR OR data memory value with ACCL IAAA AAAA OR long immediate, with left shift, with ACC OR long immediate, with left shift of 16, with ACC SHFT Peripheral memory-mapped register access 6-10

4 Table 6 4. Accumulator Memory Reference Instructions (Continued) Mnemonic Description ORB OR ACCB with ACC ROL Rotate ACC left 1 bit ROLB Rotate ACCB and ACC left 1 bit ROR Rotate ACC right 1 bit RORB Rotate ACCB and ACC right 1 bit SACB Store ACC in ACCB SACH SACL Store ACCH, with left shift, in data Store ACCL, with left shift, in data SHF IAAA AAAA SHF IAAA AAAA SAMM Store ACCL in memorymapped register 1 1 or IAAA AAAA SATH SATL Barrel-shift ACC right 0 or 16 bits as specified by TREG1 Barrel-shift ACC right as specified by TREG SBB Subtract ACCB from ACC SBBB Subtract ACCB and logical inversion of carry bit from ACC SFL Shift ACC left 1 bit SFLB Shift ACCB and ACC left 1 bit SFR Shift ACC right 1 bit SFRB Shift ACCB and ACC right 1 bit Peripheral memory-mapped register access Assembly Language Instructions 6-11

5 Table 6 4. Accumulator Memory Reference Instructions (Continued) Mnemonic SUB Description Subtract data memory value, with left shift, from ACC Subtract data memory value, with left shift of 16, from ACC Subtract short immediate from ACC SHFT IAAA AAAA IAAA AAAA kkkk kkkk Subtract long immediate, with left shift, from ACC SHFT SUBB Subtract data memory value and logical inversion of carry bit from ACC with sign extension suppressed IAAA AAAA SUBC Conditional subtract IAAA AAAA SUBS SUBT Subtract data memory value from ACC with sign extension suppressed Subtract data memory value, with left shift specified by TREG1, from ACC IAAA AAAA IAAA AAAA XOR Exclusive-OR data memory value with ACCL IAAA AAAA Exclusive-OR long immediate, with left shift of 16, with ACC Exclusive-OR long immediate, with left shift, with ACC SHFT XORB Exclusive-OR ACCB with ACC ZALR Zero ACCL and load ACCH with rounding IAAA AAAA ZAP Zero ACC and PREG Peripheral memory-mapped register access 6-12

6 Table 6 5. Auxiliary Registers and Data Memory Pointer Instructions Mnemonic Description ADRK Add short immediate to AR kkkk kkkk 6-43 CMPR Compare AR with ARCR as specified by CM bits CM 6-96 LAR ARx ARX IAAA AAAA Load short immediate to ARx ARX kkkk kkkk Load long immediate to ARx ARX LDP DP bits IAAA AAAA Load short immediate to DP bits I kkkk kkkk MAR Modify AR IAAA AAAA SAR SBRK Store ARx in data memory location Subtract short immediate from AR ARX IAAA AAAA kkkk kkkk Assembly Language Instructions 6-13

7 Table 6 6. Parallel Logic Unit (PLU) Instructions Mnemonic Description APL AND data memory value with DBMR, and store result in data IAAA AAAA 6-49 AND data memory value with long immediate and store result in data IAAA AAAA 6-49 CPL Compare data memory value with DBMR IAAA AAAA 6-98 Compare data memory value with long immediate IAAA AAAA 6-98 OPL OR data memory value with DBMR and store result in data IAAA AAAA OR data memory value with long immediate and store result in data IAAA AAAA SPLK Store long immediate in data IAAA AAAA XPL Exclusive-OR data memory value with DBMR and store result in data IAAA AAAA Exclusive-OR data memory value with long immediate and store result in data memory location IAAA AAAA LPH LT PREG high byte TREG IAAA AAAA IAAA AAAA

8 Table 6 7. TREG0, PREG, and Multiply Instructions Mnemonic Description LTA LTD LTP LTS TREG0; add PREG, with shift specified by PM bits, to ACC TREG0; add PREG, with shift specified by PM bits, to ACC; and move data TREG0; store PREG, with shift specified by PM bits, in ACC TREG0; subtract PREG, with shift specified by PM bits, from ACC IAAA AAAA IAAA AAAA IAAA AAAA IAAA AAAA MAC Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG IAAA AAAA MACD Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by program memory value and store result in PREG; and move data IAAA AAAA MADD MADS Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG; and move data Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; multiply data memory value by value specified in BMAR and store result in PREG IAAA AAAA IAAA AAAA Assembly Language Instructions 6-15

9 Table 6 7. TREG0, PREG, and Multiply Instructions (Continued) Mnemonic MPY Description Multiply data memory value by TREG0 and store result in PREG Multiply short immediate by TREG0 and store result in PREG IAAA AAAA k kkkk kkkk kkk Multiply long immediate by TREG0 and store result in PREG MPYA MPYS MPYU PAC SPAC SPAC SPH SPL Add PREG, with shift specified by PM bits, to ACC; multiply data memory value by TREG0 and store result in PREG Subtract PREG, with shift specified by PM bits, from ACC; multiply data memory value by TREG0 and store result in PREG Multiply unsigned data memory value by TREG0 and store result in PREG Load PREG, with shift specified by PM bits, to ACC Subtract PREG, with shift specified by PM bits, from ACC Subtract PREG, with shift specified by PM bits, from ACC Store PREG high byte, with shift specified by PM bits, in data Store PREG low byte, with shift specified by PM bits, in data IAAA AAAA IAAA AAAA IAAA AAAA IAAA AAAA IAAA AAAA SPM Set product shift mode (PM) bits PM SQRA Add PREG, with shift specified by PM bits, to ACC; load data memory value to TREG0; square value and store result in PREG IAAA AAAA

10 Table 6 7. TREG0, PREG, and Multiply Instructions (Continued) Mnemonic SQRS Description Subtract PREG, with shift specified by PM bits, from ACC; load data memory value to TREG0; square value and store result in PREG IAAA AAAA ZPR Zero PREG Table 6 8. Branch and Call Instructions Mnemonic Description B Branch unconditionally to program AAA AAAA 6-52 BACC BACCD Branch to program memory location specified by ACCL Delayed branch to program specified by ACCL BANZ Branch to program memory location if AR not zero 2 4 or 2# AAA AAAA 6-55 BANZD Delayed branch to program if AR not zero AAA AAAA 6-57 BCND Branch conditionally to program 2 4 or 2# TP ZLVC ZLVC 6-59 BCNDD Delayed branch conditionally to program TP ZLVC ZLVC 6-61 BD Delayed branch unconditionally to program AAA AAAA 6-63 CALA Call to subroutine addressed by ACCL Conditions true # Condition false Assembly Language Instructions 6-17

11 Table 6 8. Branch and Call Instructions (Continued) Mnemonic CALAD Description Delayed call to subroutine addressed by ACCL CALL Call to subroutine unconditionally AAA AAAA 6-86 CALLD Delayed call to subroutine unconditionally AAA AAAA 6-87 CC Call to subroutine conditionally 2 4 or 2# TP ZLVC ZLVC 6-89 CCD Delayed call to subroutine conditionally TP ZLVC ZLVC 6-91 INTR NMI Software interrupt that branches program control to program Nonmaskable interrupt and globally disable interrupts (INTM = 1) I NTR# RET Return from subroutine RETC RETCD Return from subroutine conditionally Delayed return from subroutine conditionally TP ZLVC ZLVC or 2# TP ZLVC ZLVC RETD Delayed return from subroutine RETE RETI Return from interrupt with context switch and globally enable interrupts (INTM = 0) Return from interrupt with context switch Conditions true # Condition false 6-18

12 Table 6 8. Branch and Call Instructions (Continued) Mnemonic TRAP Description Software interrupt that branches program control to program 22h XC Execute next instruction(s) conditionally N 01TP ZLVC ZLVC Conditions true # Condition false Assembly Language Instructions 6-19

13 Table 6 9. I/O and Data Memory Operation Instructions Mnemonic Description BLDD Block move from data to data memory Block move from data to data memory with destination address long immediate IAAA AAAA IAAA AAAA BLDP BLPD Block move from data to data memory with source address in BMAR Block move from data to data memory with destination address in BMAR Block move from data to program memory with destination address in BMAR Block move from program to data memory with source address in BMAR IAAA AAAA IAAA AAAA IAAA AAAA IAAA AAAA 6-77 Block move from program to data memory with source address long immediate IAAA AAAA 6-77 DMOV Move data in data memory IAAA AAAA IN LMMR OUT SMMR TBLR TBLW Input data from I/O port to data memory-mapped register Output data from data memory location to I/O port Store memory-mapped register in data Transfer data from program to data memory with source address in ACCL Transfer data from data to program memory with destination address in ACCL IAAA AAAA 2 2 or IAAA AAAA IAAA AAAA 2 2 or IAAA AAAA IAAA AAAA IAAA AAAA Peripheral memory-mapped register access 6-20

14 Table Control Instructions Mnemonic Description BIT Test bit BITX IAAA AAAA 6-64 BITT Test bit specified by TREG IAAA AAAA 6-66 CLRC Clear overflow mode (OVM) bit Clear sign extension mode (SXM) bit Clear hold mode (HM) bit Clear test/control (TC) bit Clear carry (C) bit Clear configuration control (CNF) bit Clear interrupt mode (INTM) bit Clear external flag (XF) pin IDLE IDLE2 Idle until nonmaskable interrupt or reset Idle until nonmaskable interrupt or reset low-power mode LST ST IAAA AAAA ST IAAA AAAA NOP No operation POP POPD PSHD Pop top of stack to ACCL; zero ACCH Pop top of stack to data memory location Push data memory value to top of stack IAAA AAAA IAAA AAAA PUSH Push ACCL to top of stack Assembly Language Instructions 6-21

15 Table Control Instructions (Continued) Mnemonic RPT Description Repeat next instruction specified by data memory value Repeat next instruction specified by short immediate IAAA AAAA kkkk kkkk Repeat next instruction specified by long immediate RPTB Repeat block of instructions specified by BRCR RPTZ Clear ACC and PREG; repeat next instruction specified by long immediate SETC Set overflow mode (OVM) bit Set sign extension mode (SXM) bit Set hold mode (HM) bit Set test/control (TC) bit Set carry (C) bit Set external flag (XF) pin high Set configuration control (CNF) bit Set interrupt mode (INTM) bit SST Store ST0 in data memory location Store ST1 in data memory location IAAA AAAA IAAA AAAA

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