Breakpoints and Breakpoint Detection in Source Level Emulation

Transcription

1 Breakpoits ad Breakpoit Detectio i Source Level Emulatio Gerot Koch 1, Udo Kebschull 1, Wolfgag Rosestiel 2 1 Forschugszetrum Iformatik (FZI), Haid-ud-Neu-Straße 10-14, D Karlsruhe, Germay 2 FZI ad Uiversity of Tübige, Sad 13, D Tübige, Germay Abstract I this paper we discuss, what breakpoits i Source Level Emulatio a are, how we ca work with them ad how we have to chage the cicuit geerated by high level sythesis to do so. We show the details of breakpoit ecodig ad detectio i our approach. The preseted approach allows for breakpoit detectio by hardware meas without seriously slowig dow the circuit or dramatically icreasig its size. 1. Itroductio For years, high level sythesis is of icreasig importace i desig automatio. The icreasig umber of commercial available tools for high level sythesis idicates that the abstractio level of the desig etry will raise to the algorithmic level at least for some kids of applicatios While there is much effort spet i methods for sythesis, there are oly few groups cocetratig o desig validatio ad debuggig of high level specificatios. I geeral, validatio ca be doe by simulatio ad emulatio. Simulatio is a powerful meas to detect mistakes i the specificatio. Some groups work o simulatio tools for whole systems cosistig of hardware ad software ad eve other techologies like mechaics [1][2]. However, simulatio ca oly be applied to the specificatio level, ad eve there, a desig ca oly be partially validated because simulatio is very time cosumig. Validatig at the specificatio level is ot sufficiet, if high level sythesis is applied. There are iterface compoets ad custom compoets i such desigs, which are ot visible at the algorithmic level. So validatio is also ecessary o lower levels of abstractio. But there, simulatio is less applicable because it is too slow. a. Work partially supported by the Deutsche Forschugsgemeischaft (DFG) Emulatio is a techique, which allows for validatio of desigs at a low abstractio level almost i real time [3]. But emulatio works at the gate level. Thus, a desiger caot relate the probed sigals to the specificatio. For this reaso, debuggig is oly possible at the I/O sigals of the system. Quicktur has addressed this problem with the HDL-ICE [4] system, which allows to relate the probed sigals to a RT-specificatio, but still there is a big gap betwee the algorithmic level ad the level, where validatio is doe. I [10], we have proposed Source Level Emulatio (SLE) as a method to close this gap by combiig behavioral simulatio with hardware emulatio. The idea of SLE is to ru the applicatio o a emulator hardware ad to keep the correlatio betwee hardware elemets ad the behavioral VHDL source such that it is possible to stop the hardware by iterruptig the clock ad to extract values of variables i the source code by readig registers of the circuit. This correlatio is maily obtaied through loggig the sythesis steps of the high level sythesis. SLE allows for symbolic debuggig of a ruig hardware similar to software debuggig. This icludes the examiatio of variables, the settig of breakpoits, ad sigle step operatio. All this is possible with the applicatio ruig as a real hardware implemetatio o a hardware emulator. By backaotatig the values read from the circuit, we ca do debuggig at the source code level. We do ot eed to capture the eviromet of the applicatio i a simulator. We just coect the emulator to the eviromet of the applicatio. There is o eed to write (ofte eormous) simulatio eviromets i VHDL which is eve better sice these simulatio eviromets are at least as fault-proe as the applicatio itself. I this paper, we discuss two importat issues of SLE i more detail: The hardware that we itroduce additioally ito the geerated circuit to set ad detect breakpoits, to read data path registers, ad to cotrol the circuit operatio. The secod issue of this paper is to defie, what a breakpoit is i terms of hardware ad how we ca ma-

2 age to set ad detect such breakpoits without eedig a tremedous hardware overhead ad without extremely slowig dow the circuit. I the ext chapter we discuss the breakpoit issue. I chapter 3 we give a detailed descriptio of the hardware extesios we eed for SLE. We coclude the paper with some results i chapter 4 ad a summary. Y := A + B; A B i++ X := A(i) * B(i); Y := Y + X; A(i) B(i) 2. Breakpoits i SLE 2.1. Breakpoit defiitio High level sythesis geerates a circuit from a software program like specificatio. The circuit cotais a data path, where the data computatios are carried out, ad a cotroller, which cotrols whe a compoet i the data path is active. The cotroller is a fiite state machie that sets cotrol values for the data path ad reacts to coditio values from the data path. Sice we wat to debug a ruig circuit at the source code level, we have to defie a breakpoit as somethig which is visible i the source code. O the other had, a breakpoit must also be visible i the circuit to eable us to detect it. Thus, we defie a breakpoit as a operatio like +, *, etc. If such a operatio is executed by a compoet, we ca detect it i the ruig hardware. Defiitio 1. A breakpoit is a triple (Op, IO, T). It is iterpreted as the time T, at which the iput or output IO of operatio Op trasports data. Defiitio 2. A breakpoit is called detectable breakpoit, if Op is implemeted by a hardware compoet ad if IO is visible i the data path at the RT level. Figure 1 illustrates the defiitios. Part a) shows all iputs ad outputs of a '+' operatio as visible i the data path. Part b) shows a example, where the iput/output X is ot visible due to a optimizatio durig sythesis. I the followig, we will use breakpoit as syoym to detectable breakpoit. The use of o detectable breakpoits is ot allowed sice we caot detect them by hardware meas Breakpoit types Oe possibility to detect the time T of a breakpoit i the hardware is by lookig at the cotroller states, sice the cotroller maages the sequetial behavior of the data path. The relatio betwee the breakpoit time, ad a cotroller state is static ad kow from the sythesis process. I the data path, there are operatios which are always executed i a certai cotroller state. We call breakpoits ADD Y Figure 1. a) A, B, Y as detectable breakpoits ad b) X as o detectable bp at this type of operatios Moore breakpoits. Such a breakpoit is reached, if the cotroller state matches the breakpoit time T. There are also operatios, that are executed at trasitios of cotroller states. To detect breakpoits at those operatios, we eed to kow about the curret state ad the ext state of the cotroller. These breakpoits are called Mealy breakpoits. A Mealy breakpoit is reached, if the cotroller state matches the breakpoit time T ad if the ext state is right oe for the breakpoit. Both, Mealy ad Moore breakpoits, ca be exteded by data depedecy. This allows for settig a coditioal breakpoit. For istace we could say "stop at B i the expressio Y := A * B; if B = 5." More sophisticated coditios are possible, but require also more hardware overhead. Naturally, we could always stop at a breakpoit ad do the evaluatio of the coditioal expressio i software after readig the correspodig values from the circuit. This is ot what we wat, sice it would make it impossible to ru the circuit i its real eviromet. Thus we have to keep the coditios very simple Breakpoit ecodig Mult_Acc a) b) Sice we wat to react, if a breakpoit is reached by iterruptig the circuit, we have to detect the breakpoits by hardware meas. To do that, we eed to ecode the breakpoits i a way that allows for very simple testig whether a cotroller state correspods to a breakpoit or ot. This ecodig of the breakpoit (breakpoit ID) has to satisfy the followig costraits: Differet breakpoits must have differet IDs. For each cotroller state that is elemet of a particular breakpoit set the cotroller must produce the correspodig breakpoit ID. This ca be compared to a breakpoit register. If equal, the breakpoit is reached. Above, we have implicitly metioed. that a breakpoit would correspod to oe cotroller state. The the state Y

3 ecodig would also serve as breakpoit ecodig for hardware breakpoit detectio. The reality is ot as simple. A breakpoit ca be represeted by a whole set of cotroller states. Furthermore, these sets of states ca itersect, as the example i figure 2 shows. For istace this could be caused by path based schedulig [7]. I Figure 2 we have costructed a case to show what if cod the C := M + N; (OP1) else X := X1 + X2; (OP2) ed if; Y1 := A + B; (OP3) Y2 := B + C; (OP4) Y3 := Y1 + A; (OP5) Y4 := Y1 + B; (OP6) Y5 := Y2 + Y3; (OP7) OP1,OP3 OP4,OP5 OP6,OP7 cod OP3,OP4 OP5,OP6 OP7,OP2 cod OP1 OP3 OP4 OP5 OP6 OP7 OP2 Figure 2. Breakpoits represeted by a itersectig set of cotroller states ca happe. For simplicity, we idetify the breakpoit triple (Op, IO, T) by the operatio Op.The code fragmet does ot compute aythig sesible, but a similar case may occur i a real example. If we costrai the hardware resources to two adders ad a comparator, schedulig ad cotroller costructio ca result i a cotroller as show. The left path of the cotroller shows the if-path, the right oe shows the else-path. There are 8 detectable breakpoits, three of them represeted by oe cotroller state, the others represeted by two states each. I state 3, for istace, we have to produce the ID of breakpoit OP3 ad of breakpoit OP4, but we ca oly have oe cotroller output word i this state. A easy but iefficiet way to solve the problem would be to code each breakpoit with three bit ad to have a 6-bit word as cotroller output cotaiig both IDs. The first 3 bit would the idicate OP3, while the last 3 bit would idicate OP4. To detect breakpoit OP3, we would tell the breakpoit comparator to igore the last 3 bit. States 3 ad 4 have to show the same patter i the first 3 bit the. The same rule ca be applied to each state. The we would have to add a 6 bit word to the cotroller outputs just for breakpoit detectio. This ca cause a explosio of the cotroller logic i larger applicatios. I geeral, this ca be formulated as the problem to biary ecode elemets of a arbitrary set structure i a way, that, give a particular subset code, oe ca see whether or ot a elemet is part of that subset just by igorig some bit positios (which are fixed for a subset). As may other problems i sythesis, this is a NP-hard problem. Thus, for the geeral case, a heuristic has to be used A heuristic for breakpoit ecodig The heuristic we use is drive by the followig assumptios ad facts: Usually, if a breakpoit set A itersects with aother breakpoit set B, the A is a subset of B or vice versa. A subset structure like the oe give i Figure 2 ca be costructed, but it will happe very rarely to that exted, sice the data depedecies usually wo t allow for such differeces i the executio order i differet ifpaths. Breakpoit itersectio ca oly happe i the local cotext of loops if these cotai a hierarchy of if-braches. There caot be a itersectio of breakpoits belogig to differet loops, sice all loop are scheduled idepedetly of each other. This greatly reduces the size of such itersected breakpoit clusters. The algorithm we use is hierarchically orgaized. A level of hierarchy is made up of all itersectig sets, excludig supersets, which belog to the ext higher level, ad subsets, which belog to the ext lower level. Ecodig starts at the highest of hierarchy. We defie Top as the set of all breakpoit sets, Top(S) as the set of all subsets of S. The set of clusters i the set S is C(S), where a cluster C S is give by: N C S M C S { N M N M N N M M} Iit: We set the workig set Curret = Top. Step 1: ( C Curret C( Curret) ): Assig a biary ecodig (the cluster ID). The followig sub-ecodigs of differet clusters are attached to the cluster ID ad ca share the same bit positios. Step 2: Withi each C Curret, all itersectig sets are assiged oe bit. This umber of bits is added to the cluster ID. Step 3: ( C Curret C( Curret) ) ( S C Curret ) : Set Curret = Top(S), ad go to Step 1. The result of this subecodig is attached to the ecodig achieved so far. For differet S, these share the same bit positios. I step 2, we eed the assumptios we made above about the itersectio of breakpoits. E.g. i a case like the oe give i figure 2, the ecodig accordig to step 2 is far away from beig optimal. Here we would eed 8 bits with our heuristic, while a ecodig with 4 bits is possible to fulfil the costraits metioed above. The umber of bits is give by the followig recursive formula: Bits( Top) = log CTop ( ) + max( C Top ) + max( Bits( S C Top )) Bits( ) = 0.

4 The worst case rutime of the algorithm is O(Bp 2 * CS), where Bp deotes the umber of possible differet breakpoits ad CS deotes the umber of cotroller states. This is a equal complexity to state of the art schedulig algorithms sice Bp is proportioal to the umber of operatios. I practice, the rutime is much less, sice there is o global itersectio of breakpoits, thus the algorithm always works locally Example for breakpoit ecodig The example i figure 3 shows a umber of itersectig breakpoits to which we apply our algorithm to clarify its operatio. Bp.1 Bp.2 Bp.7 Bp Bp.4 First, we idetify two clusters at the top level of hierarchy: C1: Bp. 1, 2, 3, 4, 5, 6 C2: Bp. 7, 8 The first bit of the ecodig is the '0' for C1 ad '1' for C2. The ext bits deped o the clusters ad may be shared for differet clusters. For C2 we get oe bit for Bp. 7 o the highest level ad if we go dow oe level, we get a additioal bit for Bp. 8. For cluster 1, we get 2 bits, oe for Bp.1 ad oe for Bp. 2 at the highest level. Goig dow oe level, we get aother 2 bit for Bp. 3 ad Bp. 4, which share the positios with the 2 bit for Bp. 5 ad Bp. 6. Thus, the ecodig of the states is accordig to table1. Bit 1 tells us the cluster, bit 2 idicates that a state belogs to Bp 1, if we are i cluster C1, or to Bp. 7, if we are i cluster C2. The meaig of the other bits is aalog to that. The ecodig eeds 5 bit, which is optimal by chace i this case. It caot be doe with less bits ad still satisfy the ecessary costraits. 3. Breakpoit detectio i the hardware 3.1. Breakpoit detectio logic 5 Bp Bp.68 9 Bp.8 10 Figure 3. Example for the ecodig algorithm State Ecodig Table 1. Example State ecodigs As metioed above, we ca detect breakpoits by comparig the ecoded cotroller state idetifier with a give breakpoit ID. Depedig o the breakpoit we are iterested i, we eed to igore certai bits of the idetifier. The idetifier is a sigal geerated by the cotroller. A example of the VHDL style of the geerated cotroller together with the breakpoit idetifier is show i figure 4. fsmlogic: process(curret_state, iput_list) begi default_assigmets; case curret_state is WHEN state1 => idetifier <= "01010"; output_assigmets; ext_state_assigmet; WHEN state2 => idetifier <= "01000"; output_assigmets; ext_state_assigmet;... ed case; ed process fsmlogic; Figure 4. Breakpoit IDs i the geerated VHDL cotroller It is a process with a case statemet, i which the outputs ad the ext state are computed accordig to the curret state. I each state, we geerate the correspodig idetifier for breakpoit detectio. The breakpoit detectio logic we eed to add to the geerated circuit is show i figure 5. We eed a register to write i the desired breakpoit ad a mask register, where we tell the comparator, which bits of the breakpoit idetifier ad the breakpoit register it should igore. The first bit of the breakpoit register tells the comparator to costatly output '0' if it is set, i.e. it represets the operatio with o breakpoit set. The comparator tests the ot masked bits of the breakpoit idetifier ad the breakpoit register for equality. If equal, the BP-reached sigal is raised to '1'. The BP-scai sigal represets a sca path for settig ad chagig breakpoits i circuit. Thus, we do ot eed to sythesize the

5 BP-ID (from cotroller) BP scai BP-ID reg. circuit each time we wat to set a ew breakpoit. All this is doe dyamically i the implemeted circuit. The detectio of data depedet breakpoits is also very similar to that. We just replace each register i the data path by a compoet which cotais a data register, a programmable register for breakpoit detectio ad a comparator Debuggig cotroller BP-comparator mask reg. BP reached Figure 5. Breapoit detectio logic The programmig of breakpoits ad the iterrupt of the circuit is doe by the debuggig cotroller. This compoet allows the host to cotrol the circuit operatio. A abstract scheme of its operatio is show i figure 6. Write to breakpoit or data path registers Ru circuit Commad Bp_reached or Iterrupt Step oe clock cycle Read data path registers Figure 6. Simplified diagram of dbg. cotroller The macro state commad is the iitial state of the cotroller. I this state it waits for a commad ad the circuit is iterrupted. As commads we ca have the followig: Write a breakpoit Write values to the data path registers Read the cotets of the data path registers Step oe clock cycle Ru the circuit clock outp Each commad is decoded, ad the cotroller switches to the correspodig macro state, which maages the required actio. I each macro state, the cotroller comes back to the commad state after the actio is fiished. Oly i ru_circuit state it remais util a breakpoit is reached or a iterrupt commad is issued by the host. Iterruptig the circuit is doe by settig a clock_cotrol sigal to '0', which the prevets the data path registers ad the circuit cotroller from operatio. Thus, the circuit halts. Each register i the data path is exchaged accordig to figure 7 by a register which allows for the required operatio cotrol. The iputs added to the origial data path register are used for programmig/readback of the register cotets via a sca path (sca_i, sca_e, sca_out), ad for eablig ormal data path operatio (clock_ctrl). These additioal iputs are maaged by the debuggig cotroller. The debuggig cotroller is ot applicatio depedet. We implemet it together with the applicatio o the FPGAs for reasos of simplicity, but it may also reside outside of the programmable logic. 4. Results load ip register sca_i sca_e clock_ctrl clock a) b) load ip register outp sca_out Figure 7. a) Origial ad b) for dbg iserted data path register The described techique is implemeted withi our sythesis tool amed CADDY [5][6][7]. All chages to the circuit cotroller ad to the data path are applied automatically durig the geeratio of the VHDL code by CADDY. There is o maual work by the user required for the geeratio of the debug model. The debuggig cotroller commuicates with a SUN workstatio via the parallel port. The applicatios listed below for the results were all real sythesized, dowloaded ad ru o our WEAVER [8] prototypig board. The followig applicatios were doe: GCD: A stadard example for high level sythesis. SIRDG: A circuit which computes "sigle image radom dot stereograms". It receives a source image with the height iformatio via a parallel iterface ad writes the geerated image to a host via a parallel iterface.

6 DCT: A circuit which computes a two-dimesioal 8x8-DCT. It is implemeted as a coprocessor for the Hyperstoe processor [9]. The commuicatio with the processor is doe via the exteral processor bus. I table 2, the area values of the differet circuits are listed. All values are give i CLBs for the Xilix XC4000 series. Please ote, that the costat overhead for the debuggig cotroller (ca. 44 CLBs) virtually ca be subtracted from the overhead umbers for the examples, because it is ot depedig upo the applicatio. It could easily be implemeted separately from the FPGAs. Circuit Orig. Dbg 1 Dbg 2 Mealy Moore GCD /84 141/ SIRDG / / DCT / / Table 2. Area values Orig. refers to the origial circuit without debug overhead. Dbg 1 icludes the overhead for debuggig without the possibility of data depedet breakpoits. It shows the value with/without debuggig cotroller. Dbg 2 represets the full versio with data depedet breakpoits. Mealy deotes the umber of bits eeded for the Mealy idetifiers, Moore deotes the umber of bits of the Moore idetifiers. The sum of Mealy ad Moore is added to the output of the circuit cotroller. #Bp deotes the umber of differet detectable breakpoits i the specificatio. #States lists the umber of cotroller states of the circuit cotroller. Table 3 shows the delay that is added by the additioal logic for debuggig. Circuit Orig. Dbg 1 Dbg 2 GCD 5.7 Mhz 4.7 Mhz 4.5 Mhz SIRDG 7.7 Mhz 4.8 Mhz 4.9 Mhz DCT 3.5 Mhz 3.5 Mhz 3.5 Mhz Table 3. Clock frequecies The values are obtaied by the Xilix tool 'xdelay'. This tool provides a quite pessimistic estimatio. All desigs ru at a sigificatly higher clock speed o our Weaver board. Nevertheless, it shows the relatio betwee the differet implemetatios. There is ot much differece betwee the two versios with debuggig overhead, sice the evaluatio of coditioal breakpoits does ot slow dow the circuit additioally. Our approach maily adds cotroller delay. Therefore we do ot add ay delay to the dct, which is maily determied by the combiatorial multiplier. To this path, we do o add ay delay. Therefore, the debug versios ca be clocked with equal frequecy. 5. Summary I this paper, we have preseted the details of how we hadle breakpoits i our ew SLE approach. We have discussed, how we ca relate breakpoits set i a algorithmic specificatio to a implemeted circuit. We have show, how we ecode the breakpoits ad how we detect them by hardware meas. We have demostrated the applicability of our approach by a set of implemeted circuits. 6. Refereces [1] Y. Taurha, S. Schmerler, K. Mueller-Glaser, A Backplae Approach for Cosimulatio i High-Level System Specificatio Eviromets, Europea Desig Automatio Coferece EURODAC 95, Brighto, 1995 [2] J. Soiie, T. Huttue, K. Tiesyrjae, H. Heusala, Cosimulatio of Real-Time Cotrol Systems, Europea Desig Automatio Coferece EURODAC 95, Brighto, 1995 [3] H. Owe, U. Kah, J. Hughes, FPGA based ASIC Hardware Emulator Architectures, School of Electrical ad Computer Egieerig, Georgia Istitute of Techology, 1993 [4] ASIC-Emulatio auf RTL-Level, Markt&Techik - Wochezeitug für Elektroik Nr. 42, 1994 [5] R. Camposao, W. Rosestiel, Sythesizig Circuits from Behavioral Descriptios, IEEE Trasactios o CAD, Vol. 8, [6] P. Gutberlet, J. Müller, H. Krämer, W. Rosestiel, Automatic Module Allocatio i High Level Sythesis, Europea Desig Automatio Coferece EURODAC 92, Hamburg, 1992 [7] P. Gutberlet, W. Rosestiel, Schedulig Betwee Basic Blocks i the CADDY Sythesis System, Europea Coferece o Desig Automatio EDAC 92, Brussels, 1992 [8] G. Koch, U. Kebschull, W. Rosestiel, A Prototypig Architecture for Hardware/Software Codesig i the COBRA Project, Proceedigs of 3rd iteratioal Workshop o Hardware/Software Codesig Codes/CASHE 94, Greoble 1994 [9] Hyperstoe electroics, Hyperstoe E1 32-Bit-Microprocessor User s Maual, 1990 [10] G. Koch, U. Kebschull, W. Rosestiel, Debuggig of Behavioral VHDL Specificatios by Source Level Emulatio, Europea Desig Automatio Coferece EURO- DAC 95, Brighto, 1995