NCSA Reconfigurable Systems Summer Institute July, Michael Babst DSPlogic, Inc x705. DSPlogic Proprietary

Transcription

1 Reconfigurable Practical Reconfigurable Computing Computing Made Easy! Today NCSA Reconfigurable Systems Summer Institute July, 2005 Michael Babst DSPlogic, Inc x705 DSPlogic Proprietary

2 Typical Design flow (the old way) Benchmark performance, profile execution, I/O Partition Algorithm Define CPU/FPGA messaging scheme Learn VHDL or Verilog Design FPGA Code Application I/O (interface w/ custom vendor cores) Verify I/O - Synthesize/Place/Route FPGA Optimize I/O for BW/latency Code Application Core (verify) Synthesize/Place/Route FPGA (App+I/O) Fiddle with I/O, Application until FPGA builds Verify APP+I/O - Synthesize/Place/Route FPGA Done! Make a small change to the application Become an Expert in VHDL/Verilog, HW design, timing diagrams Redesign I/O, Modularize design, Isolate I/O from application Optimize speed and timing Working design!

3 Typical Design flow (the old way) Here comes the Virtex 4! Re-partition Algorithm Redesign I/O Get the idea? RC can be a challenge, even for a hardware designer

4 Practical Reconfigurable Computing Customers #1 Requirement in selecting (or not selecting) an RC platform Usability of Tools Currently available methods High-level C programming Mitrion-C, System-C, Handel-C Hard-core HDL VHDL, Verilog Model-based / Dataflow Design Viva, Simulink Customers need a solution that 1) works today 2) is easy to use.

5 Agenda Rapid RC Development Kit Reconfigurable Computing (RCIO) API RCIO API Implementation RCIO FPGA Core / SW Library Cray XD1 Platform Application Examples FFT Point Projection Floating point Multiply/add/subtract

6 Rapid RC Development Kit DSPlogic Proprietary

7 DSPlogic Rapid RC Development Kit Key Development Kit Components RCIO Software Library RCIO API Implementation, platform optimized RCIO FPGA Core RCIO Core Implementation, platform optimized Matlab/Simulink Interface DSPlogic RC Blockset for Matlab/Simulink RCIO FPGA Builder Automated FPGA implementation, platform optimized Reliable one-click build process Xilinx System Generator Application Example

8 Rapid RC Development Kit Design Flow Algorithm Matlab/Simulink Rapid implementation Simplified CPU/FPGA messaging CPU/FPGA Partition, Specify Dataflow Simulink Low-overhead Bandwidth or latency optimization Implement Algorithm Call RCIO API Functions DSPlogic RC Blockset Familiar, industry standard modeling environment Design Data Processor Verify Data Processor Output DSPlogic RCIO FPGA Builder Stream or block processing Common API Portable, reusable upgradeable code Optimized core libraries Efficient resource utilization Integrated algorithm verification Processor Fully Integrated, Verified, Seamless Application RCIO API Transparent interface Integrated bitstream generation Simplified high-speed design Maximum processing and I/O throughput Floating-point capability

9 Model-based FPGA Design Advantages VHDL not required (but possible) Integrated algorithm verification Industry standard, familiar environment Easy integration of IP cores Clear view of algorithm architecture Optimized core libraries Highly efficient use of FPGA resources Ease of FPGA design verification Automatic design documentation Integrated bitstream generation Compatible with high-level languages HLL Behavioral descriptions possible

10 DSPlogic/Xilinx System Generator Integrated Environment Direct Algorithm To Platform FPGA! FPGA

11 Reconfigurable Computing I/O (RCIO) API DSPlogic Proprietary

12 Reconfigurable Computing I/O API A Simple, future-proof CPU/FPGA messaging interface Transparent portable interface Dramatically reduces FPGA development time RCIO Library and FPGA Core User FPGA Application Quickly achieve optimum latency and bandwidth Crucial to performance User Software Application rcio_send() rcio_receive() rcio_appcfg() rcio_appstat() Input Data Bus Output Data Bus Control Registers Status Registers Application portability, reusability and upgradeability Future-proof: easy migration to newer, higher-performance FPGAs Separate data and control message paths RAM Interface Low-overhead Block and Stream Processing Platform RAM Multiple CPU/FPGA support

13 Reconfigurable Computing I/O API Multiple processor / multiple FPGA support CPU #1 CPU #2 CPU #N User Application RCIO SW library User Application RCIO SW library MPI, PVM, etc User Application RCIO SW library Platform Specific Connection Fabric Transparent, Portable Application Interface! RCIO FPGA Core User Application FPGA #1 RCIO FPGA Core User Application FPGA #2 RCIO FPGA Core User Application FPGA #K

14 Data Message Structure (64-bit) Dataset Message MSG 0 BLK 0 User-definable format BLK 1 Data Block real32 real32 MSG 1 word 0 [63:0] word 1 [63:0] int16 int16 real64 int16 int16 custom BLK B-1 MSG M-1 M Messages B Blocks word K-1 [63:0] K words I/O often limits performance - Use care with CPU/FPGA algorithm partitioning - Consider smaller data types Easily group processing blocks into messages for optimal I/O bandwidth

15 Software API - Data Interface rcio_send() Send single message to FPGA rcio_receive() Receive single message from FPGA rcio_stream() Blocking function Break dataset into messages Send all messages to FPGA Receive all result messages from FPGA Bandwidth-optimized

16 Software API - Control Interface Messaging control functions rcio_config() Initialize / configure CPU/FPGA communications link rcio_status() Return status of communications link rcio_close() fpgastatus nmsgreceived,nmsgreturned Fifo levels / over/underflow Close CPU/FPGA communications link User application control and status commands rcio_appcfg() Write to user-definable application control register rcio_appstat() Read user-definable application control register

17 RCIO Hardware Abstraction Layer (HAL) API DSPlogic RCIO Core User FPGA Application in_ready Input Data Message FIFO Output Data Messag FIFO in_data in_write in_start in_length out_ready out_data out_write out_start Data Processor Platform Specific RAM / Peripherals out_length Control I/O ctrl_reg(0-7) stat_reg(0-7) ib_depth, ob_depth clk rst

18 RCIO Hardware Abstraction Layer (HAL) API FPGA design tool-independent Supports wrappers in all design environments High-level design tools Xilinx System Generator, etc. Custom VHDL / Verilog High-level C Mitrion-C System C, Handel-C, System Verilog, etc.

19 RCIO FPGA Core / SW Library Implementation for the Cray XD1 Supercomputer DSPlogic Proprietary

20 Seamless Cray XD1 CPU-FPGA Messaging Application Memory Processor DSPlogic RCIO SW Library rcio_send(fpga_id, *datap, txmsglen) RAP Directly Link CPU and FPGA Applications! Total Hardware Abstraction! DSPlogic RCIO FPGA Core ready data write start length Application Processing FPGA

21 RCIO FPGA core and SW Library Cray XD1 Opteron Application Accelerator User CPU Application User Data Memory Control DSPlogic RCIO Library Cray AA API Result Buffer (2 MB) 1.42 GB/s (Max) 1.1 GB/s (Typ) RAP 1.42 GB/s (Max) 1.1 GB/s (Typ) Cray RT Core DSPlogic RCIO Core Input Data FIFO Output Data FIFO Control User FPGA Application Process Data Control Cray QDRII Core 8 MB RAM Transparent interface

22 Cray XD1 Performance Demonstrated performance and usability on multiple applications in multiple design environments Extremely Modular - Multiple applications at full speed (200 MHz) Fastest CPU/FPGA Interface Available for the Cray XD1! Combined (Send/Recv) Throughput (Symmetric Send/Recv rates) Achievable Data Rates (Mbytes/sec) (Including dataset sizes > 2 MB) Send Rcv Total 1400 Theoretical Max (not achievable) Typical Send Only Application N/A MBytes/sec Typical Receive Only Application Typical Send/ Receive Application DSPlogic RCIO Send/Receive * N/A < < > Message Length (64-bit words) * Using rcio_stream() Applications immediately benefit from API enhancements

23 Application Examples -FFT -VHDL-based design flow DSPlogic Proprietary

24 FFT Accelerator FFT Length: 32 to Fixed-point, full-precision Complex FFT VHDL design flow Device Utilization 14k Slices (60% V2P50) 186 Block Rams (80% V2P50) Software API Include RCIO API Additional application specific library functions fft_init(fft length, direction) FFT Usage rcio_config() fft_init() rcio_stream() rcio_close()

25 FFT Performance Improvement ~10x improvement possible today! Complex FFT, FPGA vs. FFTW on AMD 246 Performance depends on data types Im 1 (15:0) Re 1 (15:0) Im 0 [15:0] Re 0 [15:0] in unused Re 0 (15:0) unused Re 0 [15:0] Im 1 (15:0) Re 1 (15:0) Im 0 [15:0] Re 0 [15:0] out Im[31:0] Re[31:0] Additional speed at expense of considering scaling / dynamic range effects Accuracy similar to single-precision floating point algorithms R=1.4G R=1.1G R=800M R=1.4G R=1.1G R=800M T(fftw)/T(fpga) T(fftw)/T(fpga) Nfft Nfft

26 FFT Summary Performance is I/O constrained > 10x speed gains are achievable today FPGA Performance enhancement increases with FFT length Multiple FFTs utilize pipeline and provide efficiency FFT L2norm accuracy ~10-5, similar to other single-precision algorithms Modular architecture Separate I/O and application optimization Rapid application development Message latency limits speed improvement for single computations of small FFT sizes

27 Application Examples -Dirt Code - Point Projection -Model-based design example DSPlogic Proprietary

28 Original Code struct s_point pointprojection(struct s_plane plane, struct s_point p1) { // // Get the projection of point p1 on the plane // v = p1 - plane.p; result = v - (v*plane.n)plane.n + plane.p // double temp; struct s_point vec1, proj; // // Get the vector (vec1) from a point in the plane to p1 // vec1.x = p1.x-plane.p.x; vec1.y = p1.y-plane.p.y; vec1.z = p1.z-plane.p.z; // // temp = vec1 dot plane.n // temp = plane.n.x*vec1.x + plane.n.y*vec1.y + plane.n.z*vec1.z; // // Get the global coordinates for p1's projection // proj.x = vec1.x - temp*plane.n.x + plane.p.x; proj.y = vec1.y - temp*plane.n.y + plane.p.y; proj.z = vec1.z - temp*plane.n.z + plane.p.z; return proj; } Courtesy David Raila / Youssef Hashash

29 Original Code struct s_point pointprojection(struct s_plane plane, struct s_point p1) plane.p p1 plane.n vec1.x = p1.x-plane.p.x; vec1.y = p1.y-plane.p.y; vec1.z = p1.z-plane.p.z; delay vec1 delay temp = plane.n.x*vec1.x + plane.n.y*vec1.y + plane.n.z*vec1.z; proj.x = vec1.x - temp*plane.n.x + plane.p.x; proj.y = vec1.y - temp*plane.n.y + plane.p.y; proj.z = vec1.z - temp*plane.n.z + plane.p.z; delay delay delay delay delay dot temp delay } return proj; proj

30 Message Formats Input Format Output Format Block 64-bit offset in_data[63:0] 0 pt[0].x 1 pt[0].y 2 pt[0].z 3 plane_n[0].x 4 plane_n[0].y 5 plane_n[0].z 6 plane_p[0].x 7 plane_p[0].y 8 plane_p[0].z 9 pt[1].x 10 pt[1].y 11 pt[1].z 12 plane_n[1].x 13 plane_n[1].y 14 plane_n[1].z 15 plane_p[1].x 16 plane_p[1].y 17 plane_p[1].z : : : : : : : : : pt[p-1].x pt[p-1].y pt[p-1].z Block 0 Block 1 Block P-1 plane_n[p-1].x plane_n[p-1].y plane_n[p-1].z plane_p[p-1].x plane_p[p-1].y 9P-1 plane_p[p-1].z Block 64-bit offset out_data[63:0] 0 proj[0].x Block 0 1 proj[0].y 2 proj[0].z 3 proj[1].x Block 1 4 proj[1].y 5 proj[1].z : : : : : : : Block P-1 : : proj[p-1].x proj[p-1].y 3P-1 proj[p-1].z Number of Projections/Message P = 64*k, 6 <=k <= 113 Theoretical Max possible projections / second I/O limited No Packing ~ 200 MHz/9 = 22.2 M projections/sec With Packing ~ 200 MHz/3 = 66.6 M projections/sec

31 Data Format / Precision Data Width Use 64-bit for future flexibility Tradeoff data packing vs. software/firmware rework Input Data din[15:0] Output Data dout[63:0] Precision Input: 16-bit signed integer Output: 52-bit signed integer (sign-extended to 64-bits)

32 Point Projection High-level Diagram DSPlogic Rapid Reconfigurable Computing Development Kit Point Projection Demonstration in_data in_write in_start in_length_m1 sfix64 double double uint16 out_data_s sfix64 in_data in_write in_start out_data testbench_source uint16 blkspermessage uint16 out_length_m1 userparameters 1 boolean double in_data_s in_write_s in_start_s in_length_m1_s out_ready _s rst_s out_write_s out_start_s out_length_m1_s in_ready _s double double double double out_write out_start out_length_m1 in_ready testbench_verify ib_depth_s dp_stat_reg_0_s uf ix64 dp_stat_reg_0 DSPlogic RCIO FPGA Builder ob_depth_s dp_ctrl_reg_0_s dp_stat_reg_1_s uf ix64 dp_stat_reg_1 dp_ctrl_reg_1_s dp_stat_reg_2_s uf ix64 dp_stat_reg_2 Sy stem Generator dp_ctrl_reg_2_s dp_ctrl_reg_3_s dp_ctrl_reg_4_s dp_stat_reg_3_s dp_stat_reg_4_s uf ix64 uf ix64 dp_stat_reg_3 dp_stat_reg_4 Copyright 2005 DSPlogic, Inc All Rights Reserved Double-click for more info 0 uf ix64 dp_ctrl_reg_5_s dp_ctrl_reg_6_s dp_ctrl_reg_7_s dp_stat_reg_5_s dp_stat_reg_6_s uf ix64 uf ix64 dp_stat_reg_5 dp_stat_reg_6 DSPlogic Proprietary core dp_stat_reg_7_s uf ix64 dp_stat_reg_7

33 Point Projection Core Unit: projection Fix_16_0 1 plane_n_x Fix_16_0 2 plane_n_y Fix_16_0 3 plane_n_z in_x in_y in_z delay1 out_x out_y out_z Fix_16_0 Fix_16_0 Fix_16_0 plane_n_x plane_n_y temp_x_planen_x Fix_51_0 temp = plane.n.x*vec1.x + plane.n.y*vec1.y + plane.n.z*vec1.z; plane_n_z Fix_16_0 4 p1_x Fix_16_0 5 p1_y Fix_16_0 6 p1_z Fix_16_0 7 plane_p_x Fix_16_0 8 plane_p_y Fix_16_0 9 plane_p_z p1_x p1_y p1_z plane_p_x plane_p_y plane_p_z getvec v1_x v 1_y v 1_z Fix_17_0 Fix_17_0 Fix_17_0 v 1_x v 1_y v 1_z temp_x_planen_y temp_x_planen_z v1_dot_plane_n Fix_51_0 Fix_51_0 temp_x_planen_x temp_x_planen_y temp_x_planen_z proj_x Fix_64_0 1 proj_x vec1.x = p1.x-plane.p.x; vec1.y = p1.y-plane.p.y; vec1.z = p1.z-plane.p.z; in_x in_y in_z out_x out_y out_z Fix_17_0 Fix_17_0 Fix_17_0 v1_x v1_y v1_z proj_y Fix_64_0 2 proj_y delay3 plane_p_x in_x in_y out_x out_y Fix_16_0 Fix_16_0 in_x in_y out_x out_y Fix_16_0 Fix_16_0 plane_p_y plane_p_z proj_z Fix_64_0 3 proj_z Fix_16_0 Fix_16_0 in_z out_z in_z out_z proj delay2 delay4 Stage1Delay=2 Stage2Delay=12 Stage3Delay=6 proj.x = vec1.x - temp*plane.n.x + plane.p.x; proj.y = vec1.y - temp*plane.n.y + plane.p.y; proj.z = vec1.z - temp*plane.n.z + plane.p.z; Bool 10 in_en z -2 Bool z -12 Bool z -6 Bool 4 out_en 11 Bool z -2 Bool z -12 Bool z -6 Bool in_start 5 out_start

34 Performance results Computation Rate (conservative) Input data type precision Millions of Projections/s Message Size (64-bit words) ~10-5 Computation Accuracy Full-precision L2Norm Error = 0 4x additional speed improvement (60M projections/sec) with data packing Next steps Move more functionality into FPGA Partition algorithm for lower I/O bandwidth

35 Summary Rapid RC Development Kit A practical design method available today Reconfigurable Computing (RCIO) API Offers many benefits, including portability RCIO API Implementation Cray XD1 Platform fastest FPGA/CPU interface available Additional platforms coming Application Examples FFT Point Projection Floating point multiply/add/subtract Future Hardware co-simulation CPU/FPGA I/O Standardization RCIO API enhancements High-level language integration

36 Contact Information Michael Babst x705