MANUAL XILINX ISE PROJECT NAVIGATOR

Transcription

1 Hochschule für Angewandte Wissenschaften Hamburg University of Applied Sciences Department of Electrical Engineering and Computer Sciences MANUAL XILINX ISE PROJECT NAVIGATOR AND MODELSIM Design Flow for CPLD and FPGA Implementations 1. Xilinx ISE: Project Configuration 1.1 Start ISE Project Navigator with click on this desktop icon: ISE Project Navigator PAL, VOL 03, SWR 04 1

2 1.2 ISE Project Configuration With click on File New Project... this new project window appears: Project : Project location and name, HDL design entry New At first choose the location D:\ISEwork then edit the project name. The subfolder s name is attached automatically in the field Project Location. A my_first.npl project file will be created. Select HDL for the top-level module type as shown above. For choices click onto this field and a list of choices appears. Now proceed with Weiter and a window for a project configuration is available. New Project : Device and design flow selection for CPLD hardware. For a CPLD design choose the device options and the HDL design flow as above in the value column. 2

3 For a Spartan FPGA design choose the depicted entries to the value column: Project : Device and design flow selection for Spartan FPGA hardware. New Proceed with the Weiter button and follow with Weiter again when the New Project Create a New Source window is available. 1.3 Add a Copy of Source File from Disk to an ISE Project The empty New Project Add Existing Sources window is opened. Now three steps have to be performed. New Project : Add existing sources, choose source type. Click on Add Source and search for your VHDL file(s) <entity_name>.vhd within the opened folders window. A 3.5 disk drive and a USB(-stick) mass storage is available on the PCs in lab room 801. Select Öffnen and then the Choose Source type window presents a choice. Select VHDL Design File from the Choose Source Type window. After given a click on OK the selected VHDL file is entered to the first row in the New Project Add Existing Sources window. Finally the user constraints file *.ucf can be added with the same procedure beginning with Add Source. 3

4 With a click on Weiter the New Project Information window presents a summary of all edited project details. The configuration sequence is finished with a click on Fertigstellen. The Project Navigator window will be opened. Reduce the Project Navigator window size. 2.MODELSIM : FUNCTIONAL SIMULATION 2.1 Start the Program ModelSim Click on the desktop icon as seen right: Close the window ModelSim Xilinx Version if it appears. If the Welcome window appears activate Do not show... and click on: Proceed to ModelSim. All further actions are started in the console window: ModelSim XE II/Starter xxx Custom Xilinx Version. ModelSim 4

5 2.2 Create New Project ( in ModelSim!) Choose File New Project, fill in Project Name i.e. SEG7_TEST and browse for the shown Project Location i.e. D:/ISEwork/my_first.as seen right. The Default Library Name must be work. A ModelSim Project File SEG7_test.mpf and a folder work will be created. No files should be added to this folder by the user. If you use ModelSim without ISE it is necessary to type in a new project folder instead of browsing: D:\ISEwork\<projectname> With a click on OK the Add Items to the Project window gets invoked. 2.3 Add VHDL-File to Project Select the Add existing File Icon from the Add Items to the Project window. The dialog Add file to Project appears: Browse to your project folder D:\ISEwork\My_first. Select your VHDL files and click Open. The added source file will be listed in the left column of the console window according to the tab Project Make sure that Reference from current location is selected before you finish with OK. Close the Add Items to the Project window. If you use Modelsim without ISE it is necessary to copy your source files from disk ( *.vhd) into your just created project folder. 5

6 2.4 Compiling the Source File Right click on the selected VHDL file Click on Compile Compile Properties Activate the following options in the Project Compiler Settings window with tab VHDL: Use 1993 Language Syntax Use explicit declarations only Show source lines with errors Check for: Synthesis Report Warnings On: all Vital Compliance Optimize for: StdLogic 1164 Vital Click on OK to leave the Project Compiler Settings window. Compilation of the selected file: Click on Compile Compile Selected Compilation success is reported in the right hand side of the console window with green letters. In case of errors and warnings the report is given with red letters. Click on the red report line and an additional window presents a detailed report about the code lines with errors and about the error type. Clicking on a line with an error description will open the source file with the related code line yellow highlighted. Correct the error, save file and Compile again. Do so until source file is free of errors. 2.5 Load Design Click on Simulate Simulate Options. Enter following options: Default Radix: Hexadecimal Default Run: 100 ns Default force type: Freeze Terminate with Apply and OK. Click on Simulate Simulate Choose the Design tab in the window Simulate. Open the work folder with a click on + and select the entity name. Then click on OK. Loading reports will be listed in the console window. 2.6 Simulation-Execute Macro ( command file *.do) Copy your *.do files from disk into the project folder: File Add to Project Existing File Browse to your disk drive, set file type to All types of file; select the appropriate *.do file and terminate with Open. Set to Copy to Project Directory and finish with OK. Click on Tools Execute Macro, choose your *.do file. Use the button Restart in the appearing Restart window. Keep all other selections active. 6

7 3. Xilinx ISE: Synthesis +Implementation 3.1 Synthesize Source File in Xilinx Project Navigator Double click the VHDL file in window Sources in Project. The <entity-name>.vhd file will be shown in an editor window. Start synthesis with double click on Synthesize-XST in window Processes for Source. Then have a look at the Synthesis Report with the double click on View Synthesis Report. 3.2 Implement Design Invoke the implementation by double click on Fit. For CPLD designs have a look at the Fitter Report. The generated equations and the pinout of the device can be checked. For FPGA designs click on Implement Design and have a look at the Place and Route Report and the Pad Report Viewing the Timing Report For CPLD designs click on Timing Report For FPGA designs click on Text-based Post Place & Route Static Timing Report or/and Analyze Post-Place & Route Static Timing (Timing Analyser) provides details about the longest delay paths Generate Post-Fit Timing Model for ModelSim For CPLD designs click on Generate Post-Fit Simulation Model For FPGA designs click on Generate Post Place & Route Simulation Model The files <entity-name>_timesim.vhd (structural VHDL model with back annotation) and <entity-name>_timesim.sdf (Vital standard delay format) are generated. CPLD Design FPGA Design 7

8 4. MODELSIM: TIMING SIMULATION Post-Fit Timing Simulation of CPLD Designs. If ModelSim is not yet active start it again from desktop icon. The <entity-name>_timesim.vhd file has to be included to the project (my_first). Click on: File Add to Project Existing File The steps explained in chapter 2.3 have to be performed within the Add File to Project window. Before compilation can be started the compiler settings need to be modified according to chapter 2.4: The Check for: Synthesis has to be deselected. The compilation procedure is the same as described in chapter 2.4. To load the compiled back annotation model the Simulate window has to be opened: Simulate Simulate Select at first the SDF tab and select Add and Browse in order to search for the *.sdf file: <entity-name>_timesim.sdf. No entries to the field Apply to Region. Then select the Design tab and open the work folder with a click on + and select the implemented entity name. Then click on OK. Loading reports will be listed in the console window with a report about correct assignment of the sdf-backannotation. Execute the same *.do file as in the functional simulation: Tools Execute Macro. Remove all references to internal signals from the *.do file! 5. Xilinx ISE: Generation Output File 5.1 Generating a Programming File *.svf for CPLD designs During the first step a <entity_name.jed> file is generated by invoking Generate Programming File. The second step provides the final programming file format *.svf filled with the original <entity_name>.jed file. Double click on the last line in the Processes for Source window: Generate SVF/XSVF/STAPL File Choose the Boundary-Scan file option which is offered by the Prepare Configuration Files window. The next step is to select the SVF-File option which is offered with a second Prepare Configuration Files window. Close the last window with Fertigstellen. As a result the Create a New SVF File window is available. A file name has to be edited and stored: <entity_name>.svf Within the new Add Device window the <entity-name>.jed file has to be chosen which has been generated during the first step. This file is assigned to the selected CPLD device which is depicted with the File GenerationMode impact window. Now it is necessary to click on the device on the screen so it will be marked in green. Click on Operations Program. The menu is left only with activated Erase Before Programming. Click OK. Finally a <entity_name.svf> file with a size >> 500 kb is contained in the project folder. 5.2 Generating a Programing File *.bit for FPGA designs 8

9 In Xilinx Project Navigator double click on Generate Programming File. A <entity_name.bit> file will be generated. 6. Download the Programming Files to XS* Boards Start the program GXSLoad with the desktop icon. Click on the desktop icon as seen on the right: Following menu has to be accomplished with the gxsload window. At first choose the board type: For CPLD: XS For Spartan FPGA: XSA-50 Set the correct LPT port number. Then open the explorer and pull with drag and drop the programming *.svf file into the field FPGA/CPLD. Finally click on Load. GXSLoad FPGA-Programming is done in two steps: 1. Drag and drop the dwnldpar.svf file from D:\ISEwork Load. 2. Drag and drop the <entity_name.bit> file from D:\ISEwork\project_name Load. X S G 7. Set Input Signals by the PC via LPT The pin names in the constraints file *.ucf must have been assigned to specific pins which are connected to the LPT3 interface to be set to a H or L level. Check the pinout for the target board! Use the gxsport window: 1. Activate port LPT3. 2. Set the level on the D0 to D 5 buttons. A click changes the level. 3. Click on the button Strobe in order to enable the values. Attention: D7 and D6 cannot be used! GXSPort 8. Usage of Constraints file *.ucf Use the *.ucf file in order to assign the entity port list signals to the pins of the device. Edit a *.ucf file with notepad and save it as <entity_name>.ucf. The option all files prevents the extension.txt to be added automatically. Example line : net seg<0> loc = p67; # comment net reset loc = p33; Appendix: Macro File example.do provides stimulus inputs to simulation 9

10 # Model-Sim Macro-Datei # Comment lines begin with '#' # # All time values for simulation step width have to be written # with a number and the unit nanoseconds i.e: 200ns!!! # # Automatic loading of a compiled design, not for timing simulation #vsim work.<filename> # Start a new simulation restart # windows to be opened: #view structure view signals #view variables view wave view process # Default Radix, important for hex-inputs by console radix hex # Displays all signals in waves window: # add wave sim:/<entity_name>/* add wave -height 30 -radix default sim:/seg7/* # 1. Example: discrete assigning of values # step by step labels the absolute time # Don t forget to apply appropriate time-units force a 1 run 100ns force a 2 run 100ns force a # Assignment according to the absolute timescale force a force a run 200ns #... # 2. Example: periodic assignment of signals # truth table style with the -r(epeat) period -switch: # 4 assignments provide a sequence of low and high levels, # the value of the period is given right from the -r switch. # value time, value time (after the actual time value) force a(0) 0 0, 1 50ns -r 100ns force a(1) 0 0, 1 100ns -r 200ns force a(2) 0 0, 1 200ns -r 400ns force a(3) 0 0, 1 400ns -r 800ns # single signal assignment: force a 0 run 1800ns 10