Final Exam Review. EE 3610 Digital Systems

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1 EE 3610: Digital Systems 1 Final Exam Review

2 2 Combinational and Sequential Logic: short answers

3 Combinational and Sequential Logic Timing: clock, hold time, setup time etc 3 Fast Carry Adder/Subtractor State machine in VHDL CPLDs and FPGAs VHDL Coding: Fundamentals Given a code, find errors

4 4 Floating Point Representation

5 Why Floating Point? Floating point numbers are used to represent fractions and allow more precision e.g , , Arithmetic units for floating-point numbers are more complex than fixed-point numbers IEEE 754 Floating-Point Formats Single precision (32-bit) Double precision (64-bit) Extended precision (128-bit)

6 Basics: Sign Field 6 N= (-1) S x (1 + F) x 2 E S = Sign field E = Exponent field F = Mantissa (Fractional) Field x 2 5 Sign field is 1-bit long: 0 (positive) or 1 (negative) 0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx

7 Basics: Exponent Field x Exponent field is 8-bits long: range 0 to 255 Add 127 to the exponent in scientific notation Here = 132: (If the exponent is less than 127 then it is negative) xxxx xxxx xxxx xxxx xxxx xxx

8 Basics: Mantissa (Fraction) Field x Mantissa field is 23-bits long: throw away 1 to the left of binary point and pad it with zeros at the end

9 Single Precision Representation x Sign Exponent Fraction

10 Single Precision Formats: Single Precision 10 Example: : : x 2 3 (Note: 0.45 produces repeating binary fractions) Sign: positive: 0 Exponent: = 130: Mantissa (Fraction): :

11 Double Precision Formats: Double Precision 11 Example: : x 2 3 (Note: 0.45 produces repeating binary fractions) Sign: positive: 0 Exponent: = 1026: Mantissa (Fraction):

12 Application of Floating Point DSP ADSP SHARC: most computationally intensive, real-time signal-processing applications Examples: High Definition Audio, Precision Motor/Tool Control, Precision Sensors 12 ADI SHARC DSP

13 EE 3610: Digital Systems 13 VHDL Functions

14 Functions: example 1 14 function Parity (a: std_logic_vector) return std_logic is variable b:std_logic:='0'; begin for i in a'low(1) to a'high(1) loop b:= b xor a(i); end loop; return b; --b is set to 1 if number of bits is odd otherwise 0 if even end parity; VHDL Predefined Attributes:

15 Functions: example 2 15 function bit_count (a: std_logic_vector(3 downto 0)) return integer is variable count:std_logic:='0'; begin for i in 0 to 3 loop if a(i)='1'then count:= count+1; end if; end loop; return count; end bit_count;

16 EE 3610: Digital Systems 16 VHDL Procedures

17 Procedures: example 1 17 procedure parity2 (a:in std_logic_vector;signal p:out std_logic) is variable b:std_logic:='0'; begin for i in a'range loop b:= b xor a(i); end loop; p <= b; end parity2;

18 Procedures: example 3 library ieee; use ieee.std_logic_1164.all; package my_reg8 is subtype byte8 is std_logic_vector(7 downto 0); type iarr is array(integer range 0 to 3) of integer; constant CLEAR8: byte8 := (others=>'0'); procedure dff8 (signal takt: in std_logic; signal D: in byte8; signal Q: out byte8); end my_reg8; package body my_reg8 is procedure dff8 (signal takt: in std_logic; signal D: in byte8; signal Q: out byte8)is begin if rising_edge(takt) then Q <= not D; end if; end dff8; end my_reg8; 18

19 Procedures: example 3 (continued...) library ieee; use ieee.std_logic_1164.all; use work.my_reg8.all; entity mydff is port (clk : in STD_LOGIC; datain: in std_logic_vector(7 downto 0); dataout : out std_logic_vector(7 downto 0)); end mydff; architecture behav of mydff is signal fromdip: byte8; signal toled: std_logic_vector(7 downto 0); signal arrtest: iarr; begin reg: process(clk) begin if(clk='1' and clk'event) then fromdip <=datain; dff8(clk,fromdip,toled); dataout<=toled; end if; end process; end behav; 19

20 EE 3610: Digital Systems 20 Attributes

21 Attributes: Example type example is array (0 to 255, 7 downto 0) of integer; 21 Useful for for loops example'left(1) would be 0 example'left(2) would be 0 example'right(1)would be 255 example'range(1) would be 0 to 255 example'range(2) would be 7 downto 0 example'length(1) would be 256

22 Attributes: Simulation Only 22 T'LEFT is the leftmost value of type T. (Largest if downto) T'RIGHT is the rightmost value of type T. (Smallest if downto) A'LEFT(N) is the leftmost subscript of dimension N of array A. A'RIGHT(N) is the rightmost subscript of dimension N of array A. A'HIGH is the highest subscript of array A or constrained array type. A'HIGH(N) is the highest subscript of dimension N of array A. A'LOW is the lowest subscript of array A or constrained array type. A'LOW(N) is the lowest subscript of dimension N of array A. A'RANGE is the range A'LEFT to A'RIGHT or A'LEFT downto A'RIGHT. A'RANGE(N) is the range of dimension N of A. A'LENGTH is the integer value of the number of elements in array A. A'LENGTH(N) is the number of elements of dimension N of array A. S'EVENT is true if signal S has had an event this simulation cycle. S'ACTIVE is true if signal S is active during current simulation cycle. S'LAST_VALUE is the previous value of signal S. VHDL Predefined Attributes:

23 EE 3610: Digital Systems 23 MIPS: Microprocessor without Interlocked Pipeline Stages

24 CPU DESIGN Heart of CPUs: Register File and ALU (Arithmatic and Logic Unit) 24 A 1 A 2 A 3 D 3 D 1 D 2 A L U op

25 R Instructions R-Format (32-bits): ALU Instructions 25 0 R S R T R d Shift F_Code Source Registers Destination Register Shift Amount

26 I Instructions I-Format (32-bits): Load/Store, Immediate ALU, Branch 26 op code R S R T C (sign extended) opcode Source Registers offset/immediate

27 J-Format (32-bits long) JUMP Instructions 27 op code Jump Address opcode offset word: 32 bits byte: 8-bits

28 Instructions Encoding 28

29 MIPS: example program Write MIPS Assembly Language Program for the following task: 29 for i= 1, 100, i++ y(i) = x(i) + y(i) ; repeat 100 times ; add each element of the arrays and store it in y Assume that x and y start at locations and Answer: andi $3,$3, 0 ;intialize loop counter $3 to 0 andi $2, $2, 0 ; clear register for loop end addi $2, $2, 100 ; loop end $label: lw $15, 4000($3) ;load x(i) to R15 lw $14, 8000($3) ;load y(i) to R14 add $24, $15, $14 ;x(i) + y(i) sw $24, 8000 ($3) ;save new y(i) addi $3, $3, 4 ;update address reg, addr=addr+4 bne $3,$2,$label ;check it the loop counter=loop end

MIPS: example program Write MIPS Machine Code given the following assembly program: 30 andi $3,$3, 0 ;intialize loop counter $3 to 0 andi $2, $2, 0 ; clear register for loop end addi $2, $2, 100 ;

30 MIPS: example program Write MIPS Machine Code given the following assembly program: 30 andi $3,$3, 0 ;intialize loop counter $3 to 0 andi $2, $2, 0 ; clear register for loop end addi $2, $2, 100 ; loop end $label: lw $15, 4000($3) ;load x(i) to R15 lw $14, 8000($3) ;load y(i) to R14 add $24, $15, $14 ;x(i) + y(i) sw $24, 8000 ($3) ;save new y(i) addi $3, $3, 4 ;update address reg, addr=addr+4 bne $3,$2,$label ;check it the loop counter=loop end

31 EE 3610: Digital Systems 31 MIPS Pipelining

32 PIPELINING: Why do we care? 32 Serial Microprocessor: Executes n instructions using s number of stages in ns clock periods Total Execution Time = ns Pipelined Microprocessor: Executes n instructions using s number of stages Total Execution Time = s + (n 1) Examples: n=30, s=5 Serial Microprocessor Pipelined Microprocessor 150 clock cycles 5+29=34 clock cycles

33 MIPS: Five Stages with Pipeline Registers 33

Data Hazards: Example1 34 Here, last four instructions require data from $2, which is changed in the first instruction data in $2 will not be rewritten

34 Data Hazards: Example1 34 Here, last four instructions require data from $2, which is changed in the first instruction data in $2 will not be rewritten until cycle 4, so the AND (2nd instruction) and OR (3rd instruction) will fetch incorrect data from $2 ADD may not get correct information SW will be correct

35 Solution: Stalling 35 One solution is in insert bubbles This means delaying certain operation in the pipeline lw $1, 4($2) IF ID EX MEM WB add $3, $1,$4 IF nop nop nop ID Another solution may require modification in the datapath, which will raise the hardware cost Hazards slow down the instruction execution speed An alternative approach to deal with this is for the compiler (or the assembler) to insert NOP instructions, or reorder the instructions

36 EE 3610: Digital Systems 36 Hardware testing and design for testability

37 Introduction Digital systems should be designed so that they are easy to test 37 Important to develop efficient testing methods Design for testability (DFT) Automatic test pattern generators (ATPG) Built in Self Test (BST) Testing Combinational Logic Testing Sequential Logic Scan Testing Boundary Scan

38 Testing Combinational Logic: stuck-at faults Two-level circuit 38 s-a-0 s-a-1

39 Scan Testing: Example 39 Q 1+ Q 2+ Q 3 + Z 1 Z 2 Q 1 Q 2 Q 3 X 1 X 2 = Shift 101 using TCK via SDI: Q 3 (LSB) First, Q 1 (MSB) last

40 Boundary Scan 40

41 Boundary Scan 41 One cell of boundary scan shift register (BSR) is placed between each input/output and the core logic TEST Access Port (TAP) Pins TDI: Test data input (serial input into the shift register) TCK: Test Clock TMS: Test Mode Select TDO: Test Data Output (serial output from the shift register) TRST: Test Reset (resets TAP controller and test logic)

42 Additional Problems 42 Given a Problem, Write the VHDL Process

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle