Binary Phase Shift Keying Demodulation Using Digital Signal Processor

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1 Binary Phase Shift Keying Demodulation Using Digital Signal Processor Roopa.V 1, R.Mallikarjuna Setty 2 1 Sree Siddaganga College of Arts, Science and Commerce for Women, B.H.Road, Tumkur , Karnataka 2 Vijaya First Grade College, South End circle, Bangalore , Karnataka ABSTRACT This paper describes about BPSK demodulation using costas loop and implementing on a DSP kit. The demodulation process can be divided into three major subsections. First, since the incoming waveform is suppressed carrier in nature, coherent detection is required. The methods by which a phase-coherent carrier is derived from the incoming signal are termed carrier recovery. Next, the raw data are obtained by coherent multiplication, and used to derive clock-synchronization information. The raw data are then passed through the filter, which shapes the pulse train so as to minimize inter symbol-interference distortion effects. This shaped pulse train is then routed, along with the derived clock, to the data sampler which outputs the demodulated data. The codes for the PLL and the Costas loop are written in C language and implemented on the DSP kit ADSP [1,2] The various input and output plots are observed on the SHARC (Super Harward Architecture) simulator and also on the Emulator. Keywords: BPSK Demodulation, Costas Loop, Digital Signal Processor and SHARC simulator. 1. INTRODUCTION In the earlier days in satellite communication analog systems were used for the communication between the base station and the satellite, but there were many disadvantages of using the analog systems for satellite communication. The incorporation of the analog system for communication occupied large area on the satellite up to few square feet. This would in turn lead to more consumption of the fuel which was not preferred. This lead to the use of digital systems for communication.[6,7] The advantages of the digital systems are, they are less expensive, more compatible, easy to manipulate, flexible, compatible with other digital systems, transmission without degradation and integral network. These advantages lead to use of digital systems in satellite communication.[8] There are different techniques of digital modulation namely ASK (Amplitude shift keying), FSK (frequency shift keying), PSK (phase shift keying), QPSK (quadrature phase shift keying), MSK (minimum shift keying), but for satellite communication the BPSK is employed the reason behind that is communication between the base station and the satellite is small commands in which the data rate is less of around 4Kbps, hence the BPSK type of modulation and demodulation is employed. BPSK is preferred over FSK because FSK causes Doppler shift, it uses high speed transmission and less efficient in both power and bandwidth.[3] When you submit your paper print it in one-column format, including figures and tables. In addition, designate one author as the corresponding author. This is the author to whom proofs of the paper will be sent. Proofs are sent to the corresponding author only. 2. INTRODUCTION TO DIGITAL SIGNAL PROCESSOR (DSP) Digital Signal Processors are a special class of microprocessors that are optimized for computing the real time calculations used in signal processing. Although it is possible to use some fast general purpose microprocessors for signal processing, they are not optimized for that task. The resulting design can be hard to implement and costly to manufacture. In contrast, DSPs have an architecture that simplifies application designs and makes low cost signal processing a reality. The kinds of algorithms used in signal processing can be optimized if they are supported by a computer architecture specifically designed for them. In order to handle digital signal processing tasks efficiently, a microprocessor must have the following characteristics. Volume 2, Issue 9, September 2014 Page 76

Fast, flexible computation units. Unconstrained data flow to and from the computation units. Extended precision and dynamic range in the computation units. Dual address generates.

1 Capabilities Floating point: A processor s data format determines its ability to handle signals of different precision, dynamic range and signal to noise ratios.

2 Fast, flexible computation units. Unconstrained data flow to and from the computation units. Extended precision and dynamic range in the computation units. Dual address generates. Efficient program sequencing and looping mechanisms. 2.1 Capabilities Floating point: A processor s data format determines its ability to handle signals of different precision, dynamic range and signal to noise ratios. However, ease of use and time to market considerations are often equally important. Precision: The precision of converters has been improving and will continue to increase. In the past few years, average precision requirements have raised by several bits and the trend is for both precision and sampling rates to increase.[4] Dynamic range: Traditionally, compression and decompression algorithms have operated on signals of known bandwidth. These algorithms were developed to behave regularly, to keep costs down and implementations easy. Increasingly, the trend in algorithm development is to remove constraints on the regularity and dynamic range of intermediate results. Adaptive filtering and imaging are 2 applications requiring wide dynamic range. Signal to noise ratio: Radar, Sonar and even commercial applications (like speech recognition) require a wide dynamic range to discern selected signals from the noisy environments. Ease of use: Ideally, floating point digital signal processors should be easier to use and allow a quicker time to market than DSPs that do not support floating point formats. If the floating point processor s architecture is designed properly, designers can spend time on algorithm development instead of assembly coding, code paging and error handling. The following features are hallmarks of a good floating point DSP architecture.[4] Consistency with IIEEE workstations simulations. Elimination of scaling. High level language programmability. Large address spaces. Wide dynamic range. Figure 1 : Architecture of ADSP 2106x processor Volume 2, Issue 9, September 2014 Page 77

3. FEATURES OF ADSP 21000 FAMILY The ADSP 21020 and ADSP 21060 are the first members of Analog Devices ADSP 21000 family of floating point Digital Signal Processors.

3 3. FEATURES OF ADSP FAMILY The ADSP and ADSP are the first members of Analog Devices ADSP family of floating point Digital Signal Processors. ADSP family architecture meets the 5 central requirements for DSPs that are mentioned above. Fast and Flexible Arithmetic: The ADSP can execute all instructions in a single cycle. It provides one of the fastest cycle times available and the most complete set of arithmetic operations, including Seed 1/X, Min, Max, Clip, Shift and Rotate in addition to the traditional multiplication, addition, subtraction and combined addition/subtraction. It is IIEEE floating point compatible and allows either interrupt on arithmetic exceptions or latched status exception handling. Unconstrained Data Flow: The ADSP as a Harward architecture combined with a 10 port, 16 word data register file. In every cycle the following operations can be executed. The register file can read or write two operand off-chip The ALU can receive two operands The multiplier can receive two operands The ALU and multiplier can produce two results The processors 48-bit orthogonal instruction word supports parallel data transfer and arithmetic operations in the same instruction. Extended IEEE-Floating-Point Support: All members of the ADSP family handle 32-bit IEE floating-point format,32-bit integer and fractional formats, and an extended precision 40-bit IEEE floating-point format. These processors carry extended precision throughout their computation units, limiting intermediate data truncation errors. The fixed-point formats have an 80-bit accumulator for true 32-bit fixed point computations. Dual address Generators: The ADSP has two data address generators(dag) that provide immediate or indirect addressing. Modulus and bit-reverse operations are supported, without constraints on buffer placement. Efficient Program Sequencing: In addition to zero-overhead loops, the ADSP supports single-cycle setup and exit for loops. Loops are nestable (six levels in hardware) and interruptible. The processor also supports delayed and non-delayed branches. Figure 2: pin diagram of ADSP 2106x Volume 2, Issue 9, September 2014 Page 78

4 4. Other features available in ADSP Data Register File: A general purpose data register file transfers data between the computation units and the data buses, and for storing intermediate results. This 10 port, 32 register (16 primary and 16 secondary) register file, combined with the ADSP Harvard architecture, allows unconstrained data flow between computation units and memory. Instruction Cache: The ADSP includes high performance instruction cache that enable three-bus operation for fetching an instruction and two data values. The cache is selective, only the instruction whose fetches conflict with PM bus data accesses are cached. This allows full-speed execution of looped operations such as digital filter multiplyaccumulates and FFT butterfly processing. Flexible Instruction Set: The ADSP bit instruction word accommodates a variety of parallel operations, for concise programming. For example, in a single instruction, the ADSP can conditionally execute a multiply, an add, a subtract and a branch. Serial Scan and Emulation Features: The ADSP supports the IEEE standard P1149 Joint Test Action Group(JJAG) standard for system test. This standard defines a method for serially scanning the I/O status of each component in a system. The serial port gives access to the ADSP on-chip emulation features. Interrupts: The ADSP has five external hardware interrupts(four general purpose interrupts and a special interrupt for reset), nine internally generated interrupts and eight software interrupts. For the general purpose external interrupts and internal timer interrupt, the processor automatically tracks the arithmetic status and mode registers in parallel with servicing the interrupt, allowing four nesting levels of very fast service for these interrupts Timer: The programmable interval timer provides periodic interrupt generation. When enabled the timer decrements a 32-bit count register every cycle. When this reaches zero, the ADSP generates an interrupt and asserts its TIMEXP output. The count register is automatically reloaded from a 32 bit period register and the count resumes immediately. Internal Data Transfers: Nearly every internal resister of the ADSP is classified as a universal register. Ads instruction provide for transferring data between ant two universal registers or between a universal register and external memory. This includes control registers and status registers, as well as the data registers in the register file. 5. Computation Units The computation units of the ADSP provide the numeric processing power for performing DSP algorithms. The ADSP contains three computation units : An arithmetic/logic unit (ALU). A multiplier A shifter. Both fixed-point and floating point operations are supported by the processor. Each computation unit executes instructions in a single cycle. Figure 3: Computational Unit Volume 2, Issue 9, September 2014 Page 79

5 The individual registers of the register file are prefixed with an f when used in floating-point computations. The register are prefixed with an r when used in fixed-point computations. Rounding: Two modes of rounding are supported in the ADSP : round towards zero and round towards nearest. Round toward Zero- If the result before rounding is not exactly representable in the destination format, the rounded result is that number which is nearer to zero. This is equivalent to truncation. Round toward Nearest- If the result before rounding is not exactly representable in the destination format, the rounded result is that number which is nearer to the result before rounding.[5] ALU Operation: The ALU takes one or two input operands, called the X input and the Y input, which can be any data registers in the register file. It usually returns one result, in add/subtract operations it returns two results, and in compare operations it returns no result(only flags are updated). ALU results can be returned to any location in the register file. The input operands are transferred from the register file during the first half cycle. Results are transferred to the register file during the second half of the cycle. Thus the ALU can read and write the same register file location in a single cycle. ALU Instruction Summary Instruction ASTAT Status STKY status Flags Flags Fixed point: AZ AV AN AC AS AI AF CACC AV AO AIS AUS S S Rn=Rx+Ry * * * * ** - Rn=Rx-Ry * * * * ** - Rn=Rx+Ry+CI * * * * ** - Rn=Rx-Ry+CI- I * * * * ** - Rn=Rx+Ry * * * * ** - Rn=(Rx+Ry)/2 * 0 * * COMP(Rx,Ry) * 0 * * Rn=Rx+CI * * * * ** - Rn=Rx+CI-1 * * * * ** - Rn=Rx+1 * * * * ** - Rn=Rx-1 * * * * ** - Rn=-Rx * * * * ** - Rn=ABS Rx * * 0 0 * ** - Rn=PASS Rx * 0 * Rn=Rx AND Ry * 0 * * Rn=Rx OR Ry * 0 * Rn=Rx XOR Ry * 0 * Rn=NOT Rx * 0 * Rn=MIN(Rx, Ry) * 0 * Rn=MAX(Rx, Ry) * 0 * Rn=CLIP Rx BY Ry * 0 * Rn=FIX Fx BY Ry * * * 0 0 * 1 - ** ** - ** Rn,Rx,Ry Any register file location, treated as fixed point Fn,Fx,Fy Any register file location, treated as floating point C ADSP 21xx compatible instruction * set or cleared, depending on results of instruction ** may be set(but not cleared), depending on results of instruction Multiplier Operation: The multiplier performs fixed point or floating multiplication and fixed point multiply / accumulate operations. Fixed point multiply/accumulates may be performed with either cumulative addition or cumulative subtraction. Floating point multiply accumulates can be accomplished through parallel operation of the ALU and multiplier, using multifunction instructions. The multiplier takes two input operands, called the X input and the Y input, which can be any data register file. Fixed point operations can accumulate fixed point results in either of two local multiplier result(mr) registers or write back to register file. Input operands are transferred during the first half of the cycle. Results are transferred during the second half of the cycle. Thus the multiplier can read and write the same register file location in a single cycle. Volume 2, Issue 9, September 2014 Page 80

6 6. MEMORY MANAGEMENT AND INTERFACE The ADSP has two distinct but similar memory interfaces: one program memory, which contains both instructions and data, and one for data memory, which contains data only. The processor is capable of connecting to a number of different memory devices and memory mapped peripherals. Minimal external hardware is required for a variety of configurations.[9] The ADSP provides on chip memory management. Program and Data memory spaces are user configurable into banks(two for program memory, four for data memory). Wait states for each bank are independently programmable. The processor also detects page boundaries to facilitate memory paging. The bus request/bus grant protocol allows an external device to take control of the processor s memory buses. This is useful for transferring data to its memory, for example the ADSP also has an internal bus exchange path for transferring data between the program memory and data memory spaces. For the project a program memory(prom) of 65k bytes and data memory consisting of 3 banks, bank 0-1M bytes and bank2 16K*16 is made use of. Data Addressing: The ADSP 21020/21010 s two data address generators(dags) simplify the task of organizing data by maintaining pointers into memory. The DAGs allow the processor to address memory indirectly, that is, an instruction specifies a DAG containing an address instead of the address value itself. Data Address generator 1(DAG1) produces 32-bit address for data memory. Data address generator2 (DAG2) produces 22- bit address for program memory. The DAGs also support in hardware some functions commonly used in digital signal processing algorithms. Both DAGs support circular buffers, which require advancing a pointer repetitively through a range of memory. DAG1 can also perform a bit-reverse operation, which places the bits of an address in reverse order to form a new address.[10] DAG Registers : Each DAG contains four types of registers: Index(I), Base(B) registers, and Length(L) registers. An I register acts as a pointer to memory, an M register contains the increment value for advancing the pointer. By modifying an I register with different M values, you can vary the increment as needed. B registers and L registers are used only for circular data buffers. A B register holds the base(starting) address of a circular buffer. The same numbered L register holds the number of locations in(i.e. the length of) the circular buffer. System Interface : The external memory interface supports memory mapped peripherals and slower memory with a user defined combination of programmable wait states and hardware acknowledge signals. Both the program memory and data memory interfaces support addressing of page mode DRAMs. The ADSP s internal functions are supported by four internal buses: the program memory address (PAM) and data memory address(dma) buses are used for addresses associated with program and data memory. The program memory data(pmd) and data memory data(dmd) buses are used for data associated with the two memory spaces. These buses are extended off chip. Four data memory select (DMS) signals select one of four user configurable banks of data memory. Similarly, two program memory select(pms) signals select between two user configurable banks of program memory. All banks are independently programmable for 0-7 wait states.[11] The PX registers permit passing data between program memory and data memory apaces. They provide a bridge between the 48 bit PMD bus and the 40 bit DMD bus or between the 40 bit register file and the PMD bus. The PMA bus is 24 bits wide allowing direct access of up to 16 M words of mixed instruction code and data. The PMD is 48 bits wide to accumulate the 48 bit instruction width. For access of 40 bit data the lower 8 bits are unused. For access of 32 bit data the lower 16 bits are ignored. The DMA bus is 32 bits wide allowing direct access of upto 4 Gigawords of data. The DMD bus is 40 bits wide. For 32 bit data, the lower 8 bits are unused. The DMD bus provides a path for the contents of any register in the processor to be transferred to any other register or to any external data memory location in a single cycle. The data memory address comes from one of two sources: an absolute value specified in the instruction code(direct addressing) or the output of a data address generator (indirect addressing). External devices can gain control of the processor s memory buses from the ADSP by means of the bus request/ grant signals (BR and BG). To grant its buses in response to a bus request, the ADSP halts internal operations and places its program and data memory interfaces in a high impedance state. In addition, three state controls(dmts and PMTS allow an external device to place either the program or data memory interface in a high impedance state without affecting the outer interface and without halting the ADSP unless it requires a memory access from the affected interface. The three state controls make it easy for an external cache controller to hold the ADSP off the bus while it updates an external cache memory. Volume 2, Issue 9, September 2014 Page 81

7 7. Software Development: Figure 4 : System development You begin code generation by creating assembly language source code files. Each file is assembled separately by the assembler. Several files are then linked together to form an executable program. The linker reads the target hardware information from the architecture description file to determine placement of code and data segments. Non relocatable code or data segments are placed at specified memory addresses, provided the memory area has the correct attributes. Relocatable objects are placed in memory by the linker. The linker generates a file containing a single executable program, which may be loaded into a simulator or emulator for testing. The simulator provides a window based interface that displays different portions of the hardware environment. To replicate the target hardware, the simulator configures its memory according to the architecture description file and simulates memory mapped I/O ports [12]. This simulation allows you to debug the system and analyze performance before committing to hardware prototype. After fully simulating your system and software, you can use an emulator in the prototype hardware to test circuitry, timing, and real time software execution. 8. Conclusion A lot of thought, research and experimentation has gone into this project. There is no such thing as an ideal design, further modifications can be done to this project to improve its performance. For any assignment a basic foundation is necessary and this is what we have tried to achieve in this venture. Costas demodulation loop has been successfully implemented using ADSP processor. By making slight modifications of the design equations it is possible to use the same program for real time high quality demodulation purpose. The focus of this project does not lie in merely implementing some concept, but rather in studying the various ways in which it can be implemented. Volume 2, Issue 9, September 2014 Page 82

8 9. Future Scope of the Project BPSK modulation and demodulation is used for a low data transmission of commands from the base station to the satellite system. Also there is sometimes phase ambiguity at the receiver. So for transmitting any information at a higher data rate and in order to improve the overall efficiency, it can be extended to Quadrature Phase Shift Keying (QPSK) in which two bits can be represented using a single phase of the carrier. The error rates of both BPSK and QPSK are same. In QPSK the bandwidth requirement is half as that of BPSK and data rate is twice. Also this can be extended to M-array modulation in which M bits are represented using one phase of the carrier thus reducing the bandwidth requirement. References [12] Roland E. Best- Phase Locked Loops- Design, Simulation, and Applications McGraw-Hill [13] Paul V. Brennan Phase-Locked Loops- Principles and Practice Macmillan Press Ltd [14] Alain Blanchard-Phase-Locked Loops-Applications to Coherent Receiver Design John Wiley & Sons Inc [15] Hari Krishna Garg-Digital Signal Processing Algorithms CRC Press LLC [16] Johnathan(Y) Stein-Digital Signal Processing A computer Science Perspective A Wiely Interscience Publictions [17] JJ Spilker-Digital Communications by Satellite Prentice Hall Inc [18] Leon W. Couch. Digital and Analog Communication systems Prentice Hall Inc [19] Benjamin C. Kuo- Automatic Control Systems Prentice Hall Inc [20] ADSP Family Assembler Tools and Simulator Manual- July [21] Santanu Sarma, P.K. Maharana and V.K. Agarwal Flexible Mode Frequency Trackling using Phase Locked Loop July [22] Marcelo J. Bruno, Juan E. Cousseau and Pedro D. Donate on reduced complexity Iir Adaptive filters (2005 IEEE International Symposium on circuits and systems) William Stallings- Wireless Communication and Networking Pearson Education Inc Volume 2, Issue 9, September 2014 Page 83

This section discusses resources available from Analog Devices to help you develop applications using ADSP Family digital signal processors.

This section discusses resources available from Analog Devices to help you develop applications using ADSP Family digital signal processors. Introduction This applications handbook is intended to help you get a quick start in developing DSP applications with ADSP-2000 Family digital signal processors. This chapter includes a summary of available