SystemC Users Forum - Japan. February 1, 2001

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1 SystemC Users Forum - Japan February 1, 2001

2 Agenda Why SystemC? Organizational Update The Growing SystemC Marketplace SystemC v2.0 Roadmap v2.0 Capabilities and Benefits v1.2beta Capabilities and Benefits 2

3 SystemC Mission - Model Concept to RTL Specify Co-Design Code Software Reuse IP Environment Product Architecture Reuse IP Hardware Design Concept to RTL & Software Implement Co-Verify Verify SW Code Implement Verify Reusable IP Integration HW Design Implement Verify RTL to GDSII 3

4 SystemC - Enabling System Level Design HW Implementation Verification & Analysis SW Implementation System System Level IP RTL Physical Soft IP Hard IP C-Compiler 4

5 Why SystemC? Stan Krolikoski Vice President System Level Design Group Cadence Design Systems

Exploration 2.0 Links to Verification and Implementation 1.

6 The Evolution of SystemC Full System Specification 2.x/3.y Algorithm Design System Architecture Design Space Exploration 2.0 Links to Verification and Implementation 1.0 Advanced & Functional Verification Synthesis / Place & Route etc. 6

7 We ve been here before During the 1960/1970 s, many SW languages were created Lack of compatibility between SW modules became a real issue Even single languages had multiple dialects Eventually C/C++ became the de facto standard Others still being used, e.g., Ada, Lisp,... During the 1970/1980 s, multiple HDLs started to be developed Strong actions by the US department of defense helped create VHDL Market dominance helped Cadence establish Verilog Not many alternative HDLs are being used today But we still ended up with two! Let s not repeat the past! 7

8 We are at a fork in the road System level design is becoming necessary The size, speed and complexity of the latest designs require a higher level of abstraction than RTL Good system languages will be crucial in enabling system-level design Even in systems that are GUI based Therefore, we need to develop system languages, but. Can we afford to have many system level languages? NO!!!!!! 8

9 There must be A language for system design We cannot get into the mess we were with SW languages We cannot even afford to have two dominant languages as in the HDL world We need a single language that can serve as A backbone for system-level design tools A common format for system level IP exchange and tool interoperability Other languages may still be used for specialized tasks, but we need a common system-level language That Language is SystemC 9

10 We need everyone s help! SystemC must meet the needs of both users and vendors This requires a strong cooperation between companies Even between strong rivals-- we are all in this together The SystemC group already has a good mixture of vendors and users from around the world But we need more members, and we need more user participation in evolving SystemC If SystemC is OUR language, then WE must develop it 10

11 Organizational Update Pete Hardee Director, Product Marketing CoWare

12 Open SystemC Initiative Delivers! Fast Innovation SystemC v2.0 Specification major step in system level modeling cross industry contributions - Cadence, CoWare, Fujitsu, Motorola, STM, Synopsys SystemC v1.2 beta Software Common, Open Industry Solution OSCI incorporated NOW as non profit organization OSI-compliant Open Source license Broad industry adoption and success! 12

13 Open SystemC Initiative Steering Group ARM Cadence* CoWare Ericsson Fujitsu Infineon Lucent Motorola* NEC* STMicroelectronics Sony Synopsys Texas Instruments *elected 6/00

14 Strong User Adoption and Success Over 7,000 Licensees at over 500 companies/institutions Over 12,000 successful downloads of SystemC source code SystemC successes presented at numerous venues DATE, FDL, HDL Con, IP/SoC, ASP/DAC, ESP, CSELT, Infineon, Siemens, STM,... Commercial projects featured on web based SystemC Forum at 14

15 A year of Strong SystemC Adoption Downloads Licensed Users SystemC v1.0/1.1beta Released Sep-99 Nov-99 Jan-00 Mar-00 May-00 Jul-00 Sep-00 Nov-00 Users/Downloads 15

16 SystemC Solutions Kevin Kranen Director, Strategic Programs Synopsys, Inc.

17 SystemC Value Chain is Building Solutions include EDA, IP and Services Over 20 Companies / over 25 Products announced or released EDA tools - 20 Training - 6 IP - 2 See for exhaustive list 17

18 SystemC Product Briefs All product claims contained within are provided by the respective supplying company.

19 Blue Pacific Computing BlueWave Blue Pacific s BlueWave is a simulation GUI, including waveform viewer that can be used to view and analyze VCD results on Linux, Unix, Windows, including SystemC outputs. BlueWave Student version is free. Enables visualization and analysis of SystemC modeling Contact Blue Pacific at: info@bluepc.com of find us on the web at phone: (858)

20 Blue Pacific Computing SystemC Classes Three-day SystemC On-Site Classes focussing on SystemC for VHDL and Verilog Designer with additional two-day foundational course on C and C++ Teaches SystemC modeling and simulation to people with traditional Verilog or VHDL background. Contact Blue Pacific at info@bluepc.com or find us on the web at phone: (858)

SYSTEMSIM Multilingual simulator, supporting Verilog, Superlog, C, C++ and SystemC, without interfaces or co-simulation C / C++ HDL Superlog SYSTEMSIM SystemC Allows SystemC models to be called

21 SYSTEMSIM Multilingual simulator, supporting Verilog, Superlog, C, C++ and SystemC, without interfaces or co-simulation C / C++ HDL Superlog SYSTEMSIM SystemC Allows SystemC models to be called from alternative language constructs to provide a fast, usable method to solve alternative language IP and legacy code issues Contact Co-Design Automation, Inc, info@co-design.com 21

Vip Library: a wide set of customizable and flexible system level Intellectual Property Soft Cores to answer Information and Communication Technologies Product requirements

22 Vip Library: a wide set of customizable and flexible system level Intellectual Property Soft Cores to answer Information and Communication Technologies Product requirements Availability of SystemC Core description to stress architectural exploration before HW/SW partitioning is performed. Contact CSELT S.p.A, viplibrary@cselt.it, Visit Booth 4653 at DAC

23 CoWare N2C TM CoWare N2C - Napkin to Chip in Half the Time. Full SystemC Co-Design Environment featuring: Specification Partitioning }Analysis at every stage Co-implementation Co-verification Read in and write out SystemC from CoWare N2C CoWareC or SystemC in CoWareC, SystemC, VHDL and Verilog out Visit DAC booth #4745 or 23

24 CoWare N2C System-Level Design Flow Algorithms, Control and Testbench ANSI C/C++, SystemC or CoWare C IP and Performance Models Function Behavioral C System Design and Partitioning Cycle-Accurate C HW-SW Co-design and Multi-level level Co-verification Refine "Traditional" HW-SW Co-verification SystemC Executable Implementable Spec Testbench SW Optimization Interface Synthesis HW Design RTL SystemC Generate HDL RTL Implementation Refine Architecture 24

25 Databahn Memory Subsystem Generator Databahn, an on-line tool, generates synthesizable memory controller cores and automatically produces all C-level verification support for the associated memory subsystem Produces SystemC models of these cores Contact: Steven Shrader (208) , or visit our website at 25

EDS2001 Booth DT511 Proven SystemC-based architectural exploration Interactive C-to-HDL design flow Optimized implementation High level design re-use

26 EDS2001 Booth DT511 Proven SystemC-based architectural exploration Interactive C-to-HDL design flow Optimized implementation High level design re-use ASIC and FPGA Silicon proven for : ultra-low power applications telecom base-band processing consumer speech processing Contact info@frontierd.com 26

EDS2001 Booth DT511 Inputs Automatic SystemC-to-HDL What You Write Is What You Get Produces hierarchical Mealy Machine VHDL and Verilog output ASIC and FPGA Automatic

27 EDS2001 Booth DT511 Inputs Automatic SystemC-to-HDL What You Write Is What You Get Produces hierarchical Mealy Machine VHDL and Verilog output ASIC and FPGA Automatic test-bench generation Contact Compute process (combinatorial) Compute Update Update process (sequential) Clk Reset Enable Outputs 27

28 VStation Co-Modeling Ultra high-performance Co-Modeling between behavioral models running on a workstation and implementation models running on IKOS VStation. Based on the world s first high-performance transaction interface System verification productivity at emulation speed Enables SystemC models to be used in conjunction with emulation Bring the value of high performance emulation earlier in the verification process Utilizing your SystemC environment throughout the design cycle 28

29 Closing The Verification Productivity Gap Design Flow Untimed C Mixed-Level C RTL HDL Run 4 seconds real-time verification in 5 minutes Overnight 1.5 months Gate-Level 1.25 years Real Hardware 4 seconds 29

30 Visual SLD Systems-Level Design environment for defining and verifying system architecture, Hardware/Software co-verification, Register Definition. Includes Embedded Systems support, Complete code-coverage debug and analysis. Built upon the strongest graphic entry tool in the industry, Visual HDL. Truth-table, flowchart, Finite-State Machine, Block Diagram Language design via SystemC, C/C++, Verilog, VHDL come see Innoveda at booth (3101), or (800)

31 31 Visual SLD

32 TestBencher Pro Graphical environment for generating bus-functional models TestBencher generates SystemC test benches from language independent timing diagrams. Generates all the class code for each diagram, including port mappings and sensitivity lists Visit and download an evaluation version Contact SynaptiCAD at or

33 TestBencher Pro Generates SystemC Code

34 CoCentric TM Tools Architecture Functionality CoCentric TM System Studio SystemC CoCentric TM SystemC Compiler + a.out

CoCentric TM System Studio HW/SW Co-Design

for performance analysis of system architecture

35 CoCentric TM System Studio HW/SW Co-Design propelled by SystemC integrated system level tool for performance analysis of system architecture and function concurrent design of HW and SW at multiple levels of abstraction Contact or visit for more information 35

36 CoCentric TM SystemC Compiler Complete synthesis from SystemC to hardware C/SystemC synthesis refine & synthesize from C/C++ executable spec path to FPGAs for system designers powerful constructs for RTL designers Complete behavioral & RTL SoCs, ASICs, FPGAs Contact or visit for more information Behavioral or RTL CoCentric SystemC Compiler Design Compiler Physical Compiler FPGA Compiler II 36

37 SystemC-HDL Co-Simulation HDL Interface Library HDL VCS, Scirocco, MTI-VHDL Model import & export Contact or visit for more information 37

38 SystemC-VERA I/F High performance, direct kernel interface for integrating VERA with SystemC Uses the powerful, verification related features in VERA to verify system designs described in SystemC Contact or visit the website at for more information 38

39 TT VTOC Converts from Synthesisable Verilog to C/C++ Compiles multiple Verilog modules totalling up to about 100K gates into one large, highly-efficient, cycle-based C or C++ implementation. Provides a mechanism for efficient linking of separately compiled modules. Main applications are fast simulation and generation of a system-level emulator for the software team. SystemC is one of the output formats Web site is 39

40 SuperC A very fast SystemC Simulator that writes a highly compressed data format. This wave form data is compressed by 15-50X and can be displayed almost instantly by the Undertow waveform viewer regardless of file size. Veritools provides the SuperC C++ class compile library for the Veritools SuperC simulator Contact Veritools at inquiry@veritools.com or Robert Schopmeyer at schop@veritools.com 40

41 Undertow Suite A waveform viewer and Source Code debugging program for the SystemC/SuperC Simulator that reads the the highly compressed data format that is written directly by the SuperC simulator. This waveform data can be displayed almost instantly by the Undertow waveform viewer regardless of file size while providing linkage and synchronization with the SystemC source code. Undertow uses the highly compressed Fast file format from SuperC while providing Source Code debug facilities for SystemC Source Code. Contact Veritools at inquiry@veritools.com, or Robert Schopmeyer at schop@veritools.com 41

42 Undertow A very powerful waveform viewer for the SystemC/SuperC Simulator. This wave form data can be displayed almost instantly by the Undertow waveform viewer regardless of file data size Undertow uses the SystemC native waveform data or the highly compressed Fast file format from SuperC Contact Veritools, Inc. at inquiry@veritools.com or Robert Schopmeyer at schop@veritools.com 42

43 From Virtual Prototyping to SystemC Evaluate, experience, and design embedded IP platforms from your browser! Explore pre-configured embedded platforms, create high-level system models, and generate SystemC to link your designs to implementation. For more information contact or visit our web site at 43

44 Training: Modeling with SystemC. Introduction to modeling with C/C++ and the SystemC class libraries. Learn how to write, compile, execute, and debug system and hardware descriptions with SystemC. SystemC for High Level Synthesis(HLS) Learn HLS concepts, SystemC coding style required for HLS, testbenches and RTL co-simulation. For more information or for class schedules to or visit website at 44

45 Language Rule Checker Complete language rule checker Performs netlist, general coding style and synthesis coding style checks on your SystemC code. Contact Willamette HDL, 45

46 Open SystemC Initiative Delivers! Fast Innovation cross industry contribution Common, Open Industry Solution OSCI incorporating NOW as non profit organization OSI-compliant Open Source license Broad industry adoption and success! 46

47 SystemC v2.0 Roadmap Takashi Hasegawa, Director of Strategic Software Systems, World Wide System LSI Technologies - Fujitsu

48 SystemC v2.0 Innovation SystemC v1.0 RTL & behavioral level modeling (HDL & beyond) integrated with higher level C/C++ functional modeling SystemC v2.0 provides higher levels of abstraction enables modeling of HW / SW interaction flexible communication channel refinement 48

49 SystemC Evolution v2.0 Detailed Spec v1.2 beta v2.0 model of time Dynamic sensitivity Code fixes v2.0 beta New SystemC Foundation for Systems Channels & Events Comms Refinement Backward compatibility SystemC v2.0 LRM v2.0 Production User Validation Feb 2001 Q Q

50 SystemC Release Roadmap Hardware Design Flow RTL and Behavioral Hardware Modeling 1.x - Master-Slave Communication Library RPC-based untimed & timed functional modeling down to RTL for bus protocol based systems System Design Flow General purpose communication and synchronization Communication Refinement Multiple, customizable models of computation 50

51 SystemC Release Roadmap (cont) 2.X - Extensions to System Design Flow Dynamic thread creation, fork / join Interrupt / abort for behavioral hierarchy Performance modeling support Timing specification and constraints 3.X Software Design Flow Abstract RTOS modeling Scheduler modeling 4.X - Analog / Mixed Signal Systems Modeling 51

52 SystemC 2.0 Specification and Benefits Thorsten Grötker Synopsys, Inc.

53 Motivation SystemC 1.0 HW modeling (RTL and behavioral) SystemC 2.0 extend scope to System-Level Modeling System-Level Modeling functional models transaction-level platform models high-level architecture models 53

54 MoC: Model of Time SystemC 1.0 Relative floating-point model of time (double) SystemC 2.0 Absolute (64 bit) unsigned integer model of time Why? Avoid finite precision effects, e.g. underflow Use absolute model of time: define time units (IP exchange) 54

55 MoC: Rules for Process Activation SystemC 1.0 Static sensitivity Processes are made sensitive to a fixed set of signals during elaboration SystemC 2.0 Static sensitivity Dynamic sensitivity The sensitivity (activiation condition) of a process can be altered during simulation (after elaboration) Main features: events and extended wait() method 55

56 Events Events are objects (sc_event) Events can be notified (sc_event::notify()) Channels use events (Signals use events to indicate value changes.) Modules can use events Processes can wait for events (Dynamic sensitivity) 56

57 Waiting wait(); // as in SystemC 1.0 wait(event); // wait for event wait(e1 e2 e3); // wait for first event wait(e1 & e2 & e3); // wait for all events wait(200, SC_NS); // wait for 200ns // wait with timeout wait(200, SC_NS, e1 e2); wait(200, SC_NS, e1 & e2); 57

58 MoC: Communication SystemC 1.0 Fixed set of communication channels (sc_signal, ) and ports (sc_in, sc_out, ). SystemC 2.0 user-defined interfaces channels Define your own bus, message queue, etc. ports richer set of predefined channels (HW signals, FIFO, semaphore, mutex, ) 58

59 Interfaces and Channels An interface is a set of methods implemented by a channel. struct write_if : public sc_interface { virtual void write(char) = 0; virtual void reset() = 0; }; struct read_if : public sc_interface { virtual void read(char &) = 0; virtual int num_available() = 0; }; A channel can implement multiple interfaces. 59

60 Ports Ports connect modules and channels specify the required interface (e.g. sc_port<if>) give modules (processes) access to interface methods sc_port<write_if> p; void some_process() {... p->reset(); p->write( X );... } 60

61 Primitive and Hierarchical Channels Primitive channels are atomic entities have no visible internal structure can use request-update scheme (HW signals) Hierarchical channels are modules that implement interfaces can have ports can contain processes, modules, and channels Both implement interfaces 61

62 Architecture of SystemC 2.0 Methodology-specific and User-Defined Channels Elementary channels (signals, FIFOs, ) Channels, Interfaces, Ports Events, Dynamic Sensitivity SystemC Scheduler 62

63 Model of Computation Very powerful and flexible Supports well known MoCs such as discrete-event models RTL / behavioral HW models network modeling transaction-level SoC platform modeling Kahn process networks static multi-rate data flow dynamic data flow Communicating Sequential Processes 63

64 Benefits of SystemC v2.0 Enables, fast smooth system design Communication can modeled and refined independent of function Supports virtually all system modeling needs Flexible semantic foundation additions support most models of computation within one environment Leverages all existing v1.0 and v1.1beta capabilities Broadly applicable, best of breed solution Designed by 12 experts from six different EDA and System IC companies Tuned for both EDA tool and IP use 64

65 SystemC v1.2 beta Capabilities and Benefits Dundar

66 Panel Session

67 Panelist names and titles 67

Appendix SystemC Product Briefs. All product claims contained within are provided by the respective supplying company.

Appendix SystemC Product Briefs All product claims contained within are provided by the respective supplying company. Blue Pacific Computing BlueWave Blue Pacific s BlueWave is a simulation GUI, including