MAXQ PIC16CXXX ( ) AVR MAXQ 1 MNEMONIC DESCRIPTION MNEMONIC DESCRIPTION
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1 43 RISC 16CXXX ( ) MIPS ( )ma SOURCE SPECIFIER 1. - DESTINATION SPECIFIER FORMAT BIT ( = IMMEDIATE SOURCE, 1 = MODULE SOURCE) MNEMONIC DESCRIPTION MNEMONIC DESCRIPTION BIT MANIPULATION LOGICAL MOVE C, ##1 ClearSet Carry AND Logical AND CPL C Complement Carry OR Logical OR AND Acc.<b> Logical AND Carry with Accumulator Bit XOR Logical XOR OR Acc.<b> Logical OR Carry with Accumulator Bit CPL,NEG One's, Two's Complement XOR Acc.<b> Logical XOR Carry with Accumulator Bit SLA,SLA2, SLA4 Shift Left Arithmetically 1,2,4 MOVE C, Acc.<b> Move Accumulator Bit to Carry SRA,SRA2,SRA4 Shift Right Arithmetically 1,2,4 MOVE Acc.<b>,C Move Carry to Accumulator Bit SR Logical Shift Right MOVE C, src.<b> Move Register Bit to Carry RR,RRC Rotate Right Carry (ExIn) clusive MOVE dst.<b>, ##1 ClearSet Register Bit RL,RLC Rotate Left Carry (ExIn) clusive MATH DATA TRANSFER ADD, ADDC Add Carry (ExIn) clusive XCHN Exchange Accumulator data nibbles SUB, SUBB Subtract Carry (ExIn) clusive XCH (2) Exchange Accumulator data bytes FLOW CONTROL AND BRANCHING MOVE dst, src Move source to destination JUMP {CNCZNZENES} Jumps - unconditional or conditional, relative or absolute PUSHPOP PushPop stack DJNZ LC[n], src Decrement Counter, Jump Not Zero POPI Pop stack and enable interrupts (INS ) CALL Call relative or absolute Other RET {CNCZNZS} Return unconditional or conditional NOP No Operation RETI {CNCZNZS} Return from Interrupt unconditional or conditional CMP Compare with Accumulator 7
2 ... ( ) 1. ISA STRENGTH WEAKNESS 16CXXX general-purpose ( working ) registers (accumulators) Data pointers are part of the directly addressable working registers; allow easy masking and bit-manipulation + ( of 63 highlow ) pointer bytes. Read from pointer + displacement RAM ( to 63-byte displacement) ( Stack 9S12 limited only by RAM internal RAM =3) (except 9S12 with no RAM, then stack depth = 3) Single-cycle operation ±2k ( ) Relative jumps ±2k (two-cycle) All have data EEPROM EEPROM Explicit instructions to setclear each status register flag; large group of bit-manipulating instructions Separate interrupt vectors Source, destination ALUbit encoded into ALU operations ( ) Direct data access (symbolic addressing mode) can produce dense code and is conducive to data overlays Pipelined instruction fetch Beyond the 32 regs, load (LD)store 32 (LD) (ST) overhead becomes a factor (ST) = two cycles, LDST = 3 Y, cycles Z = LPM Reduced = 3 supportscope on literal operations (no ADDC, EORI; only CPI, ORI, ANDI, SUBI, SBCI, LDI ( ADDC EOR1 CPI ORI work on R16 R31) ANDI No rotate SUBIinstructions SBCI LDI exclusive of carry R16 R31 ) Conditional jump range only (two-cycle) ( ) CALLRETRETI = four cycles CALLRETRETI = four-clock core yields poor execution speed Pipelined instruction fetch Access to upper data-memory banks (RP1: requires paging ) (RP1: bank select) Indirect data access INDFrequires INDF,FSR registers Cannot directly load W (accumulator) W( ) ADDC No ADDC, SUBB SUBB Stack =8 depth = 8 No relative jumpsbranches only (CALL absolute (CALL, GOTO) or GOTO) conditional skips (BTFSx) (BTFSx) RETLW for code memory = reads = wasted code space and does CRC not allow CRC of code space CALLGOTORETRETFIERETW CALLGOTORETRETFIERETW all require eight clock ( cycles ) (two instruction cycles) Single interrupt vector 1 ( ) Dallas Semiconductor 8
3 1. ( ) ISA STRENGTH WEAKNESS 43 Extensive source, destination addressing modes are encoded within the op code can yield dense 16code 16-bit internal data path Internal memory (CG) accessible -1 1 as word or byte Constant generator (CG) for -1,, 1, 2, 4, 8 Single-cycle operation RAM Stack limited only by internal = ±512RAM Conditionalrelative jump destination ( ) range = ±512 (two-cycle) Separate interrupt vectors, singlesource flags automatically cleared System and peripheral registers are accessible as source or destination in the same logical memory space, yielding the fastest data transfers Single-cycle operation and no pipelining ( ) Single-cycle conditional ( 65,535) jump ( ) or two-cycle absolute CALLRETRETI jump ( 65,535) Single-cycle CALLRETRETI Auto-decrementing loop-counter registers eliminate overhead normally wasted when maintaining (FP) a counter Three + data pointers with autoincrementdecrement BP[Offs]) support. One ( data pointer, ( FP, supports ) base pointer + offset addressing (i.e., BP[Offs]). Auto-incrementdecrementmodulo controls for accumulator (working register) file Selectable word or byte-access mode for each data pointer Prefixable op code allows a simple means for instruction set extensions or enhancements Von Von Neumann Neumann memory + map + elaborate addressing modes = many = cycles. The ONLY single-cycle instructions are Rn those dealing exclusively with = 3 Rn. 6 Peripheral CGregister access = three to six cycles Literals not supported by CG require extra word Destination operand cannot be register indirect or register indirect auto-increment No auto-decrement support for register indirect Symbolic addressing limits the ability to reuse code routines Active accumulator ALU is always the implicit destination for ALU operations SRAM Single-port, synchronous, SRAM data memory requires that ( a data) pointer be activated = 16 (selected) before being used Default stack depth = 16, however, data pointer hardware is ideal for implementing a soft stack in data memory (MemCpy64 )
4 ;============================================================================ ; ramsize=r16 ;size of block to be copied ; Z-pointer=r3:r31 ;src pointer ; Y-pointer=r28:r29 ;dst pointer ; USES: ; ramtemp=r1 ;temporary storage register loop: ; cycles ld ramtemp,z+ ; => temp st Y+,ramtemp ; 2 temp dec ramsize ; 1 brne loop ; 21 ret ; 45 ; ;(7*bytecount) + return 1(last brne isn t taken). ; WORD COUNT = 5 ; CYCLE COUNT = 451 ;=====================================1==================================== ; DP[] ; src pointer (default WBS=) ; DP[1] ; (dst-1) pointer (default WBS1=) ; LC[] ; byte count (Loop Counter) loop: ;words & cycles move DP[], DP[] ; 1 implicit DP[] pointer selection ; 1 djnz LC[], loop ; 1 ret ; 1 ; ; 4 (3*bytecount) +1 ; WORD COUNT = 4 ; CYCLE COUNT = 193 ;====================================2===================================== ; Assuming bytes are word aligned (like 43 code) for comparison ; DP[] ; src pointer (default WBS=1) ; DP[1] ; (dst-1) pointer (default WBS1=1) ; LC[] ; byte count (Loop Counter) loop: ;wordscycles move DP[], DP[] ; 1 implicit DP[] pointer selection ; 1 djnz LC[], loop ; 1 ret ; 1 ; ; 4 (3*bytecount2) +1 ; WORD COUNT = 4 ; CYCLE COUNT = 97 1 ;====================================43===================================== ; 43 has a 16-bit data bus ; assuming bytes are word aligned, only requires (blocksize2 transfers). ; R4 ;src pointer ; R5 ;dst pointer ; R6 ;size of block to copy loop: ;wordscycles (R5) ;2 => dst add #2, R5 ;1 1 const generator makes this 11 decd.b R6 ;1 1 really sub #2, R6 jz loop ;1 2 ret ;1 3 ; ;6 (9*(bytecount2)) + return ; WORD COUNT = 6 ; CYCLE COUNT = 291 ;===================================16CXXX=================================== ; a ; src pointer base ; b ; dst pointer base ; i ; byte count held in reg file ; USES: ; temp ; temp data storage loop: ; cycles decf i, W ; 1 i-- => W addlw a ; 1 (a+i--) => W starting at end movwf FSR ; 1 W => FSR movfw INDF ; 1 W get data movwf temp ; 1 W => temp
5 movlw (b-a) ; 1 diff in dest-src addwf FSR, F ; 1 (b+i--) => W movfw temp ; 1 temp => W movwf INDF ; 1 W store data decfsz i, F ; 21 i-- goto loop ; 2 return ; 2 ; ;11 (12*bytecount) +1 (ret instead of goto, +1 on decfsz) ; WORD COUNT = 12 ; CYCLE COUNT = 769 (*4clksinst cycle = 376) MemCpy64 MemCpy64 CYCLEBYTE COUNT COMPARISON CYCLES BYTES ( 43 2 ) 1 1) 2) 3) Harvard 4) ADC ADC ; wordscycles mov.w &ADAT,(R14) ; 3 6 Store output word incd.w R14 ; 1 1 Increment pointer ; ADCOUT ;
6 (BubbleSort ) 32 BubbleSort BubbleSort CYCLEBYTE COUNT COMPARISON CYCLES 25, 2, 15, 1, ,58 BYTES ASCII (Hex2Asc ) 16 ( 9 A F) Hex2Asc Hex2Asc CYCLEBYTE COUNT COMPARISON CYCLES BYTES (#nnnnh) Atmel 43 2 (ShRight ) 16 ALU 16 ( )
7 CYCLES 16 ALU ALU ShRight CYCLEBYTE ShRight COUNT COMPARISON BYTES ( ) 43 (RRA@R5) (SRA2 SRA4 SLA2 SLA4) (BitBang ) ( ) IO BitBang CYCLEBYTE BitBang COUNT COMPARISON CYCLES BYTES ( ) 43 Von Neumann BitBang #3h) RISC ( ®ister) ( ( ) 43 IO 13
8 V ( ) ma MHz 2. -MHz STEEPER-DYNAMIC-CURRENT mamhz CHARACTERISTIC HIGHER INITIAL STATIC (DC) CURRENT (DC) CHARACTERISTIC 2 mamhz ma MHz ma (DC) mamhz mamhz (DC) ma-mhz ( ) 2 -MHz MIPS MIPS 3 MIPS MHz (CPI) Microchip 1 CLOCKSINSTRUCTIONS X MILLION CLOCKS SECOND = MIPS (MILLIONS ( INSTRUCTIONSSECOND) ) 3. CPI MIPS ( ) (MIPS) MIPS 14
9 2. mamhz DEVICE TYAL MAX mamhz mamhz SOURCE 16C55X C55X data sheet: DC Table 1.1, D1 (V CC = 3V, 2MHz); XT or RC 16C62X C62X data sheet: DC Table 12.1, D1 (V CC = 3V, 2MHz); XT or RC 16LC C71X data sheet: DC Table 15.2, D1 (V CC = 3V, 4MHz); XT or RC 16F62X F62X data sheet: DC Table 17.1, D1 (V CC = 3V, 4MHz) 16LF F871 data sheet: DC Table 14.1, D1 (V CC = 3V, 4MHz); XT or RC AT9S AT9S12 data sheet: EC Table (3V, 4MHz), Figure 38, 4mA12MHz (typ) AT9S AT9S2313 data sheet: EC Table (3V, 4MHz), Figure 57, 7.5mA15MHz (typ) 43F x11x1 data sheet: DC specs IccActive (V CC = 3V, FMCLK = 1MHz) 43C11X x11x1 data sheet: DC specs IccActive (V CC = 3V, FMCLK = 1MHz) 43Fx12x x12x data sheet: DC specs (V CC = 3V, FMCLK = 1MHz, FACLK = 32kHz) 1.3 Simulations 2.3 Simulations MIPS MHz MIPSMHz ( ) MIPSMHz mamhz MIPSMHz 3. MIPSMHz CORE MIPSMHz MemCpy64 BubbleSort Hex2Asc ShRight BitBang Peak CORE MemCpy64 BubbleSort Hex2Asc ShRight BitBang MIPSMHz ( MIPSMHz 1) 3 (MIPSMHz =.33) ( ) 15
10 4. CORE NORMALIZED () MemCpy64 BubbleSort Hex2Asc ShRight BitBang (1) (2) 16
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