CA226 Advanced Computer Architecture

Size: px

Start display at page:

Download "CA226 Advanced Computer Architecture"

Tiffany Fisher
5 years ago
Views:

1 Table of Contents Stephen Blott 1

2 MIPS MIPS is: a RISC instruction-set architecture: all ALU operations are register-register initially 32-bit, later 64-bit Its design is heavily influenced by opportunities for instruction-level parallelism: and we ll talk much more about that later 2

3 MIPS Overview We will cover: 64-bit MIPS, as simulated by the WinMIPS64 simulator there is a summary of the (WinMIPS64) MIPS instruction set here [./mips/ winmips64.html] 3

4 MIPS Basics Basics: fixed-sized, 32-bit instructions r0 is always 0 31 general-purpose integer registers (r1,, r31) 32 floating-point registers (f0,, f31) byte, half-word, word and double-word addressing displacement addressing with 16-bit displacements 4

5 Integer Loads ld r1,64(r2) lw r1,64(r3) lh r1,64(r4) lb r1,64(r5) load double word from Mem[r2+64] load word from Mem[r2+64] load half word from Mem[r2+64] load byte from Mem[r2+64] 5

6 All addressing is displacement addressing Displacement addressing: ld r1,64(r2) Direct addressing: ld r1,1024(r0) ; use r0 (always 0) Register-indirect addressing: ld r1,0(r2) ; use a displacement of 0 6

7 Immediate Addressing int i = 123; Immediate addressing: is not supported for loads/stores Note However, immediate addressing can be emulated (see anon). 7

8 Sign Extension For words, half words and bytes: loads are sign extended [ unmatched bits in the target register are padded with copies of the most significant bit from the source Therefore: the appropriate twos-compliment [ sign and value is retained for both loads and stores 8

9 Sign Extension Examples Example lb with : Example lb with :

10 Unsigned Integer Loads lwu r1,64(r3) lhu r1,128(r4) lbu r1,256(r5) load unsigned word Mem[r2+64] load unsigned half word Mem[r2+128] load unsigned byte Mem[r2+256] Note Unmatched bits are 0 (no sign extension). 10

11 Integer Stores sd r1,32(r2) sw r1,64(r3) sh r1,128(r4) sb r1,256(r5) store double word to Mem[r2+32] store word to Mem[r3+64] store half word to Mem[r4+128] store byte to Mem[r5+256] Note Unmatched bits are discarded (which is correct for both signed data and unsigned data). 11

12 Note All loads and stores use: 16 bits of displacement (although we ll come nowhere near having to worry about that) 12

13 Summary Loads and stores: displacement addressing only direct and register indirect addressing via 0-valued address components b, h, w and d variants of all load/store operation (where necessary) Loads: signed loads with sign extension unsigned loads (lwu, etc) 13

14 Floating-Point Loads/Stores There are also: bit floating-point registers (always 64-bits) Load 64-bit floating-point value: l.d f1,1024(r2) Store 64-bit floating-point value: s.d f1,1024(r2) 14

15 Integer ALU Instructions Integer arithmetic instructions are: register-register or register-immediate 64-bit arithmetic signed and unsigned variants 15

16 Register-Register Integer Arithmetic dadd r1,r2,r3 dsub r1,r2,r3 dmul r1,r2,r3 ddiv r1,r2,r3 r1 = r2 + r3 r1 = r2 - r3 r1 = r2 * r3 r1 = r2 / r3 Note ddiv is integer division, remainders are discarded. 16

17 Unsigned Integer Arithmetic daddu r1,r2,r3 dsubu r1,r2,r3 dmulu r1,r2,r3 ddivu r1,r2,r3 r1 = r2 + r3 r1 = r2 - r3 r1 = r2 * r3 r1 = r2 / r3 17

18 Immediates daddi r1,r2,100 r1 = r daddi r1,r2,-1 r1 = r2-1 18

19 Immediate Addressing (for "loads") Load in immediate value into a register: int i = 123; daddi r1,r0,123 19

20 Logical Operations (Bitwise) and r1,r2,r3 or r1,r2,r3 xor r1,r2,r3 r1 = r2 and r3 r1 = r2 or r3 r1 = r2 xor r3 andi r1,r2,1 r1 = r2 and 1 ori r1,r2,1 r1 = r2 or 1 xori r1,r2,1 r1 = r2 xor 1 20

21 Logical Shifts Table 1. Logical shifts: dsll r1,r2,1 r1 = r2 << 1 dsrl r1,r2,3 r1 = r2 >> 3 Table 2. Logical shifts (by variable amounts): dsllv r1,r2,r3 dsrlv r1,r2,r3 r1 = r2 << r3 r1 = r2 >> r3 Table 3. Arithmetic right shifts (sign extended): dsra r1,r2,1 r1 = r2 << 1 dsrav r1,r2,r3 r1 = r2 >> r3 21

22 Examples Multiply r2 by 4, result in r1: dsll r1,r2,2 Multiply r2 by 3, result in r1: dsll r1,r2,1 dadd r1,r1,r2 Divide r2 by 2, result in r1: dsrl r1,r2,1 ; or... dsra r1,r2,1 ; if r2 is unsigned (or known positive) ; general arithmetic case 22

23 Aside Note Addition, subtraction and shift instructions require considerably fewer cycles than multiplication and division, even for integers. 23

24 Set a value (set conditions) Signed: slt r1,r2,r3 ; r1 = (r2 < r3)? 1 : 0 slti r1,r2,100 ; r1 = (r2 < 100)? 1 : 0 Unsigned: sltu r1,r2,r3 ; r1 = (r2 < r3)? 1 : 0 sltiu r1,r2,100 ; r1 = (r2 < 100)? 1 : 0 Note Often used immediately before a branch. 24

25 Branches and Jumps Branches conditional changes to the programme counter Jumps unconditional changes to the programme counter 25

26 Branches and Jumps Branches typically for and while loop conditions, if statements Jumps typically loops, also subroutine, function calls 26

27 Branches Branch on equality/inequality: beq r1,r2,1024 ; branch to 1024 if r1 equals r2 bne r1,r2,1024 ; branch to 1024 if r1 doesn't equals r2 Branch on zero/not zero: beqz r1,1024 ; branch to 1024 if r1 equals 0 bnez r1,1024 ; branch to 1024 if r1 doesn't equals 0 27

28 Branch Example Example: branch iff value in r1 is less than

29 Branch Example Example: branch iff value in r1 is less than 100 slti r2,r1,100 ; set r2 iff r1 < 100 bnez r2,1024 ; branch to 1024 if r2 is set 29

30 Branch Example If statement: if ( x == 3 ) {... } // rest... ; assume x is initially in r1 daddi r3,r0,3 ; load 3 into r3 bne r1,r3,rest ; if ( x == 3 ) {... ;... rest: ; }... ; // rest 30

31 Jumps Jumps are unconditional: j 1024 ; jump to immediate 1024 jr r20 ; jump to register r20 31

32 Jump and Link (function call) For function calls: jal 1024 ; jump to 1024 jalr r20 ; jump to r20 In both cases: leave the return address (PC+4) in r31 (in this regard, r31 is also a special-purpose register) 32

33 Branches and Jumps With fixed, 32-bit instructions: it makes no sense to branch/jump to an address which is not divisible by four so target addresses are shifted left by two bits (so multiplied by four) Note This happens transparently in assembly language (where target addresses are symbolic). 33

34 Example Write a MIPS program involving a loop to: sum the numbers from 1 to 100 leaving the result in r1 Note Note to self. See mips/sum-to-100-template.s. 34

35 Example.text main: daddi r1,r0,0 ; int s = 0; daddi r2,r0,1 ; int i = 1; daddi r3,r0,101 ; int N = 101; loop: ; beq r2,r3,done ; while ( i < N ) dadd r1,r1,r2 ; s += i; daddi r2,r2,1 ; i += 1; j loop ; } done: halt ; R1 now contains 5050 (= 0x13ba) 35

36 Done <script> (function() { var mathjax = 'mathjax/mathjax.js?config=asciimath'; // var mathjax = ' var element = document.createelement('script'); element.async = true; element.src = mathjax; element.type = 'text/javascript'; (document.getelementsbytagname('head')[0] document.body).appendchild(element); })(); </script> 36

CA226 Advanced Computer Architecture

CA226 Advanced Computer Architecture Stephen Blott Review of MIPS Instruction Set Table of Contents 1 2 Registers Memory Instructions r0 ; always 0 r1, r2,..., r31 ; general-purpose integer registers f0, f1, f2,...,