Test and Testability Techniques for Open Defects in RAM Address Decoders

Transcription

1 Test and Testability Techniques for Open Defects in RM ddress Decoders Manoj Sachdev WY 4.1; Philips Research Laboratories, Prof. Holst laan 4; 5656 Eindhoven; The Netherlands; bstract It is a prevalent assumption that all RM address decoder defects can be modelled as RM array faults influencing one or more RM cells. Therefore, can be implicitly detected by testing the RM matrix with the march tests. Recently, we came across some failures in embedded SRMs which were not detected by the march tests. The carried out analysis demonstrated the presence of open defects in address decoders that can not be modelled as the conventional coupling faults, therefore, are not detected by the march tests. In this article, we present the test and testability strategies for such hard-to-detect open defects. 1 Introduction Random ccess Memories (RMs) are often tested by carrying out so-called March Tests over all its addresses [1]. march test consists of individual march elements. march element traverses through all RM addresses and performs a specified combination of read and write operations. For example, in a typical march element, each RM address location is first read and then the complemented data value is written back. ll march elements put together should cover all likely faults in a given RM. ll likely RM faults are compiled into what is known as RM Fault Model. test algorithm is evolved which covers the given fault model. The overall complexity of the test algorithm is determined by the total number of memory operations in all march elements performed over any given RM address. The test complexity of march tests is linear with respect to the address space, hence, they are also referred as linear algorithms. Test algorithms, like 13N, 6N, 9N [2,3,4] are some of the examples of march tests. The conventional wisdom suggests that RM decoder defects can be mapped as RM array faults which can be tested by testing the array [5,6]. Hence, no special test is needed for the address decoders. However, recently we came across some open defects in RM address decoders that were not detected by linear test algorithms and resulted in field failures. This development prompted us to look into occurrence of open defects in RM address decoders. Open defects or transistor stuck-open faults are known to cause sequential behavior in MOS circuits and require a 2-pattern test sequence for their detection [7]. The transistor stuck-open testability has received a considerable attention [7,8,9]. number of DfT solutions for stuck-open testing has been proposed [8,9]. However, application of these solutions over RM decoders due to performance/ area constraints is not likely. Furthermore, such faults are not directly observable. One has to excite them in such a way that these faults are detected through read operation over the RM. Finally, owing to the constraints of addressing sequence, the detection of open defects by march tests is not ensured. ll these reasons put together, on one hand, render existing stuck-open DfT solutions for RM decoders impractical and on the other hand, make testing of such faults a new challenge. In this article, we examine the occurrence of open defects in RM address decoders and propose test and testability strategies for their detection. In the following section, a short review of the assumption of implicit RM address decoder testing is presented. In Section 3, we share the results of the conducted failure analysis over an embedded SRM failure and explain why such defects (faults) are not detected by march tests. Section 4 is devoted to open defects in a generic address decoder. test solution for hard-to-detect open defects is proposed. In Section 5, layout level DfT measures are proposed (i) to reduce the probability of occurrence of hard-to-detect open defects in address decoders, and (ii) to simplify their detection. Furthermore, logic level DfT measures are proposed that build fault tolerance in the address decoder. The decoder functions correctly in spite of hard-to-detect open defects. Finally, in the last section conclusions are drawn. 2 Previous work RMs enjoy a strategic position in the microelectronics industry. In many respects, RM testing is different from the testing of conventional logic. RMs are the largest and densest circuits produced. Small feature size and huge chip size result in an enormous critical area for defects [10]. High complexity and defect sensitivity have pushed the RM test costs to the extreme. To cope with the economic and qualitative issues, a variety of test solutions have been proposed. n interested reader is referred to [11,12] for an overview of RM test practices. vast majority of the research on RM testing was fo- ED&T /96 $ IEEE

2 cused on development of better, efficient test algorithms for a variety of fault models. These fault models included from simple Stuck-t Faults (SFs) to complex pattern sensitive faults in the RM array. However, little attention was paid to the faults in the address decoders or other RM building blocks. ddress decoder faults were assumed to be tested implicitly. n address decoder is a combinational circuit that selects a unique RM cell for each given RM address. ssuming that the faulty address decoder does not become sequential in operation, Thatte and braham [5] proposed that a faulty address decoder will behave in one of the following manners: The decoder will not access the addressed cell. In addition, it may access non-addressed cell(s) Wordline decoder olumn decoder 111 RM matrix The decoder will access multiple cells, including the addressed cell In the case of multiple access, the fault is viewed as RM matrix coupling fault between different cells. In the case of no access, the cell is viewed as either stuck-at 0 or stuck-at 1. In simple terms, decoder faults manifest themselves as RM matrix faults which are tested by the conventional algorithms. However, the above mentioned study was conducted over a NMOS decoder. The open defects in NMOS address decoders cause a logic stuck-at behavior. The same is not entirely true in the case of MOS address decoder. Therefore, those open defects which do not cause the stuck-at behavior escape the detection by the conventional tests. 3 Failure and nalysis The undetected faults in address decoders can be explained with the help of Fig. 1. The figure depicts a part of an embedded SRM block diagram, showing only the matrix and row and column decoders. n actual failure mechanism in an embedded SRM is illustrated with the help of three cells,,, and respectively. The addresses, (--0), of these cells are ; ; and respectively. The considered SRM has 256 addresses (8-bits) and word size is also 8-bit wide. Different bits are not close to each other, so there is no possibility of intra-word coupling faults. ddress bits,6,,4, and 3 decode the word lines and the rest of the bits select the column (or bit) line. ell is the cell that fails conditionally. Following are the symptoms of the failure as observed: 1. Write address ( ) with logic Write address ( ) with logic Read address : result is logic 1, which is correct. Observation: RM behaves normally, because address input 4 has changed. Fig. 1: graphical representation of the failure. 4. Write address ( ) with logic Read address : result is logic 0, which is wrong!! Observation: the failure occurs, because none of the address inputs 3, 4 or has changed. The read operation on cell yields wrong data value only if between write and read operations over cell, some address bits (,4 and 3) are kept unchanged. If any of these bits are changed, then the read operation over cell yields the expected data value. Furthermore, the fault is completely data independent. The failure does not write data into another cell, it seems to be a read only error. 3.1 nalysis From the above mentioned failure symptoms following deductions are made: 1. ll three cells have the same column address (111). 2. The cell yields a read failure when address bits,4,3 are kept unchanged. 3. The fault causes only the read failure in cell and do not influence other cells in any manner. 4. The fault is not detected by the 6N SRM test algorithm. The first deduction suggests that when cell is enabled after cell access, somehow cell is also enabled (or it is not disabled). ell is controlled by the corresponding wordline. onsider a situation when wordlines as well are enabled. If the complimentary data (cell ) is written into cell, the same is written in cell as well. Hence, a subsequent read operation on cell results in a read failure. The second deduction makes clear that it is not the

3 3 PHIX itline W RM cell itline DD Initial. March 1 March 2 0 Wr(0) R(0),W(1) R(1),W(0),R(0) 1 Wr(0) R(0),W(1) N-1 Wr(0) R(0),W(1) R(1),W(0),R(0) R(1),W(0),R(0) Open defect 6 W W Fig. 2: part of the wordline decoder and RM matrix. case with all cells on the same column. The cell is sensitive only when address bits,4, and 3 are not changed. The third deduction strengthens the first one stating only read on cell is affected by the defect mechanism. There are two possible explanations that match the above mentioned symptoms and deductions: (i) The wordline of cell is also enabled when wordline of cell is enabled, and (ii) The wordline of cell is not disabled when cell is enabled. The first possibility is very unlikely. However, it could be caused by (a) a decoder design error or by (b) a low resistive bridging fault between wordlines of cells and. The decoder design error is ruled out since a large number of devices should be failing under the test conditions. The low resistive bridging fault explanation also seems to be unlikely since, the fault should be bidirectional. Moreover, such a defect is a typical case of a decoder fault mapped onto the matrix coupling fault which should be detected by 6N test algorithm. Therefore, the possibility that wordline of cell is not disabled when cell is selected is the likely cause. The argument that cell is not disabled can be explained with the help of Fig. 2 which illustrates a part of the wordline address decoding logic and corresponding bitlines. Fig. 2 does not show the wordline drivers and input buffers. The wordline decoder has a 5-bit address. The address bits are buffered and their true and complement values are generated. The address decoding is achieved with the help of 4-input NND gates. Subsequently, 3-input NOR gates 6N Test lgorithm Fig. 3: The 6N SRM march test algorithm. decode the outputs of NND gates with address bit 6. periodic, timing signal, PHIX, forms the third input of these NOR gates. The outputs of these NOR gates are buffered to drive the wordlines. Let us assume for a moment that the NND gate in the wordline decoder which decodes cell has an open defect such that a p-channel transistor having as its input is disconnected from VDD. Now, let us once again try to repeat the experiment carried out earlier. It is very easy to notice that all the steps and observations can be re-created with the defect on cell. In a decoder constructed with NND gates, all logic high inputs cause n-channel transistors to be in conduction mode and hence enables the particular wordline. For example, 1111 on,,4,3 and 0 on 6 select the wordline corresponding to cell. However, the disabling on that particular path can take place by four (or depending upon the fan-in of the NND gate) paths. Supposing if one of the paths has an open defect, the wordline can not be pulled high (disabled) through that path. If the wordline is disabled through the faulty path (for example, by selecting cell ), two cells are selected at the same time. Therefore, a write operation over another selected cell is also performed over cell. Now, if a read is performed over cell, depending on the original stored data value and new data value, a fault is detected. However, if cell is accessed after cell a parallel p-channel path in the faulty NND gate is able to disable the corresponding wordline and the fault is not activated. The subsequent analysis demonstrated the transistor had a stuck-open fault. Such a fault can be caused by several defects. missing contact between Source (Drain) diffusion and Metal1 is the most likely cause. n open defect in the metalization layer, step coverage problem, defects causing transistor Stuck-Open fault are other possibilities. 3.2 Why Non-detection by March Tests The question is why the fault is not detected by the 6N march test and how should we detect such failures.the 6N test algorithm is shown in Fig. 3. It is a popular and time tested algorithm used within Philips for SRM testing [3].

4 First, the RM is initialized with logic 0. Subsequently, March1 reads the initialized value and writes logic 1 in each RM cell in ascending address order. The following binary address after wordline (address 10110) is 10111, which modifies the 3 bit. Hence, wordline is disabled like a fault-free case (Fig. 2). In other words, the fault is neither activated nor detected in March1. Similarly, the fault is not detected in March2. The March2 is in descending address order. fter the wordline is activated, the next wordline address (descending order, 10101) which modifies 4 and 3 bits. s a result wordline is disabled once again and the fault is not detected. This type of a fault can only be detected by a march test (or a linear algorithm), if the next wordline address causes the fault to be activated in at least one march direction, and keep it activated till it is detected by a read operation over the cell. Now, depending upon the original and over written data values, the defect can be detected. However, this condition can not be met for all such open defects in NND gates. Therefore, most of such defects are not detected by march tests. It can be further argued that no linear test will detect such defects since due to such defects, the address decoder is changed into a faulty sequential circuit which in general requires a two pattern test, namely fault sensitising and evaluation [7]. The basic assumption about the address decoders that under the faulty conditions, they remain combinational is violated. This is a generic problem with decoders implemented with static MOS logic gates. In the situations where decoders are implemented with dynamic logic (or NMOS) such faulty conditions may not arise. 4 Open Defects in ddress Decoders Linear algorithm will not detect such open defects in address decoders and even the non-linear (nlogn -- O(n 2 )) algorithms do not ensure decoder open fault detection. In fact, the RM test economics does not allow application of non-linear test algorithms [13]. significant effort is made to employ I DDQ based test methods to reduce RM test costs [14]. Furthermore, the rising quality demands expect effective testing of the Is. Therefore, to systematically detect decoder open faults, we outline a procedure below considering a generic address decoder. 4.1 Open Defects in an ddress Decoder Only a subset of all open defects in an address decoder are not detected by march tests. Hence, it is logical to analyse which of the open defects are not likely to be detected by the march tests and devise a test only for those open defects. For this purpose, we take a row decoder of an em PHIX 11 Fig. 4: typical wordline address decoder. WL63 WL62 WL61 WL60 WL03 WL02 WL01 WL00 bedded RM (Fig. 4). The decoder decodes a 6-bit address (10 -- ) to 64 wordlines. ddress bit 11 determines the selected quadrant and PHIX is a periodic timing signal which controls the timing of the wordline (X) address. In this decoder, instead of 4-input NND gates 32 5-input NND gates are utilized and the 6th bit () is further decoded by 64 2-input NOR gates. The open defects in an address decoder may occur either between the logic gates (inter-gate) or inside the logic gate (intra-gate). Defects 1, 2 in Fig. 4 are representative of the inter-gate class. The inter-gate open defects cause a break in an interconnect line. Owing to this class of defects, at least one RM cell can not be addressed, hence, appears to have a stuck-at fault [5,6]. In other words, inter-gate open defects do not cause sequential behavior and its impact is detected by march tests such as the 6N algorithm. However, intra-gate open defects (defects 3, 4) are difficult to detect because they may influence only a single transistor. Hence, may result in the sequential behavior. If an intra-gate open defect disconnects all paths between the output and VDD (VSS), it effectively causes an output S0 (S1) fault and is detected by the march test. However, if an open defect disconnects only one of the paths between the output and VDD (VSS), it causes the sequential behavior. Let us assume defect 3 causes a n-channel transistor in a 2- input NOR gate to be disconnected from VSS. Since, there is only one other n-channel transistor in parallel to the defective transistor, the defect will be detected either by the ascending march (March1) or the descending march (March2) in the address space depending which of the transistors is faulty. The condition of this detection is that

5 the inputs of the faulty gate should be changed in gray code manner. Therefore, in this case address bit 11 and decoded 10-- bits should change in the gray code manner. The situation becomes grave as the number of inputs in a gate rise to three or more. With the reasoning of the previous section, it can be concluded that detection of all open defects in a 3 (or more) input logic gate is not guaranteed by march test. s it can be observed in this particular example, that at least 3 open defects in each of the 5-input NND gates will not be detected (the other 2 open defects will be detected by descending or ascending march elements). There are 32 such NND gates in the decoder giving rise to 96 undetected faults. 4.2 Supplementary Test lgorithm small algorithmic loop is appended to the 6N algorithm to detect address decoder stuck-open faults. However, this algorithmic loop is specific to an address decoder and is independent of the 6N algorithm. Hence, it can be added to any other test algorithm. Let us assume that M is the number of input bits of the wordline decoder and the number of wordlines equals 2 M. To test the row decoding logic we have the freedom to select any arbitrary column address for read and write operations. In the following algorithm we set the column address to 0. s explained before the least significant bit (in Fig. 4, bit ) can be ignored and remains 0 during the test. To test for the hard-to-detect opens, the NND gates in the decoding logic should be tested in a sequential manner. For each NND gate a logic 0 is written to the selected cell (say D) by the corresponding wordline (remember that bit is set to 0). Subsequently, the wordline address is changed such that only one address bit is changed (let us say 6). This will allow the particular NND gate to be disabled by a particular p-channel transistor in the NND gate. Now, the logic 1 is written in the new address location (say E). If the above mentioned p-channel transistor had an open defect, the cell D is still enabled and the write operation over cell E can also over write the content in cell D. subsequent read operation over cell D will detect a read failure and hence the open defect. This is repeated for all address bits to NND gates and for all NND gates. For example, for the 5-input NND gate in Fig. 4 with defect 4 (shaded) following test sequence can be applied: 1a. Keep Y decoder address constant, 1b. keep =0 and 11 (if available)=0 2a. Let = 00000, Write(1); 2b = 00001, Write(0); 2c = 00000, Read(1); 2d = 00010, Write(0); 2e = 00000, Read(1); 2f = 00100, Write(0); 2g = 00000, Read(1); 2h = 01000, Write(0); 2i = 00000, Read(1); 2j = 10000, Write(0); 2k = 00000, Read(1); In general, an algorithm for a given address decoder can be evolved which can be supplemented to any RM test algorithm. For the address decoder in Fig. 4, an algorithm is shown below: In the algorithm description the address values in the read and write operations correspond to the binary code at the input bits of the wordline decoder (10986). The algorithm becomes: 1.0 olumn_address := For Xor_gate := 0 To 2 (M-1) Do 2.2 ase_address = 2 * Xor_gate 2.3 Write 0 to the address ase_address 2.4 For k := 0 To M Do Write_address := 2 * (Xor_gate XOR binary 2 k ) Write 1 to address Write_address Read 0 from address ase_address End For 2.5 End For s can be determined from the algorithm, the inner loop will be executed M-1 times for each Xor_gate and consists of one write and one read operation. The main loop will be executed 2 (M-1) times and takes one extra write operation. This makes a total complexity of the algorithm as (2M- 1)x2 (M-1) read or write operations, where M is the number of input bits of the wordline decoder. To compare the complexity of the algorithm given above with the 6N algorithm we will consider a RM having 6 bits devoted to the column decoding and another 6 bits to wordline decoding. The 6N algorithm will take 6 x2 12 = 24,576 read or write operations. The algorithm given above will only take 11 x2 5 = 352 read or write operations. So the additional test complexity is less than 2% of the 6N test. It can be argued that similar open defects in the column decoder can also cause hard to detect faults. olumn decoders can also be analysed and a similar test algorithm can be devised. 5 Testability Techniques for Decoder Open Defects In the previous section we discussed the test escape problem arising due to open defects in the RM address de-

6 VDD Diffusion 10 WL63 WL62 Poly 9 WL61 ontact 8 WL60 Metal D VSS Fig. 5: Layout transformation of a 4-input NND gate for open defect testability. D 6 WL03 WL02 coders and evolved a test procedure to test such test escapes. In this section, we focus on the layout level testability measures to simplify the detection of such hard to detect open defects and on building fault tolerance through logical modifications. Such measures are best implemented while designing new address decoders. If these simple yet effective measures are implemented, the requirement for additional test is either completely eliminated or drastically reduced. However, the existing decoders without such measures will require the extra test procedure as proposed previously. 5.1 Layout measures The layout is probably the simplest and most effective method to reduce the occurrence of such open defects. The layout of the circuit affects the testability to a great extent. Simple layout modifications may reduce the occurrence of hard-to-detect faults, hence, easing the test generation. For example, Placement of multiple contacts at hard-to-detect defect locations (parallel transistors) in the decoder will make them robust against open defects. These layout techniques are well documented in the literature [15,16]. There is a need to implement such techniques in future RM decoder designs because (i) the decoder circuitry is implicitly tested by testing only the matrix, (ii) the RMs are often tested by linear algorithms which restrict the excitation of the decoder in a particular fashion so as to cover the fault model in small number of operations, and (iii) quality and economic issues. The layout measures are explained with the help of Fig. 5. The figure illustrates a switch graph representation of a 4- input NND gate. This transformation is similar to the one proposed by Levitt and braham [16]. In the unmodified layout an open at a contact can happen at any branch of a set of parallel transistors or metal line. simple test may not detect such an open defect, and all the parallel branches must be tested separately. ssuming that open defect probability due to a poor contact is relatively high compared to open defect probability due to a break in diffusion, the modified layout results in robust layout as well PHIX as simpler test generation for open defects. It was reported [16] that though area as well as delay of the transformed gate may increase fractionally, the number of hard to detect faults are reduced drastically. 5.2 Logical measures: building fault tolerance WL01 WL00 11 Fig.6: fault tolerant row decoder against hard to detect open defects. The layout level techniques, in principle, can reduce the occurrence of open defects in sensitive decoder locations but can not eliminate their occurrence completely. Therefore, in this subsection we propose building some kind of fault tolerance in the key decoder locations such that in spite of such a defect, the decoder as well as the RM functions correctly. The fault tolerance can be used together with the layout level transformations to enhance the robustness of the decoder as well as building the fault tolerance. Fig. 6 illustrates the concept of logical measures. This figure is the same as Fig. 4 except for the highlighted areas, an inverter and an added net shown by the thick broken line. From the earlier reasoning, we conclude that opens affecting only single p-channel transistors in 5- input NND gates are hard-to-detect. The p-channel network in NND gates provide the disabling paths to the wordlines (since a particular wordline is selected if and only if the output of the corresponding NND gate is logic 0). Therefore, an extra p-channel transistor can be added in each of the 5-input NND gates such that it provides an alternative path for wordline disabling such that before application of a new address all NND gates are disabled. In other words, no wordline is selected. corresponding n- channel transistor is also added to avoid logical conflicts and effectively making it a 6-input NND gate. The modified NND gates are shaded in the figure. The inputs of

7 these transistors are driven by the PHIX signal which activates the wordline address. Effectively, PHIX now gates address bits instead of and 11 (see Fig. 4). The extra inverter is needed to invert timing signal PHIX. In a decoder where 5-input NOR gates are utilised instead of NND gates, the extra inverter is not needed. s far as the logical functioning of the decoder is concerned, it is not changed. The design of the decoder can be optimized for correct timing without sacrificing the gains through the concept. Furthermore, highlighted 3-input NOR gates are reduced to 2-input ones. 6 onclusion March tests are popular for testing RMs. The test complexity of march tests is linear with respect to RM address space. Thatte et al. [5] suggested that RM decoder faults can be mapped as the RM matrix coupling faults. Hence, no special test is needed for address decoders. Therefore, most of the RM test algorithms, including march tests, do not test address decoders explicitly. Recently, we found that the above mentioned assumption is not valid for a certain class of open defects in the address decoders. These defects were not detected by march tests and resulted in field rejects. Typically, such defects cause a sequential behavior of the decoder and require a 2- pattern test. Owing to the constraints of addressing sequence, the detection of open defects by march tests is not ensured. In this article, we examined the occurrence of open defects in RM address decoders and propose test and DfT strategies for their detection. Open defects in address decoders can be divided into two broad segments: (i) inter-gate open defects, and (ii) intra-gate open defects. rguably, all inter-gate open defects will cause a SF behavior in the addressed cell(s) and therefore will be detected by march tests. Some of the intra-gate open defects cause the gate to have a sequential behavior. Such defects are identified and an algorithmic test solution is proposed. This test solution is specific to the organization of the decoder and for a given decoder results in a 2% increase in the test time. s DfT measures, a layout level and a logic level solutions are proposed. The layout level measure reduces the probability of occurrence of hard-to-detect open defects in the address decoder. Furthermore, the detection of such open defects is simplified. s the logic level measure, we utilize the address decoder clock to break the address decoder s faulty sequential behavior. s a result, the modified address decoder functions correctly in spite of the open defects. These DfT measures allow us to continue testing RMs with march tests. However, these measures cost a small additional area. References [1] D. S. Suk, S. M. Reddy, March Test for Functional Faults in Semiconductor Random ccess Memories, IEEE Transactions on omputers, Vol. -30, no. 12, Dec. 1981, pp. [2] R. Dekker, F. eenker, L. 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