6/23/2011. Review: IEEE-754. CSE 2021: Computer Organization. Exercises. Examples. Shakil M. Khan (adapted from Profs. Roumani & Asif)

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1 6/23/2 CSE 22: Computer Orgniztion Lecture-8() Floting point computing (IEEE 754) Review: IEEE-754 single: 8 its doule: its single: 23 its doule: 52 its S Exponent Frction S x ( ) ( Frction) 2 (Exponent Bis) S: sign it ( non-negtive, negtive) Normlize significnd:. significnd < 2. leding pre-inry-point it represented implicitly significnd is frction with the. restored Shkil M. Khn (dpted from Profs. Roumni & Asif) Exponent: ctul exponent + Bis ensures exponent is unsigned single: is = 27; doule: is = 23 CSE-22 June single: x45c Exmples doule: x 42B8-5.2 single: xc doule: x C2E6666. single: x3a8326f doule: xd2fa9fc 3F5624D Exercises Represent 7.4 s flot Wht is the lrgest possile IEEE flot? How mny flots etween 64,5 nd 64,6? CSE-22 June CSE-22 June

2 Arithmetic Dt Trnsfer Conditionl Brnch 6/23/2 FP Support in MIPS Floting Point Registers Directives in.dt.flot nd.doule (note the lignment) Register Set seprte set of 32 regs, $f-$f3, with evenodd piring I/O System Clls Syscll 2,3 (print) nd 6,7 (red) Co-Processor the FP instruction suset Nme Exmple Comments 32 floting point registers ech is 32 its long $f - $f3 The following is the estlished register usge convention for the floting point registers: $f - $f3: Function-returned vlues $f4 - $f: Temporry vlues $f2 - $f5: Arguments pssed into function $f6 - $f9: More Temporry vlues $f2 - $f3: Sved vlues MIPS floting point registers re used in pirs for doule precision numers CSE-22 June CSE-22 June Floting Point Instructions () Floting Point Instructions (2) Ctegory Instruction Exmple Mening FP dd single dd.s $f2,$f4,$f6 $f2 $f4+$f6 FP sutrct single su.s $f2,$f4,$f6 $f2 $f4-$f6 FP multiply single mul.s $f2,$f4,$f6 $f2 $f4 $f6 FP divide single div.s $f2,$f4,$f6 $f2 $f4/$f6 FP dd doule dd.d $f2,$f4,$f6 $f2 $f4+$f6 FP sutrct doule su.d $f2,$f4,$f6 $f2 $f4-$f6 FP multiply doule mul.d $f2,$f4,$f6 $f2 $f4 $f6 FP divide doule div.d $f2,$f4,$f6 $f2 $f4/$f6 Ctegory Instruction Exmple Mening lod word copr. lwc $f2,($s2) $f2 Mem[$s2+] store word copr. swc $f2,($s2) Mem[$s2+] $f2 FP compre single (eq, ne, lt, le, gt, ge) FP compre doule (eq, ne, lt, le, gt, ge) Brnch on FP true ct 25 c.lt.s $f2,$f4 c.lt.d $f2,$f4 if($f2<$f4)cond =, else cond = if($f2<$f4)cond =, else cond = if cond== go to PC++4 Brnch on FP flse cf 25 if cond== go to PC++4 CSE-22 June CSE-22 June

3 6/23/2 Exercises Exmple Red flot; multiply it y 4; output As ove ut red from.dt As ove ut w/o using the FP mult As ove ut for doule # clc ult e re of ci rcle.dt Ans:.scii z "The re of th e ci rcle is: " Ans_d.word Ans d: # Poin ter to St ring (Ans ) Pi:.doul 3.45 e Rd:.doul e Rd_d.word Rd d: # Poin ter to fl ot (Rd).text min: lw $, ($) # lod dd ress of A ns in An s_dd to $ ddi $ v, $, 4 # Sys Cll 4 (P rint Stri ng) syscl l # # lod flo t (A ssem ler Inst ruct ion) l $s, Pi # lod dd ress of P i int o $s ldc $ f2, ($s ) # $f2 = Pi # lod flo # t (M IPS Instr ucti on) lw $s, R d_dd ($) # lod dd ress of R d in to $ s ldc $ f4, ($s ) # $f4 = R d mul.d $f2, $f4, $f 4 mul.d $f2, $f 2, $ f2 ddi $ v, $, 3 # Sys Cll 3 (P rint Dou le) syscl l exit: jr $r CSE-22 June CSE-22 June-23-2 CSE 22: Computer Orgniztion Lecture-8() Intro. to hrdwre, Boolen lger, Logic gtes Comintionl circuits (MUX, ALU) The Hrdwre Tril. From Ides to s nd s 2. The S/W H/W Interfce 3. Inside the CPU 4. How is it mde? Shkil M. Khn (dpted from Profs. Roumni & Asif) CSE-22 June

4 6/23/2 High Level Assemly High Level Assemly dd $t, $, $ The Softwre Tril CSE-22 June The Softwre Tril CSE-22 June Assemly Mchine Assemly Mchine dd $t, $, $ The Softwre Tril CSE-22 June The Softwre Tril CSE-22 June

5 6/23/2 Mchine Disk The Hrdwre Tril Executle File. From Ides to s nd s 2. The S/W H/W Interfce 3. Inside the CPU 4. How is it mde? The Softwre Tril CSE-22 June CSE-22 June Disk DRAM Disk DRAM Executle File Executle File Address Content Lirry File Lirry File Lunch, Link, nd Lod CSE-22 June Lunch, Link, nd Lod CSE-22 June

Send Content Send PC The Fetch-Decode-Execute Cycle CSE-22 June-23-2 2 CSE-22 June-23-2 22 Inside the CPU The CPU

6 6/23/2 DRAM CPU The Hrdwre Tril WAIT PC x43 x42c. From Ides to s nd s 2. The S/W H/W Interfce 3. Inside the CPU 4. How is it mde? Send Content Send PC The Fetch-Decode-Execute Cycle CSE-22 June CSE-22 June Inside the CPU The CPU circuits must e le to: look t the its coming from DRAM interpret the instruction nd then mke it hppen Execute Decode CSE-22 June dtpth REGISTER FILE control A L U The Fetch-Decode-Execute Cycle CSE-22 June

7 6/23/2 PC REGISTER FILE A L U The Fetch-Decode-Execute Cycle CSE-22 June The Hrdwre Tril. From Ides to s nd s 2. The S/W H/W Interfce 3. Inside the CPU 4. How is it mde? CSE-22 June How is it Mde? Peek elow Gtes CPU < dtpth + control > GATES < nd/or/not, nnd, nor > TRANSISTORS < mosfet > Cf. Lecure trnsistor switches semiconductors wfers, polished wfers ingot silicon (snd) SAND < silicon > CSE-22 June CSE-22 June

8 6/23/2 Logic Gtes: AND, OR Logic Gtes: NOT. AND Gte: c = 3. NOT Gte (Inverter): 2. OR Gte Symol c ( c ) Nottion Truth Tle c = + Symol c ( c, ) Nottion c Truth Tle Symol c ( c ) Nottion Truth Tle CSE-22 June CSE-22 June Universl Gtes Comintionl Circuits: XOR x y F Truth Tle x y F Truth Tle CSE-22 June z Does this circuit ehve like n XOR? How cn we prove / verify tht clim? CSE-22 June

9 6/23/2 Verilog Code Exercises module first; reg, ; wire lph, et; wire nota, notb; not mynot(nota, ); not mynot2(notb, ); nd upperand(lph,, notb); nd lowerand(et, nota, ); or finlor(z, lph, et); Cf. ls K N, textook Appendix C.4 progrms developed in clss Complete the verifiction using: hrd-coded inputs commnd-line inputs smpled inputs exhustive testing CSE-22 June CSE-22 June Comintionl Circuits: MUX s if ( s ), c ; else c ; s c c Nottion Truth Tle Symol Verify tht the following circuit functions s: C = (S == )? A : B Boolen Alger () Logic opertions/circuits cn e expressed in terms of logic equtions A B C AB AB To implement the ove digitl circuit, 2 AND, NOT nd OR gtes re required C Cn we simplify the ove circuit? CSE-22 June CSE-22 June

10 6/23/2 Boolen Alger (2) Boolen Alger (3) Expressions Identity Lw A + = A A = A Expressions Zero nd One Lw Inverse Lw Commuttive lw A + = A = A + Ā = A Ā = A + B = B + A A B = B A De Morgn s Lw ( A B) A B ( A B) A B Associtive Lw A + (B + C)= (A + B) + C A (B C) = (A B) C Distriutive Lw A (B + C) = (A B) + (A C) A + (B C) = (A + B) (A + C) CSE-22 June CSE-22 June Boolen Alger (4) Exercise : s implify the expressions: ( ) ( ) ( c) ( d) ( e) AB ABC ABC xyz xz ( x y)( x y) xy x( wz wz) ( BC AD)( AB CD) Exercise 2: implement s implified expressions for () (e) us ing O R, A ND, nd N OT gtes CSE-22 June

Today s Lecture. Basics of Logic Design: Boolean Algebra, Logic Gates. Recursive Example. Review: The C / C++ code. Recursive Example (Continued)

Today s Lecture. Basics of Logic Design: Boolean Algebra, Logic Gates. Recursive Example. Review: The C / C++ code. Recursive Example (Continued) Tod s Lecture Bsics of Logic Design: Boolen Alger, Logic Gtes Alvin R. Leeck CPS 4 Lecture 8 Homework #2 Due Ferur 3 Outline Review (sseml recursion) Building the uilding locks Logic Design Truth tles,