Associate Professor Electrical and Computer Engineering Old Main Hill, Logan, Utah

Transcription

1 Koushik Chakraborty Contact Information Associate Professor Electrical and Computer Engineering Utah State University 4120 Old Main Hill, Logan, Utah Research Interests VLSI Design and Automation, Circuit-Architectural Co-design. Education Ph.D., University of Wisconsin-Madison, August 2008 M.S., University of Wisconsin-Madison, May 2004 B.Tech., Indian Institute of Technology, Kanpur, India May 2000 Awards and Nominations Best Paper Award Nomination, 2014 ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS). Best Paper Award, 2012 IEEE International Conference on Computer Design (ICCD). Best Paper Award Nomination, 2011 IEEE/ACM Design Automation and Test in Europe (DATE). Best Paper Award Nomination, 2010 IEEE VLSI Design Conference (VLSID). Peer Reviewed Conference Publications C1. Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip Rajesh JayashankaraShridevi 1, Dean Michael Ancajas 1, Koushik Chakraborty, and Sanghamitra Roy IEEE/ACM International Symposium on Network-on-Chip, September Acceptance Rate: 23% C2. Tackling Voltage Emergencies in NoC Through Timing Error Resilience Rajesh JayashankaraShridevi, Dean Michael Ancajas 1, Koushik Chakraborty, and Sanghamitra Roy IEEE/ACM International Symposium on Low-Power Electronic Devices, August Regular Paper, Acceptance Rate: 18% C3. Opportunistic Turbo Execution in NTC: Exploiting the Paradigm Shift in Performance Bottlenecks Hu Chen 1, Dieudonne Manzi 1, Sanghamitra Roy, and Koushik Chakraborty ACM/IEEE Design Automation Conference (DAC), June Acceptance Rate: 21% C4. Tackling QoS-induced Aging in Exascale Systems Through Agile Path Selection Dean Michael Ancajas 1, Koushik Chakraborty, Sanghamitra Roy, and Jason Allred 1 IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis (CODES-ISSS), October Won Best Paper Award Nomination (3 out of 117 submissions: 2.56%) C5. Fort-NoCs: Mitigating the threat of a Compromised NoC Dean Michael Ancajas 1, Koushik Chakraborty, and Sanghamitra Roy, ACM/IEEE Design Automation Conference (DAC), June Acceptance Rate:22% C6. DARP:Dynamically Adaptable Resilient Pipeline Design in Microprocessors Hu Chen 1, Sanghamitra Roy, and Koushik Chakraborty ACM/IEEE Design Automation and Test in Europe (DATE), March Acceptance Rate: 23.1% (Regular Paper). 1 USU students.

2 C7. Exploiting Static and Dynamic Locality of Timing Errors in Robust L1 Cache Design Hu Chen 1, Sanghamitra Roy, and Koushik Chakraborty IEEE International Symposium on Quality Electronic Design (ISQED), pp. 9 15, March C8. A Global Router on GPU Architecture Yiding Han 1, Koushik Chakraborty, and Sanghamitra Roy IEEE International Conference on Computer Design (ICCD), October Acceptance Rate: 25.1% (Regular Paper). C9. Long Term Sustainability of Differentially Reliable Systems in the Dark Silicon Era Jason Allred 1, Sanghamitra Roy, and Koushik Chakraborty IEEE International Conference on Computer Design (ICCD), October Acceptance Rate: 25.1% (Regular Paper). C10. HCI Tolerant NoC Router Micro-architecture Dean Michael Ancajas 1, James McCabe Nickerson 1, Koushik Chakraborty, and Sanghamitra Roy, ACM/IEEE Design Automation Conference (DAC), Article 40, June Acceptance Rate:22% C11. Efficiently Tolerating Timing Violations in Pipelined Microprocessors Koushik Chakraborty, Brennan Cozzens 1, Sanghamitra Roy, and Dean Michael Ancajas 1 ACM/IEEE Design Automation Conference (DAC), Article 102, June Acceptance Rate:22% C12. DMR3D: Dynamic Memory Relocation in 3D Multicore Systems Dean Michael Ancajas 1, Koushik Chakraborty, and Sanghamitra Roy ACM/IEEE Design Automation Conference (DAC), Article 157, June Acceptance Rate:22% C13. Proactive Aging Management in Heterogeneous NoCs through a Criticality-driven Routing Approach Dean Michael Ancajas 1, Koushik Chakraborty, and Sanghamitra Roy ACM/IEEE Design Automation and Test in Europe (DATE), pp , 2013 Acceptance Rate: 24.5% C14. Mitigating NBTI in the Physical Register File through Stress Prediction Saurabh Kothawade 1, Dean Michael Ancajas 1, IEEE International Conference on Computer Design (ICCD), pp , October Won Best Paper Award (5 out of 246 submissions: 2%) C15. Designing for Dark Silicon: A Methodological Perspective in Energy Efficient Systems Jason Allred 1, Sanghamitra Roy, and Koushik Chakraborty ACM International Symposium on Low Power Electronics and Design (ISLPED), pp , July Acceptance Rate: 30.1% C16. Predicting Timing Violations Through Instruction Level Path Sensitization Analysis. IEEE/ACM Design Automation Conference (DAC), pp , June Acceptance Rate: 22%. C17. Towards Graceful Aging Degradation in NoCs Through an Adaptive Routing Algorithm. Kshitij Bhardwaj 1, Koushik Chakraborty, and Sanghamitra Roy IEEE/ACM Design Automation Conference (DAC), pp , June Acceptance Rate: 22%. C18. An MILP-Based Aging-Aware Routing Algorithm for NoCs Kshitij Bhardwaj 1, Koushik Chakraborty, and Sanghamitra Roy ACM/IEEE Design Automation and Test in Europe (DATE), pp , March 2012 Acceptance Rate: 27%.

3 C19. Power-Performance Yield Optimization for MPSoCs Using MILP Kshitij Bhardwaj 1, Sanghamitra Roy, and Koushik Chakraborty IEEE International Symposium on Quality Electronic Design (ISQED), pp , March 2012 C20. Process Variation Aware DRAM Design Using Block Based Adaptive Body Biasing Algorithm Satyajit Desai 1, Sanghamitra Roy, and Koushik Chakraborty IEEE International Symposium on Quality Electronic Design (ISQED), pp , March 2012 C21. Exploring High Throughput Computing Paradigm for Global Routing Yiding Han 1, Dean Michael Ancajas 1, ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2011, pp Acceptance Rate: 30% C22. Topologically Homogeneous Power-Performance Heterogeneous Multicore Systems. IEEE Design Automation and Test in Europe (DATE), pp. 1 6, March Won Best Paper Award Nomination (5 out of 789 submissions: 0.63%) Regular Paper Acceptance Rate: 25% C23. Optimizing Simulated Annealing on GPU: A Case Study with IC Floorplanning. Yiding Han 1, Sanghamitra Roy, and Koushik Chakraborty IEEE International Symposium on Quality Electronic Design (ISQED), pp. 1 7, March Regular Paper Acceptance Rate: 31.7%, DOI: /ISQED , C24. Analysis and Mitigation of NBTI Aging in Register File: An End-To-End Approach Saurabh Kothawade 1, Koushik Chakraborty, and Sanghamitra Roy IEEE International Symposium on Quality Electronic Design (ISQED), pp. 1 7, March Regular Paper Acceptance Rate: 31.7%, DOI: /ISQED C25. Integrated Circuit-Architectural Framework for PSN Aware Floorplanning in Microprocessors. Mandar Padmawar 1, Sanghamitra Roy, and Koushik Chakraborty IEEE International Symposium on Quality Electronic Design (ISQED), pp. 1 7, March 2011 Regular Paper Acceptance Rate: 31.7%, DOI: /ISQED C26. A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization Yiding Han 1, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala 1 IEEE/ACM 24th VLSI Design Conference (VLSID), pp , January 2011 Acceptance Rate: 20% (66 accepted out of 330 submissions). C27. Microarchitecture Aware Gate Sizing: A Framework for Circuit-Architectural Co-Optimization IEEE International Conference on Computer Design (ICCD), pp , October Regular Paper Acceptance Rate: 29.6%. C28. A Convex Optimization Framework for Leakage Aware Thermal Provisioning in 3D Multicore Architectures IEEE International Symposium on Quality Electronic Design (ISQED), pp , Regular Paper Acceptance Rate: 32.6%. C29. Re-thinking Threshold Voltage Assignment in 3D Multicore Designs. IEEE VLSI Design Conference (VLSID), pp , Won Best Paper Award Nomination (5 out of 320 submissions: 1.56%) C30. Mixed-Mode Multicore Reliability. Philip Wells, Koushik Chakraborty, Gurindar Sohi. IEEE/ACM International Conference on Architectural Support for Programming Languages

4 and Operating Systems (ASPLOS), pp , Acceptance Rate: 26%. C31. Adapting to Intermittent Faults in Multicore Systems. Philip Wells, Koushik Chakraborty, Gurindar Sohi. IEEE/ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp , Acceptance Rate: 24%. C32. Computation Spreading: Employing Hardware Migration to Specialize CMP Cores on-thefly. Koushik Chakraborty, Philip Wells, Gurindar Sohi. IEEE/ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp , Acceptance Rate: 24%. C33. Hardware Spin Management in Overcommitted Virtual Machines Philip Wells, Koushik Chakraborty, Gurindar Sohi. ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), pp , Journal Publications J1. Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm Dean M. Ancajas 1, Kshitij Bhardwaj, Koushik Chakraborty, and Sanghamitra Roy IEEE Transactions on Very Large Scale Integration Systems (TVLSI). DOI: /TVLSI J2. Dark Silicon Aware Multicore Systems: Employing Design Automation with Architectural Insight Jason Allred 1, IEEE Transactions on Very Large Scale Integration Systems (TVLSI). DOI: /TVLSI J3. Exploring High Throughput Computing Paradigm for Global Routing Yiding Han 1, Dean Michael Ancajas 1, Koushik Chakraborty, and Sanghamitra Roy IEEE Transactions on Very Large Scale Integration Systems (TVLSI). DOI: /TVLSI J4. Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No. 4, pp , April DOI: /TVLSI J5. Analysis and Mitigation of BTI Aging in Register File: An End-To-End Approach Saurabh Kothawade 1, and Koushik Chakraborty Elsevier Journal of Microelectronics Reliability (MR), Vol. 53, Issue 1, pp , January J6. Analysis of Intermittent Timing Fault Vulnerability Saurabh Kothawade 1, Koushik Chakraborty, Sanghamitra Roy, and Yiding Han 1 Elsevier Journal of Microelectronics Reliability (MR), Vol. 52, Issue 7, pp , July 2012 J7. Maximizing Energy Efficiency in 3D Multicore Systems: A Formalized Approach Taylor-Francis International Journal of Electronics (in press). DOI: /

5 J8. Stack Aware Threshold Voltage Assignment in 3D Multicore Designs. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 20, No. 3, pp , March J9. Supporting Overcommitted Virtual Machines Through Hardware Spin Detection. Koushik Chakraborty, Philip M. Wells, and Gurindar S. Sohi IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 23, No. 2, pp , February J10. Microprocessor Power Supply Noise Aware Floorplanning using a Circuit-Architectural Framework Mandar Padmavar 1, Sanghamitra Roy, and Koushik Chakraborty Journal of Low Power Electronics (JOLPE), Volume 7, Number 3, pp , August 2011, American Scientific Publishers. J11. Design and Implementation of a Throughput Optimized GPU Floorplanning Algorithm. Yiding Han 1, Koushik Chakraborty, Sanghamitra Roy, and Vilasita Kuntamukkala 1 ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16, Issue 3, No. 23, pp 23:1 23:21, J12. Exploiting Dynamic Micro-Architecture Usage in Gate Sizing. Microprocessors and Microsystems (MICPRO), Volume 35, pages , 2011, Elsevier Publishing. J13. A Novel Threshold Voltage Assignment for 3D Multicore Design. Journal of Low Power Electronics (JOLPE), Volume 6, Number 4, pp , October 2010, American Scientific Publishers. J14. Dynamic Heterogeneity and the Need for Multicore Virtualization. Philip Wells, Koushik Chakraborty, Gurindar Sohi ACM SIGOPS Operating System Reviews (OSR), Volume 43, Issue 2, pp (2009). Patents Aging-Aware Routing for NoCs Kshitij Bhardwaj, Koushik Chakraborty, and Sanghamitra Roy Patent Filed, No. 13/793,904, File Date: 3/11/2013. Predicting Timing Violations Through Instruction Level Path Sensitization Analysis. Patent Filed, No. 13/707,977, File Date: 12/7/2012. Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems Patent Allowed, No. 13/495,961, File Date: 6/13/2012. System and Method for Circuit Design Floorplanning Sanghamitra Roy, Koushik Chakraborty, and Yiding Han Patent Allowed, No. 13/013,654 File Date: 1/25/2011. Over-provisioned Multicore Processor Koushik Chakraborty, Philip Wells, Gurindar Sohi. US Patent No. 7,962,774 B2, Issued on 6/14/2011. Funding F1. TWC: Small: Understanding and Mitigating the Threat of a Malicious Network-on-Chip National Science Foundation (NSF), Sep 2014 Aug $516,000.0 Role: PI.

6 F2. CSR: Small: DARP: Promoting Energy Efficient System Design Through a Dynamically Adaptable Resilient Pipeline National Science Foundation (NSF), Oct 2014 Sep $441, Role: Co-I F3. SHF:Small:Boosting Sustainability in NoC Architectures through a Proactive Approach National Science Foundation (NSF), Sep 2013 Aug $515,948. Role: PI. F4. CSR:Small:Employing Design Automation to Build Foundations for Holistic Multicore Design National Science Foundation (NSF), Aug 2011 July $386,000. Role: Co-I. F5. Coupling Memory Controllers with Virtualization for High Performance 3D Systems (Extension) Micron Research Foundation, Jan 2011 Dec $255,000. Role: PI. F6. GPU-CAD: Floorplanning Using Throughput Computing Utah Science Technology and Research Initiative (USTAR), Jan 2010 Dec $ Role: Co-I. F7. High-Speed River Dynamics Modeling Using Graphics Processors. Utah Water Research Laboratory, July 2009 June $49,925. Role: PI. Technical Reports A Case for Over-provisioned Multicore Systems Koushik Chakraborty, Philip Wells, Gurindar Sohi Technical Report TR1607, University of Wisconsin-Madison, August Professional Activities Technical Program Committee, IEEE/ACM Design Automation and Test in Europe (DATE), Technical Program Committee, IEEE/ACM Asia-Pacific Design Automation Conference (ASP- DAC), 2015 Technical Program Committee, IEEE Real Time and Embedded Technology and Application Symposium (RTAS), 2014 Technical Program Committee, ACM International Symposium on Low Power Electronic Devices (ISLPED), 2014 Technical Program Committee, IEEE International Conference on Computer Design (ICCD), NSF panelist, Technical Program Committee, IEEE/ACM GLSVLSI Conference, Technical Program Committee, 24th IEEE/ACM VLSI Design Conference, 2011 Technical Program Committee, International Symposium on Electronic Design, 2010 Registration Chair, ACM Conference on Code Generation and Optimization, 2010 Technical Program Committee, 39th IEEE International Conference of Parallel Processing, 2010 Journal Reviewer: ACM Journal of Emerging Technologies, IEEE TPDS, IEEE TVLSI, IEEE TCAD, ACM TECS, ACM TODAES IEEE Design and Test of Computers, IEEE Transactions on Semiconductor Manufacturing External Reviewer: DAC , MICRO 2011, HPCA 2009, ISCA 2008, HPCA 2008, HPCA Professional Experience Utah State University, Logan, Utah Associate Professor, Electrical and Computer Engineering Utah State University, Logan, Utah July, 2014 present Assistant Professor, Electrical and Computer Engineering January, 2009 June 2014 nvidia Inc., Santa Clara, California Hardware Summer Intern May, 2007 August, 2007 Worked on performance optimization of next generation graphics processor. Intel Incorporation,

7 Hudson, Massachusetts Architecture Summer Intern May, 2004 August, 2004 Designed and implemented multi-threading in the performance model for a 8-core next generation multicore. Lucent Technologies, Murray Hill, New Jersey Member of Technical Staff-I, Bell Laboratories November, 2000 June, 2002 Designed and implemented several research prototypes covering system design aspects of database, network communication and security. Talks and Presentations Understanding and Mitigating Malicious Network-on-Chips, Invited Speaker, SaTC/SRC Kickoff event, Washington DC, January Predicting Timing Violation: A Circuit-Architectural Perspective on Robust System Design, Invited Speaker, Intel Hudson, July Predicting Timing Violation: A Circuit-Architectural Perspective on Robust System Design, Invited Speaker, AMD, July Fort-NoCs: Mitigating the threat of a Compromised NoC, DAC, June DARP:Dynamically Adaptable Resilient Pipeline Design in Microprocessors, DATE, March Timing Speculation for Approximate Computing, Invited Speaker, Approximate Computing Workshop organized by Intel, August Efficiently Tolerating Timing Violations in Pipelined Microprocessors, DAC, June Predicting Timing Violation: A Circuit-Architectural Perspective on Robust System Design, Invited Speaker, Intel Circuits Research Lab, May Proactive Aging Management in Heterogeneous NoCs through a Criticality-driven Routing Approach, DATE, March Towards Graceful Aging Degradation in NoCs Through an Adaptive Routing Algorithm, DAC, June Exploring High Throughput Computing Paradigm for Global Routing, ICCAD, November Integrated Circuit-Architectural Framework for PSN Aware Floorplanning in Microprocessors, ISQED, March Analysis and Mitigation of NBTI Aging in Register File: An End-To-End Approach, ISQED, March Flexible Computation Assignment in Multicore System, Invited Talk, Micron Inc., October Flexible Computation Assignment in Multicore System, Invited Talk, Brigham Young University, April Flexible Computation Assignment in Multicore System, Interview Talk at VMware, April Over-provisioned Multicore System, Invited Talk at VMware, September 2007 GPGPU: An Architect s Perspective, UW Architecture Seminar, March 2007 Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-the-fly, ASPLOS, October 2006 Computation Reassignment: Efficient Use of Multicore Systems, UW Architecture Affiliates, October 2006 Computation Spreading: Avoiding Code Duplication Overhead in CMPs, UW Architecture Affiliates, October 2005 Vector Processors: Past, Present and Future, UW Architecture Seminar, May 2004 Memory Degree of Use, UW Architecture Affiliates, October 2003 Departmental Service Computer Engineering Curriculum Modernization, Chair, Spring 2014-present Faculty Search Committee, Fall 2010-Spring 2011 Graduate Committee, Fall 2010-present Technician Search Committee, 2010 Faculty Search Committee, Spring 2010-Summer Current Students Dean M. Ancajas (Ph.D, expected Spring 2015) Chen Hu (Ph.D., co-advisor, expected Summer 2017)

8 Rajesh JayashankarShridevi (Ph.D., expected Summer 2017) Chidham R (Ph.D., co-advisor, expected Fall 2017) Prabal Basu (Ph.D., expected Spring 2018) Atif Yasin (Ph.D., co-advisor, expected Spring 2018) Dieudonne Manzi (M.S., co-advisor, expected Summer 2015) Kurt Brenning (M.S., expected Summer 2016) Shamik Saha (M.S., expected Summer 2016) Graduated Students Yidin Han (Ph.D, 2013, First Employment: Synopsys R&D) Saurabh Kothawade (M.S, Fall 2011, currently at QualComm) Vilasita Kuntamukkala (M.S. co-advisor, Summer 2011, currently at Intel) Kshitij Bhardwaj (M.S. Summer 2012, currently Ph.D. student at Columbia University) Satyajit Desai (M.S. co-advisor, Summer 2012, currently at Qualcomm) Jason Allred (M.S. co-advisor, Summer 2013, currently at Hill AirForce Base) Jacob Duston (M.S. Summer 2013, currently at Space Dynamics Lab) Brennan Cozzens (B.S. Spring 2013, currently pursuing M.S. at RPI) James McCabe Nickerson (B.S. Spring 2013) Brian Cluff (B.S, Spring 2014, co-advised with Prof. Sanghamitra Roy)