TTool/DIPLODOCUS: a UML Model-Driven Environment for Embedded Systems-on-Chip Design
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1 Institut Mines-Telecom Telecom ParisTech CNRS/LTCI Sophia Antipolis, France TTool/DIPLODOCUS: a UML Model-Driven Environment for Embedded Systems-on-Chip Design Andrea Enrici Ludovic Apvrille Renaud Pacalet MODELS 2014 Demonstration session
2 Research context: embedded Systems on Chip (SoCs) Embedded system = information processing systems embedded into a larger product, normally not directly perceivable by users 2/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
3 Research context: embedded Systems on Chip (SoCs) Embedded system = information processing systems embedded into a larger product, normally not directly perceivable by users System on Chip = software and hardware components working together to perform a predefined set of functions 2/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
4 Research context: embedded Systems on Chip (SoCs) Embedded system = information processing systems embedded into a larger product, normally not directly perceivable by users System on Chip = software and hardware components working together to perform a predefined set of functions We focus on: data-dominated embedded systems (e.g., signal, video processing) 2/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
5 Our Design Challenge Hardware/software partitioning: decide if a functionality should be implemented in hardware or in software or both Design Space Exploration is the solution! 2/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
6 Design Space Exploration (DSE) Design Space Exploration = analyzing different implementations, that are functionally equivalent, in order to find an optimal solution according to given performance criteria (e.g., costs, area, power consumption) 3/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
7 Motivation Embedded hardware has undergone a tremendous change: from single processor architectures to on-chip cloud computers with tens or hundreds of cores 4/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
8 Motivation Embedded hardware has undergone a tremendous change: from single processor architectures to on-chip cloud computers with tens or hundreds of cores so has done embedded software: from simple routines within control loops to applications with video conferencing and voice recognition 4/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
9 Motivation Embedded hardware has undergone a tremendous change: from single processor architectures to on-chip cloud computers with tens or hundreds of cores so has done embedded software: from simple routines within control loops to applications with video conferencing and voice recognition It is now impossible to design new products from scratch! 4/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
10 A toolkit named TTool (say tea-tool ) 5/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
11 TTool/DIPLODOCUS in a nutshell UML/SysML diagrams to model an embedded system s functionality, communication services and architecture 6/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
12 TTool/DIPLODOCUS in a nutshell UML/SysML diagrams to model an embedded system s functionality, communication services and architecture Simulate and verify formally the system s models at the push of a button 6/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
13 TTool/DIPLODOCUS in a nutshell UML/SysML diagrams to model an embedded system s functionality, communication services and architecture Simulate and verify formally the system s models at the push of a button No need to be an expert in modeling, simulation or formal verification 6/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
14 TTool/DIPLODOCUS in a nutshell UML/SysML diagrams to model an embedded system s functionality, communication services and architecture Simulate and verify formally the system s models at the push of a button No need to be an expert in modeling, simulation or formal verification Let s model a signal processing algorithm running on an embedded System-on-Chip! 6/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
15 High-level models... what for? Increase simulation speed the more models contain details, the longer are the simulation and verification 7/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
16 High-level models... what for? Increase simulation speed the more models contain details, the longer are the simulation and verification Reduce design and testing effort the earlier the bugs are found, the less it costs to fix them 7/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
17 High-level models... what for? Increase simulation speed the more models contain details, the longer are the simulation and verification Reduce design and testing effort the earlier the bugs are found, the less it costs to fix them Increase portability save time and money by re-adapting models for next projects 7/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
18 The Ψ-chart design methodology 8/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
19 The Ψ-chart design methodology Formal Verification Functional Simulation Functional Simulation Application modeling Communication modeling Architecture modeling The system s functionality is modeled independently of the architecture, it can be simulated and verified before mapping Mapping Design Space Exploration Formal Verification Functional Simulation 8/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
20 The Ψ-chart design methodology Formal Verification Functional Simulation Functional Simulation Application modeling Communication modeling Architecture modeling Mapping Design Space Exploration The available resources are modeled as a set of generic hw components: buses, memories, CPUs, etc. Formal Verification Functional Simulation 8/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
21 The Ψ-chart design methodology Formal Verification Functional Simulation Functional Simulation Application modeling Communication modeling Architecture modeling The communication services Mapping offered by the architecture are modeled and can be simulated before mapping Design Space Exploration Formal Verification Functional Simulation 8/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
22 The Ψ-chart design methodology Formal Verification Functional Simulation Functional Simulation Application modeling Communication modeling Architecture modeling The user selects the architecture resources that implement the functionalities of the application and communication models Mapping Design Space Exploration Formal Verification Functional Simulation 8/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
23 The Ψ-chart design methodology Formal Verification Functional Simulation Functional Simulation Application modeling Communication modeling Architecture modeling The design space is explored after mapping via functional simulation and formal verification (model-checking) Mapping Design Space Exploration Formal Verification Functional Simulation 8/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
24 Let s model with TTool/DIPLODOCUS! Let s model a signal processing algorithm that runs on an embedded System-on-Chip! 9/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
25 Let s model with TTool/DIPLODOCUS! Diagrams are drawn by dragging and dropping the modeling assets from the toolbars 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
26 Application modeling CWM1 CWM2 SOURCE ch1 CWS ACC Let's model first the processing operations interconnected by data dependencies (blue ports) SINK 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
27 Application modeling CONTROL CWM1 CWM2 SOURCE ch1 CWS ACC Then let's model a control operation and the control dependencies among the other operations (violet ports) SINK 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
28 Application modeling CONTROL CWM1 CWM2 SOURCE ch1 CWS ACC Applications are modeled as communicating tasks which are then mapped on hardware components SINK 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
29 Application modeling CONTROL CWM1 CWM2 SOURCE ch1 CWS ACC events are used to synchronize tasks' execution SINK 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
30 Application modeling CONTROL CWM1 CWM2 SOURCE ch1 CWS ACC requests serve as means to spawn other tasks SINK 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
31 Application modeling CONTROL CWM1 CWM2 SOURCE ch1 CWS ACC s model data exchanges between tasks SINK 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
32 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() an event is sent chl WriteSample(1) for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
33 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) a task is spawn for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
34 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) write a sample to a for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
35 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) loop for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
36 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) select between multiple execution paths for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
37 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess compute 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
38 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] wait for an event Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
39 Application modeling The behavior of each task is described by a state machine SendEvent() req SpawnTask() chl WriteSample(1) for(i=0;i<5;i = i+1) [guard_1 == true] [guard_2 == true] retrieve a sample from a Wait4Evt1() chl ReceiveSample(1) Wait4Evt2() SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
40 Application modeling The TTool/DIPLODOCUS abstraction principles: SendEvent() req SpawnTask() chl 1) only the amount WriteSample(1) of data exchanged between tasks is modeled. Data-dependent decisions are for(i=0;i<5;i = i+1) expressed by non-deterministic and static operators [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
41 Application modeling The TTool/DIPLODOCUS abstraction principles: SendEvent() req SpawnTask() chl 2) algorithms are described WriteSample(1) using abstract cost operators. The complexity of computations is taken for(i=0;i<5;i = i+1) into account without having to actually execute them [guard_1 == true] [guard_2 == true] Wait4Evt1() Wait4Evt2() chl ReceiveSample(1) SamplesToProcess 10/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
42 Architecture modeling An architecture model is a set of generic components <<CPURR>> FEP a CPU executes control and data processing tasks <<MEMORY>> main <<MEMORY>> FEP_MSS <<DMA>> DMA0 <<CPURR>> LEON FEP_Bus CROSS <<BRIDGE>> Bridge0 mainbus 11/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
43 Architecture modeling An architecture model is a set of generic components <<CPURR>> FEP a memory stores data and control information <<MEMORY>> main <<MEMORY>> FEP_MSS <<DMA>> DMA0 <<CPURR>> LEON FEP_Bus CROSS <<BRIDGE>> Bridge0 mainbus 11/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
44 Architecture modeling An architecture model is a set of generic components <<CPURR>> FEP a DMA transfers data and control information <<MEMORY>> main <<MEMORY>> FEP_MSS <<DMA>> DMA0 <<CPURR>> LEON FEP_Bus CROSS <<BRIDGE>> Bridge0 mainbus 11/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
45 Architecture modeling An architecture model is a set of generic components <<CPURR>> FEP a bus enables other hw components to communicate <<MEMORY>> main <<MEMORY>> FEP_MSS <<DMA>> DMA0 <<CPURR>> LEON FEP_Bus CROSS <<BRIDGE>> Bridge0 mainbus 11/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
46 Architecture modeling An architecture model is a set of generic components <<CPURR>> FEP a bridge enables two buses to communicate <<MEMORY>> main <<MEMORY>> FEP_MSS <<DMA>> DMA0 <<CPURR>> LEON FEP_Bus CROSS <<BRIDGE>> Bridge0 mainbus 11/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
47 Architecture modeling Each component is characterized by a set of performance parameters <<CPURR>> FEP A bridge enables two buses to communicate <<MEMORY>> main <<MEMORY>> FEP_MSS <<DMA>> DMA0 <<CPURR>> LEON FEP_Bus CROSS <<BRIDGE>> Bridge0 mainbus 11/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
48 Communication modeling Dedicated models (Communication Patterns) capture the communication services offered by embedded systems' interconnects SourceStorage ExecutionUnit CommunicationUnit DestinationStorage Read( 1 ) Read( 1 ) Transfer( sample ) Transfer( sample ) sample = sample - 1 Write( 1 ) Sequence Diagrams model message exchanges among generic resources that will be mapped onto the architecture 12/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
49 Communication modeling Activity Diagrams serve to compose Sequence Diagrams with control flows into a higher-level description sd Program Transfer1 sd Program Transfer2 [samples1 > 0] [samples1 == 0] [samples2 == 0] [samples2 > 0] sd Execute Transfer1 [ ] sd Acknow. Transfer1 sd Acknow. Transfer2 [ ] sd Execute Transfer2 12/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
50 Mapping Tasks are mapped on CPUs and hardware accelerators <<CPURR>> FEP Channels are mapped onto buses, bridges and memories HOC::Source <<MEMORY>> main <<MEMORY>> FEP_MSS <<CP>> 0 CP0::SampleCP FEP_Bus 0 <<DMA>> DMA0 <<CPURR>> LEON HOC::SINK CROSS <<BRIDGE>> Bridge0 mainbus 0 13/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
51 Mapping <<CPURR>> FEP HOC::Source Communication Patterns are mapped via dedicated artifacts <<MEMORY>> main <<MEMORY>> FEP_MSS <<CP>> 0 CP0::SampleCP FEP_Bus 0 <<DMA>> DMA0 <<CPURR>> LEON HOC::SINK CROSS <<BRIDGE>> Bridge0 mainbus 0 13/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
52 Functional Simulation <<CPURR>> FEP HOC::Source Simulation is started at the push of a button <<MEMORY>> main <<MEMORY>> FEP_MSS <<CP>> 0 CP0::SampleCP FEP_Bus 0 <<DMA>> DMA0 <<CPURR>> LEON HOC::SINK CROSS <<BRIDGE>> Bridge0 mainbus 0 14/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
53 Functional Simulation <<CPURR>> FEP HOC::Source <<MEMORY>> main <<MEMORY>> FEP_MSS <<CP>> CP0::SampleCP 0 FEP_Bus 0 <<DMA>> DMA0 <<CPURR>> LEON HOC::SINK <<BRIDGE>> CROSS Bridge0 The simulator GUI allows to easily 0 explore and debug a design while animating the diagrams mainbus 14/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
54 Formal Verification <<CPURR>> FEP HOC::Source <<MEMORY>> FEP_MSS The formal static analysis allows to prove certain properties. For example, check the reachability <<MEMORY>> main and liveness of a given operator <<CP>> CP0::SampleCP 0 FEP_Bus 0 <<DMA>> DMA0 <<CPURR>> LEON HOC::SINK CROSS <<BRIDGE>> Bridge0 mainbus 0 15/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
55 Formal Verification <<CPURR>> FEP HOC::Source <<MEMORY>> FEP_MSS FEP_Bus 0 CROSS 0 <<MEMORY>> main <<CP>> 0 CP0::SampleCP <<DMA>> DMA0 <<CPURR>> Model-checking properties LEON HOC::SINK are verified with UPPAAL and the formal semantics <<BRIDGE>> Bridge0 of LOTOS, at the mainbus push of a button 15/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
56 Debugging facilities Debugging and design exploration facilities are available from simulation and verification: Gantt charts execution waveforms reachability graphs 16/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
57 Summary An environment for the design of Systems-on-Chip: easy and rapid to deploy, open source 17/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
58 Summary An environment for the design of Systems-on-Chip: easy and rapid to deploy, open source used by industrial and academic partners... Texas Instruments Freescale ISAE (Toulouse, France) 18/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
59 Summary An environment for the design of Systems-on-Chip: easy and rapid to deploy, open source used by industrial and academic partners... Texas Instruments Freescale ISAE (Toulouse, France)... and projects EVITA (automotive embedded systems) Embb (Software-Defined Radio) 18/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
60 Future works and research directions Integrate model transformations: into a code generation environment to produce the application control code 19/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
61 Future works and research directions Integrate model transformations: into a code generation environment to produce the application control code into a run-time environment for application scheduling and memory management 19/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
62 Do you want to now more? Visit TTool s website: Contact us: andrea.enrici@telecom-paristech.fr ludovic.apvrille@telecom-paristech.fr renaud.pacalet@telecom-paristech.fr 20/20 Telecom ParisTech/COMELEC MODELS 2014 Demonstration session
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