Design Space Exploration of Systems-on-Chip: DIPLODOCUS

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1 Design Space Exploration of Systems-on-Chip: DIPLODOCUS Ludovic Apvrille Telecom ParisTech May, 2011

2 Outline Context Design Space Exploration Ludovic Apvrille DIPLODOCUS 2 of 27

3 Outline Context Design Space Exploration Context Design Space Exploration Ludovic Apvrille DIPLODOCUS 3 of 27

4 Systems-on-Chip Context Design Space Exploration A System-On-Chip = set of SW and HW components intended to perform a predefined set of functions for a given market Constraints Right market window Performance and costs Ludovic Apvrille DIPLODOCUS 4 of 27

5 Context Design Space Exploration Design Challenges Complexity Very high software complexity Very high hardware complexity Problem How to decide whether a function should be implemented in SW or in HW, or both? Solution Design Space Exploration! Ludovic Apvrille DIPLODOCUS 5 of 27

6 Context Design Space Exploration Design Space Exploration Design Space Exploration Analyzing various functionally equivalent implementation alternatives Find an optimal solution Important key design parameters Speed Power Consumption Silicon area Generation of heat Development effort Ludovic Apvrille DIPLODOCUS 6 of 27

7 Level of Abstraction Context Design Space Exploration Problematic Designers struggle with the complexity of today s circuits Cost of late re-engineering Right decisions should be taken as soon as possible... And quickly (time to market issue), and so, simulations must be fast System Level Design Space Exploration Reusable models, fast simulations / formal analysis, prototyping can start without all functions to be implemented But: high-level models must be closely defined so as to take the right decisions Ludovic Apvrille DIPLODOCUS 7 of 27

8 Outline Ludovic Apvrille DIPLODOCUS 8 of 27

9 DIPLODOCUS = UML Profile System-level Design Space Exploration Y- MARTE compliant Main features Data are abstracted Formal semantics Very fast simulation support Fully supported by an open-source toolkit Ludovic Apvrille DIPLODOCUS 9 of 27

10 The Y-Methododology Ludovic Apvrille DIPLODOCUS 10 of 27

11 Application Modeling Ludovic Apvrille DIPLODOCUS 11 of 27

12 Architecture Modeling Ludovic Apvrille DIPLODOCUS 12 of 27

13 Mapping Ludovic Apvrille DIPLODOCUS 13 of 27

14 Browsing the DIPLODOCUS Methododology Application structure Application behavior Formal verification Architecture model Mapping model Simulation Formal verification Ludovic Apvrille DIPLODOCUS 14 of 27

15 Application Structure (Smart Card system) Ludovic Apvrille DIPLODOCUS 15 of 27 Back to methodology

16 Application Behavior Figure: Activity Diagram of the SmartCard component Ludovic Apvrille DIPLODOCUS 16 of 27 Back to methodology

17 Formal Verification at Application Level No assumption on the underlying architecture All possible interleavings between actions are considered Formal verification is based on LOTOS or UPPAAL Press-button approach Ludovic Apvrille DIPLODOCUS 17 of 27 Back to methodology

18 Architecture Given in terms of parameterized nodes CPU, HWA, Bus, Memory, Bridge, etc. CPU parameters: scheduling policy, cache miss ratio, miss-branching prediction, pipeline size, etc. Ludovic Apvrille DIPLODOCUS 18 of 27 Back to methodology

19 Mapping Task are mapped on execution nodes (e.g., CPUs, HWAs) Channels are mapped on communication and storage nodes Ludovic Apvrille DIPLODOCUS 19 of 27 Back to methodology

20 After-Mapping Simulation Built-in simulator Extremly fast Diagram animation Step-by-step execution, breakpoints, etc. Ludovic Apvrille DIPLODOCUS 20 of 27 Back to methodology

21 After-Mapping Formal Verification built-in simulator can compute all possible execution paths Graph analysis and visualization Ludovic Apvrille DIPLODOCUS 21 of 27 Back to methodology

22 : Main Features Open-source UML toolkit Meant to support UML2 profiles 8 UML2 profiles are currently supported Mostly programmed in Java Editor, interfaces with external tools Simulators and model-checkers are programmed in C++ or SystemC Formal verification and simulation features Hides formal verification and simulation complexity to modelers Press-button approach Ludovic Apvrille DIPLODOCUS 22 of 27

23 Outline Ludovic Apvrille DIPLODOCUS 23 of 27

24 Outline Ludovic Apvrille DIPLODOCUS 24 of 27

25 Results Fully integrated environment for the fast design of Systems-on-Chip Based on UML Open-source toolkit Support Ludovic Apvrille DIPLODOCUS 25 of 27

26 A Few Case Studies... MPEG coders and decoders (Texas Instruments) LTE SoC (Freescale) Partitioning in vehicle embedded systems (EVITA project) Ludovic Apvrille DIPLODOCUS 26 of 27

27 To Go Further... and DIPLODOCUS ttool.telecom-paristech.fr Type UML under google And click on the I am lucky button! Ludovic Apvrille DIPLODOCUS 27 of 27

TTool/DIPLODOCUS: a UML Model-Driven Environment for Embedded Systems-on-Chip Design

Institut Mines-Telecom Telecom ParisTech CNRS/LTCI Sophia Antipolis, France TTool/DIPLODOCUS: a UML Model-Driven Environment for Embedded Systems-on-Chip Design Andrea Enrici Ludovic Apvrille Renaud Pacalet