Error-Correction Coding in CMOS RAM Resistant to the Effect of Single Nuclear Particles

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1 ISSN , Russian Microelectronics, 205, Vol. 44, No. 5, pp Pleiades Publishing, Ltd., 205. Original Russian Text K.A. Petrov, V.Ya. Stenin, 205, published in Mikroelektronika, 205, Vol. 44, No. 5, pp Correction Coding in CMOS RAM Resistant to the Effect of Single Nuclear Particles K. A. Petrov a and V. Ya. Stenin a, b a Scientific Research Institute for System Analysis, Russian Academy of Sciences, Nakhimovskii pr. 36, Moscow, 728 Russia b National Research Nuclear University MEPhI, Kashirskoe sh. 3, Moscow, 5409 Russia pertrovk@cs.niisi.ras.ru; vystenin@mephi.ru Received December 8, 204 Abstract Coders/decoders that are used in RAM to enhance the data storage reliability on exposure to single nuclear particles are analyzed. If the numbers of check bits are equal, a Hsiao decoder has a lower signal propagation delay than a decoder of the modified Hamming code. A decoder of the extended Hsiao code with additional check bits has the lowest delay among all decoders. When Hsiao decoders with units with a truncated correction circuit, a symmetrically simplified circuit for error calculation, and a circuit forming the error signal without the use of the error are used in RAM, the critical path lengths and the occupied chip area may be reduced if the detection of triple errors is excluded. The equal efficiency of Richter decoders and coders/decoders obtained through optimization based on genetic algorithms is substantiated for SEC- DAEC codes. DOI: 0.34/S INTRODUCTION The reliability of data storage in static CMOS RAM in the context of single-event upsets (SEUs) on exposure to nuclear particles is enhanced both by increasing the stability of the memory cells themselves [ 3] and by using the data word coding/decoding aids [2, 4]. As the geometric size of components is reduced, the probability of a memory cell upset is increased primarily due to an increase in the probability of multiple cell upsets (MCUs) on exposure to a single particle [5, 6] (in particular, a heavy ion [7]). This leads to a reduction in the reliability of operation of microprocessor VLSIs and systems based on them. The probability of MCUs in RAM in a single data word may be reduced by multiplexing the recording of adjacent bits of the data word into memory cells that are spatially distributed over the RAM chip [8]. Fault-tolerant DICE (dual interlocked storage cell) memory cells, which are traditionally designed by simple topology scaling [9, 0], have lost their advantage over standard CMOS 6T memory cells [, 2] in terms of soft error rates (SERs) and threshold charges as the geometric size was reduced from 80 to 32 nm. In the case of DICE CMOS memory cells with their resistance to the impact of individual nuclear particles being enhanced through the use of additional elements of storage of the logical cell state [2], the soft error rate of memory cells may be reduced by increasing the distance between the sensitive units of such cells. The larger the distance between the sensitive units of a device in the active silicon layer the lower the probability of multiple impact and upset. When increasing the distance between the sensitive nodes of a circuit (component), one should use nontraditional methods for designing the topology of such components [3, 4] and thus try to avoid using the chip area inefficiently. This is a high-cost (in terms of the occupied chip area) approach that is applicable primarily to highly reliable cache RAM with a relatively low data capacity. It is not possible to enhance the reliability of data storage in CMOS RAM without the use of redundant data coding when writing into RAM and decoding when reading out [2 4]. Therefore, it is of interest to validate the feasibility of methods and means used to design coders/decoders for CMOS RAM with small geometric sizes (sub-00 nm) that should reduce the probability of data loss in the event of faults in individual RAM memory cells, be characterized by low coding/decoding delays, and occupy the minimum possible RAM chip area. Linear block Hsiao codes [5, 6] are most commonly used to enhance the reliability of the data stored in RAM. -correction coding with a linear block code is performed using a coder and a decoder that are located at the data bus and introduce delays into the process of data writing and readout, thus altering the access time. Therefore, it is desirable to reduce the delays of signal conditioning in the coder and the decoder. The characteristics of coders/decoders are altered by changing the code test matrices [7 9] and by using ROM components in the decoder [20] to raise its operating speed. The reliability of coders/decoders depends on their resistance to upsets on exposure to individual nuclear particles [2]. 36

2 ERROR-CORRECTION CODING IN CMOS RAM RESISTANT 37 Signal propagation delay in the decoder, ns Number of check bits Modified Hamming Hsiao Hamming Multidimensional triangular Multidimensional rectangular Extended Hsiao Fig.. Characteristics of decoders used in RAM to correct single errors COMPARATIVE ANALYSIS OF CODERS/DECODERS THAT CORRECT SINGLE ERRORS Several error-correction codes used in RAM are known. Coders/decoders that are designed based on the test matrices of these codes differ in the signal propagation delay time and the number of needed check bits. Coders/decoders are designated in the present paper according to the algorithm of the used test matrix. The comparative analysis of coders/decoders of a 64-bit data word that correct single errors was conducted for coders/decoders that do not detect all double errors (Hamming coder/decoder, coder/decoder of the multidimensional rectangular code, and coder/decoder of the multidimensional triangular code) and for coders/decoders that detect all double errors (modified Hamming coder/decoder, Hsiao coder/decoder, and coder/decoder of the extended Hsiao code with additional check bits). The behavioral patterns of coders/decoders were modeled, and their topologies were synthesized in accordance with the 80 nm CMOS design rule. Figure shows the diagrams of the signal propagation delay in different versions of decoders (the values on the left axis) obtained as a result of synthesis and the needed number of check bits (the values on the right axis corresponding to the markers). The analysis of the obtained data showed that the decoders that do not detect all double errors had a lower signal propagation delay (at the minimum number of check bits) than the decoders that detect all double errors (see Fig. ). If the numbers of check bits were equal, a Hsiao decoder had a lower signal propagation delay than a decoder of the modified Hamming code. A decoder of the extended Hsiao code with additional check bits had the lowest delay among all decoders. It is impractical to use decoders of the multidimensional rectangular code and the modified Hamming code, since their analogs have better characteristics. 3. OPERATING SPEED AND HARDWARE SPECIFICS OF HSIAO DECODERS 3.. Hsiao Decoder Structure A Hsiao coder (see the Hsiao coder unit in Fig. 2) is based on XOR gates; the check bits are formed based on the data written into RAM (a data word of k data bits). When each check bit is formed, the data bits are chosen in accordance with the code test matrix. The check bits at the coder output are written into RAM at the address of the data bits and form an n-bit code word together with them. The error-correction Hsiao code is denoted as (n, k), where n is the code word size and k is the data word size (in bits). Figure 2 shows the function circuit of an (n, k) Hsiao decoder. The decoder converts the code word from the output RAM bus in the process of the data readout, producing error signals and the output data that are corrected if an error occurs within them. When the (a a n ) code word is read out from RAM, the check bits are calculated again with the help of the error calculation unit and are then compared bit-by-bit to the check bits that were read out from RAM. The result of this comparison (the error ) is used in shaping the error signals and is fed to the input of the error calculation unit (an incomplete (n k)-to-n decoder; see the DC unit in Fig. 2). The error produced at the DC decoder output screens the input data through bit-by-bit adding modulo 2 in the correction unit, thus correcting single errors in the code word. The error is also involved in the error signal generation. The (b b n ) code word corrected in the case of a single error and

3 38 PETROV, STENIN а calculation unit Correction unit b а k а k + b k b k + а n (n, k) Hsiao coder calculation unit signal generation unit n k n DC b n Uncorrectable error signal signal Fig. 2. Function circuit of an (n, k) Hsiao decoder. the signals of the presence of an error and an uncorrectable error are at the output of the decoder in Fig Decoder Components and Couplings Depending on the specified requirements, different versions of correction units, units calculating the error, and units shaping the error signals and different couplings between the components (error s and error s) may be used in the design of decoders. The correction unit circuit of an (n, k) Hsiao decoder may be either complete or truncated and contain either n or k two-input XOR gates. The complete correction circuit is shown in Fig. 2. An (n, k) Hsiao decoder with a truncated correction unit circuit is used if there is no need to transmit the check bits to the decoder output and is specific in that its output contains k bits (b b k ). A decoder with a truncated correction unit circuit may not be used in RAM if the corrected check bits are to be read out (e.g., when cascade decoding is used, when debugging a coder/decoder as a component of the memory subsystem, or when faults in RAM cells are analyzed). The error calculation unit that is capable of correcting the check bits produces an n-bit error. The diagram of the error calculation unit that calculates an n-bit error from k bits is a complete one (see Fig. 3a). The diagram of the error calculation unit may be simplified at the design stage [22]. Different versions of the error calculation unit for n = 8 and k = 4 are shown in Fig. 3. When there is no need to correct the check bits, the error for them should not be calculated. If this is the case, one may use the truncated diagram of the error calculation unit that produces an (n k)-bit error (see Fig. 3b). It is sufficient to use not (n k) bits, but (n k ) bits of the error to identify all single errors in an incomplete decoder that serves as the error calculation unit. Therefore, any row of the test matrix may be excluded. The uniqueness of each column is preserved in this case, and all single errors may thus be identified. The corresponding diagram of the error calculation unit [22] is regarded as the simplified one (see Fig. 3c). The capability requirements imposed on the unused output of the error calculation unit in a decoder with a simplified correction unit circuit differ from the requirements imposed on the other outputs. This results in an asymmetry in the decoder circuit and may lead to signal races. The asymmetry may be reduced [22] through the use of the symmetrically simplified circuit for error calculation (see Fig. 3d). This circuit has (n k) inputs, but forms each error bit using only those bits that are needed to define it uniquely. The unused bits are uniformly distributed over a equal number of components of the error calculation unit (and not like a single fixed one in a simplified circuit). Thus, the complete diagram of the error calculation unit for a (8, 4) Hsiao decoder is a 4-to-8 decoder (see Fig. 3a), the truncated one is a 4-to-4 decoder (see Fig. 3b), the simplified one is a 3-to-4 decoder (see Fig. 3c) made of three-input AND gates, and the symmetrically simplified one is a 4-to-4 decoder (see Fig. 3d) that, just as in the simplified circuit, is made of three-input AND gates. The diagram of the unit that generates error signals [22] may incorporate n- and (n k)-input NOR gates

4 ERROR-CORRECTION CODING IN CMOS RAM RESISTANT 39 (a) (b) (c) (d) Fig. 3. Different versions of the error calculation unit of a (8, 4) Hsiao decoder: (a) complete circuit, (b) truncated circuit, (c) simplified circuit, and (d) symmetrically simplified circuit. and a two-input AND gate (see Fig. 4a). This allows one to detect a fraction of triple errors thanks to the fact that the error is fed to the n-input NOR gate. This circuit requires an n-bit error. If there is no need to detect a fraction of triple errors, only the error may be used in the unit that generates error signals. This allows one to reduce the occupied chip area and the signal propagation delay in the error signal generation unit by using n k-input XOR gates instead of n-input NOR gates (see Fig. 4b) Comparison of Different Versions of a Hsiao Decoder Five versions of a Hsiao decoder were chosen for modeling, topology synthesis, and comparative analysis. The specific features of these versions are presented in Table. Verilog models of the decoder versions listed in Table were developed for data words with their length varying from 4 to 64 bits. Since the code and the test matrix of the models for each data word match, the numbers of check bits and detected double errors are also equal. Decoder version is specific in that it is capable of detecting a fraction of triple errors. The topologies of different decoder versions were synthesized using the Cadence Encounter CAD software in accordance with the 80 nm CMOS design rule. The dependences of the normalized signal propagation delays in different decoder versions on the data word size are shown in Fig. 5a. The normalized areas of topologies of different decoder versions for various data word sizes are shown in Fig. 5b. The parameters of decoder versions nos. 2 5 in Fig. 5 were normalized by the parameters of version no.. The relative advantages of different decoder versions over version no. in terms of the signal propagation delay (δ tdi (k)) and the area (δ Si (k)) may be estimated based on the modeling results presented in Fig. 5. The relative advantages in terms of the signal propagation delay δ tdi (k = 4) and the area δ Si (k = 4) are shown in Figs. 5a and 5b for decoder version no. 2 (with

5 320 PETROV, STENIN n n k (a) signal Uncorrectable n k error signal n k (b) signal Uncorrectable error signal Fig. 4. Different versions of the error signal generation unit of an (n, k) Hsiao decoder: (a) with the use of the error and (b) without the use of the error. parameter i = 2). The total relative advantage of version no. i for a data word with size k may be defined as δ i (k) = δ tdi (k) + δ Si (k), where i = 2, 3, 4, or 5 and k = 4, 8, 6, 32, or 64. The total relative advantage of version no. i averaged over a number of data word sizes k may be defined as δ AVi (m) = m Σδ i (k, m), where m is the number of different data word sizes over which the averaging is performed. The averaged total relative advantages of different decoder versions are listed in Table 2. Since the δ tdi (k) and δ Si (k) dependences for each decoder version behave oppositely at k 8 with maxima for δ tdi (k) and minima for δ Si (k), the values of δ tdi (k) and δ Si (k) deviate from the averaged δ AVi (m) value by not more than 7 20% for each decoder version. This allows one to use the averaged δ AVi (m) values as measures of the advantages of different decoder versions in terms of the above-indicated parameters. In the case of decoders of data words with their sizes ranging from 8 to 64 bit and with no detection of triple errors, decoder versions nos. 2, 3, 4, and 5 have an advantage of 8, 3, 4, and 42% over version no.. 4. CODERS/DECODERS FOR RAM WITH THE DETECTION OF DOUBLE ADJACENT ERRORS Coders/decoders of the linear block SEC-DED (single-error-correction-double-error-detection) code are used to enhance the resistance of RAM to faults and may detect a fraction of errors of orders higher than 2. The test matrix of this code may be transformed to correct double adjacent errors. In order to do that, the test matrix columns are rearranged in such a way that the total error s in any two adjacent bits do not match. As a result, the SEC-DAEC (single-error-correction-double-adjacent-error-correction) code is obtained. When this code is used, nonadjacent double errors may be corrected erroneously in the decoder if a nonexistent double adjacent error is mistakenly corrected instead of detecting a nonadjacent double error in the data read out from RAM. The noise immunity criterion is one of the basic parameters of SEC- DAEC coders/decoders. This criterion defines the percentage of erroneous correction of nonadjacent double errors; its value should be lowered in order to improve the noise immunity of a coder/decoder. There are several ways to obtain test matrices of SEC-DAEC codes by optimizing test matrices of Hsiao codes with the use of heuristic algorithms of various degrees of complexity. Dutta SEC-DAEC codes [23] obtained using a pseudo-greedy heuristic algorithm and Richter SEC-DAEC codes [24] derived using a random iterative heuristic algorithm from Hsiao codes with the highest probability of detection of triple errors are known. Since it is difficult to implement complete enumeration of all possible versions of the test matrix (there are about 0 6 of them), Dutta and Richter codes were obtained using incomplete enumeration algorithms. In order to investigate the Table. Hsiao decoder versions Version no. Correction mode, number of outputs calculation unit signal generation unit Correction of any code word bit; n outputs Complete circuit (see Fig. 3a) is used; a fraction of triple errors is detected (see Fig. 4a) 2 Correction of only the data bits; n outputs Complete circuit (see Fig. 3a) is not used (see Fig. 4b) 3 Correction of only the data bits; k outputs Truncated circuit (see Fig. 3b) is not used (see Fig. 4b) 4 Correction of only the data bits; k outputs Simplified circuit (see Fig. 3c) is not used (see Fig. 4b) 5 Correction of only the data bits; Symmetrically simplified circuit is not used k outputs (see Fig. 3d) (see Fig. 4b)

6 ERROR-CORRECTION CODING IN CMOS RAM RESISTANT 32 t Di /t D δ td2 (k = 4) 3 (a) i 4 2 S i /S (b) i δ S2 (k = 4) bits 8 bits 6 bits 32 bits 64 bits bits 8 bits 6 bits 32 bits 64 bits Fig. 5. Dependences of (a) the normalized signal propagation delays and (b) the normalized decoder areas of different Hsiao decoder versions on the data word size. possibility of obtaining test matrices of more noiseresistant SEC-DAEC code versions for 32-bit and 64- bit data words, we tried to optimize test matrices of the Hsiao code using a more complex heuristic algorithm (genetic algorithm) and compared the results with Dutta and Richter coders. Coders/decoders based on test SEC-DAEC codes were compared in their conversion delay (operating speed) characterized by the maximum number of ones in the test matrix row and in their error-correcting capability characterized by the probability of erroneous correction of double errors (the lower the probability of erroneous correction the higher the error-correcting capability). Since the hardware redundancy required to implement each of these coders/decoders is characterized primarily by the number of check bits, the coders/ decoders may be considered equal in these terms. The characteristics of coders/decoders of Dutta and Richter codes and the code optimized with a genetic algorithm are compared in Fig. 6 for 32-bit and 64-bit data words. Figure 6 shows the diagrams of normalized signal propagation delays, which are characterized by the maximum number of delays in the test matrix row (the values at the left axis) and were obtained as a result of modeling, and the probabilities of erroneous correction of double errors by the mentioned decoders (the values on the right vertical axis corresponding to the markers). It follows from the obtained data (see the dependences in Fig. 6) that the derivation of test matrices of SEC-DAEC codes with genetic algorithms allows one to obtain coders/decoders that detect more nonadjacent double errors than Dutta decoders. The probability of erroneous correction of double errors was reduced from 53 (for Dutta decoders) to 35%, although the advantage over Richter decoders was marginal. This suggests that both Richter codes and the codes obtained with the help of genetic algorithms may be used with great efficiency in practice. 5. RESULTS OF SIMULATION AND ANALYSIS OF VERSIONS OF CODERS/DECODERS The comparative analysis of characteristics of coders/decoders of a 64-bit data word that correct single errors was conducted by modeling the behavioral patterns of coders/decoders and synthesizing their topologies in accordance with the 80 nm CMOS design rule and revealed the following points: () The decoders that do not detect all double errors had a lower signal propagation delay (at the minimum number of check bits) than the decoders that detect all double errors. (2) If the numbers of check bits were equal, a Hsiao decoder had a lower signal propagation delay than a decoder of the modified Hamming code. (3) A decoder of the extended Hsiao code with additional check bits had the lowest signal propagation delay among all the considered decoders. Table 2. Averaged relative advantages of different decoder versions Decoder version no Value averaged over all five data word sizes, δ AVi (m = 5) Value averaged over four data word sizes k = 8; 6; 32; and 64, δ AVi (m = 4)

7 322 PETROV, STENIN Dutta code Richter code Optimized code 0 (39, 32): Maximum number of ones in a row of the test matrix (72, 64): Maximum number of ones in a row of the test matrix (39, 32): Probability of erroneous correction of double errors, % (72, 64): Probability of erroneous correction of double errors, % Fig. 6. Characteristics of SEC-DAEC coders/decoders for 32-bit and 64-bit data words. (4) It is impractical to use the decoders of the multidimensional rectangular code and the modified Hamming code to enhance the resistance of RAM to faults, since their analogues have better characteristics. The signal propagation delay in a Hsiao decoder may be reduced by using the following methods: (i) a truncated correction unit circuit with no correction of check bits; (ii) a symmetrically simplified circuit of the error calculation unit where the error bits are used to define uniquely each error bit and no error of check bits is generated; and (iii) a unit that generates error signals without the use of the error (logic XNOR of the error bits is calculated instead of logic NAND of the error bits). Decoder versions (with diagrams of the correction unit, the error calculation unit, and the error signal generation unit) with a reduced number of logic gates were proposed following the analysis. The use of these components allows one to reduce the signal propagation delays in Hsiao decoders and the chip area occupied by a decoder for data words with their length varying from 4 to 64 bits in the case when the detection of triple errors is excluded. If no triple errors are detected, different decoder versions for data words with their length varying from 6 to 64 bits have an advantage of 8 42% over a Hsiao decoder with a complete diagram of the error calculation unit and the error signal generation unit where the error is used to detect a fraction of triple errors. After (72, 64) coders/decoders of the modified Hamming code were substituted with the designed (28, 8) and (72, 64) Hsiao coders/decoders in VLSI cache RAM, the critical path lengths and the total chip area occupied by coders/decoders were reduced by 9 and 36%, respectively (regardless of the fact that the number of coders/decoders was raised from 8 to 4 due to a change in the cache RAM architecture). The test matrices of SEC-DAEC codes derived through optimization with genetic algorithms allowed us to design coders/decoders that detect more nonadjacent double errors than Dutta decoders. The probability of the erroneous correction of double errors was reduced from 53 (for Dutta decoders) to 35%, although the advantage over Richter decoders was marginal. This suggests that Richter coders/decoders and the coders/decoders obtained through optimization with genetic algorithms may be used with equal efficiency in practice. CONCLUSIONS Coders/decoders that are used in RAM to enhance the data storage reliability on exposure to single nuclear particles were analyzed. If the numbers of check bits were equal, a Hsiao decoder had a lower signal propagation delay than a decoder of the modified Hamming code. A decoder of the extended Hsiao code with additional check bits had the lowest signal propagation delay among all the considered decoders. When Hsiao decoders with units with a truncated correction circuit, a symmetrically simplified circuit for

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