BOOST YOUR DESIGNS TO A NEW LEVEL OF ACCURACY AND CONFIDENCE WITH VERILOG-A

Transcription

1 BOOST YOUR DESIGNS TO A NEW LEVEL OF ACCURACY AND CONFIDENCE WITH VERILOG-A NICOLAS WILLIAMS, PRODUCT MARKETING MANAGER, MENTOR GRAPHICS JEFF MILLER, PRODUCT MARKETING MANAGER, MENTOR GRAPHICS A M S D E S I G N A N D V E R I F I C A T I O N W H I T E P A P E R w w w. m e n t o r. c o m

2 INTRODUCTION With Verilog-A, designers can be more productive and accurate. Verilog-A allows you to enhance your simulations so that you can: Perform behavioral modeling for faster runtimes and early system level simulations. Conduct special checks and measurements such as safe operating area checks. Create complex input stimuli. Create models of non-standard devices such as MEMS, image sensors, or TFTs. BEHAVIORAL MODELING Analog design traditionally uses a bottom up design methodology. This approach can result in costly extra effort if system integration issues are found late in the design cycle. Benefits: Run system level simulations early in the design cycle to find integration issues and minimize redesigns late in the design cycle Perform special measurements such as DNL, INL, and relative settling time Run Safe Operating Area checks during simulation, including whether a voltage is in range or if a device is operating in the specified region Mix and match device level and behavioral representations of the blocks for faster run times Easily create complex input stimuli such as random signals, pseudorandom bit streams, and signals that are clipped, non-linearly compressed, or sampled Create your own models for unusual devices such as TFTs, Image Sensors, Solar Cells, Thyristors, or MEMS devices using a simple and efficient language for describing device behavior Figure 1: Traditional bottom up methodology in analog design can result in costly extra effort. 2 of 10

3 Verilog-A enables a top down approach to circuit design that encourages early system level simulations to verify interface and integration issues. The designer creates behavioral models for each major block of the design and then starts performing system level simulations to make sure blocks will interface correctly. After system level design is complete, the individual blocks are designed at the device level. Then, each block s behavioral model is calibrated based on the detailed design. The calibrated behavioral models can be used as initial models for system level simulation of the next design. Figure 2: Verilog-A enables top down design and helps verify interface and integration issues at an early stage. Another reason to use Verilog-A for creating behavioral models is to allow co-simulation between behavioral blocks and device level analog netlists to speed up simulations and shorten design cycles. When designing a PLL, you can mix and match behavioral and device level representations of the blocks to achieve the accuracy and runtimes you need. Figure 3: PLL block diagram. 3 of 10

4 Below is a table of simulation runtimes for a PLL where each block has a behavioral and device level representation. The simulation runtimes were measured with different combinations of block representations. This allows designers to focus on block level design while still being able to perform system level simulations without lengthy runtimes. Figure 4: PLL simulation runtimes. Designers can quickly create complex behavioral models by using either mathematical equations or transfer functions. You can create an FM modulator with just three lines of code. Figure 5: Verilog-A FM modulation code; FM modulation of a digital signal. Verilog-A is especially helpful in modeling mixed signal blocks. A quadrature phase-shift keying (QPSK) modulator can be constructed in about 10 lines of code and runs more than 20 times faster than a full SPICE representation. 4 of 10

5 Figure 6: QPSK modulation of a digital signal; Verilog-A QPSK modulator code. 5 of 10

6 You can easily specify transfer functions in both the s domain and z domain using the laplace_xx and zi_xx functions in Verilog A. A digital 4th order low pass 3-db ripple Chebyshev filter can be described with one line of code. Figure 7: Verilog-A code for a 4th order low pass 3-db ripple Chebyshev filter; input and output signals for a 4th order low pass 3-db ripple Chebyshev filter. 6 of 10

7 SAFE OPERATING AREA Verilog-A also expands the toolbox of your designers, allowing them to catch design errors much earlier in the design cycle. With Verilog-A, you can perform special checks such as Safe Operating Area (SOA) checks. You can monitor voltages during simulations and issue warnings if a node s or pin s voltage is out of safe operating range. This is useful in making sure the input voltage to an ADC is within the range it can convert. You can even check if a voltage goes above a specific voltage for more than a specific time. Monitoring voltages is helpful when you are making sure the gate to source voltage stays in the range that the model is valid. Figure 8: Simulation results of voltage exceeding a specific limit. Designers can also set the operating region for specific MOSFETs and use Verilog-A to warn if these devices are not operating in the specified region such as the linear or saturation region. The compact models with Verilog-A can be modified to include any range of SOA checks. SPECIAL MEASUREMENTS Designers often need to perform complex measurements that are not possible using the.measure command in SPICE. Verilog-A allows you to measure very complex circuit character istics, including differential and integral nonlinearity (DNL /INL) for ADC and DACs, relative settling time if you don t know the ending steady state value, and jitter measurements for PLLs. 7 of 10

8 COMPLEX INPUT STIMULI Figure 9: Relative settling time measurement result. You can easily create an input stimulus that would be difficult or impossible to create with SPICE. You can inject a random signal into the circuit and check how well the design responds to noise. Figure 10: SPICE deck & Verilog-A code to add random noise to signal. 8 of 10

9 Figure 11: Signals with random noise. You can generate a pseudo-random bit stream, or signals that are clipped or have been nonlinearly compressed. You can also create sampled data based on different sampling rates or schemes. Figure 12: The main signal and different sampled results using Verilog-A. 9 of 10

10 MODEL DEVELOPMENT If you need to create your own models for an exotic device such as a TFT, solar cell, Thyristor, LDMOS, Image Sensor, or MEMS device, then Verilog-A gives you an efficient language for describing device behavior. Many standard models such as EKV 3.0, BSIM3.3, and BSIM3.4 are already available in Verilog-A format. You can modify and extend existing models such as diode models to include ESD and snapback effects. Some foundries will be soon shipping Verilog-A models for non-standard devices that do not simulate well as subcircuits using combinations of SPICE built-in devices. Verilog A provides a standard, high level language for the modeling of device behavior which is portable across simulators. For the latest product information, call us or visit: w w w. m e n t o r. c o m 2015 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners. MGC 7-15 TECH13140-w