A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for Improved Clock Data Compensation Featuring a Deep Trench Capacitor Based Loop Filter

Transcription

1 A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for Improved Clock Data Compensation Featuring a Deep Trench Capacitor Based Loop Filter Bongjin Kim, Weichao Xu, and Chris H. Kim University of Minnesota, Minneapolis, MN kimx2447@umn.edu Symposia on VLSI Technology and Circuits

2 Outline Resonant Supply Noise Issue Introduction to Clock Data Compensation Proposed 32nm Supply-Noise Tracking PLL Deep Trench Capacitor Based Loop Filter PLL Test Chip Measured Data Summary Slide 1

3 Resonant Supply Noise Basics [1] N. Kurd et al., JSSC 2009 Resonance between package/bonding inductance and on-die decoupling capacitance Typical resonant frequency : MHz Typical resonant noise amplitude : ~10% Slide 2

4 Clock Data Compensation (CDC) Clock period modulated by resonant noise Performance loss partially alleviated by intrinsic CDC Optimal CDC: Make CLKo period track datapath delay Slide 3

5 Techniques for Enhancing CDC Key control parameters : Clockpath supply, PLL output clock (CLKi) period Slide 4

6 Optimizing CDC with Adaptive PLL VDD VDD PLL CLKi... Clockpath CLKo Data path Conv. PLL (Constant CLKi period) Adaptive PLL (Variable CLKi period) VDD CLKi period CLKo Data P P P F F F P P P P P P P P P P P P PP PP P P P: Pass / F: Fail Adaptive PLL achieves optimal CDC by modulating the CLKi period using the supply noise Slide 5

7 Existing PLLs for Enhancing CDC [1] N. Kurd et al., JSSC 2009 [2] D. Jiao et al., ISSCC 2011 Prior works: open-loop, one-time programmable Proposed work: closed-loop, real-time PVT tracking Slide 6

8 Clockpath and Datapath Timing Models Datapath delay: Proportional to supply voltage Clockpath delay: Must account for the delay difference between two consecutive clock edges Slide 7

9 Deriving Optimal CDC Condition Using Timing Models CLKi period Delay D(t) CLKo period A: PLL sensitivity B: Clockpath sensitivity d/dt t ( )dt t-d(t) Supply noise = -sin(t) when A=B By making A = B using an adaptive PLL - CLKo period becomes independent of D(t) - CLKo period is perfectly aligned with datapath delay optimal CDC Slide 8

10 Comparison with Prior Art Slide 9

11 Effectiveness of PVT Tracking Slide 10

12 Proposed Supply-Noise Tracking PLL Ref. CLK CLKi Slide 11

13 Conventional CP PLL & Clockpath Ref. CLK VBN VBP Slide 12

14 Supply-Noise Sensitivity Tracking Loop CDC modulator EN[62:0] Binary to therm. Counter Digital filter Tunable critical path bit error monitor CLKo VBN Sensitivity tracking loop PFD UP DN VC Diff. VCO CLKi M U X CP Feedback CLK LF VCO bias gen. PLL freq. divider Various clockpaths Digital supply: VDD Slide 13

15 CDC Modulator & Tunable ERR Monitor Sensitivity=C u /(C u +C d ) VDD VDD RST C u C EN[0] C EN[1] VBN C EN[62] ERR CLKo Tunable delay C d EN[0] C EN[1] C C EN[62] Datapath CLKo CDC modulator EN[62:0] Binary to therm. Counter Digital filter ERR Tunable critical path bit error monitor CLKo VBN Sensitivity tracking loop Ref. CLK PFD UP DN VC VBP VBN Diff. VCO CLKi M U X CP Feedback CLK LF VCO bias gen. PLL freq. divider Various clockpaths Digital supply: VDD Slide 14

16 Tracking Loop Transient Response Slide 15

17 Deep Trench Capacitor G. Wang et al., IEDM 2009 Vertical shape ~50x higher density than thick-oxide Applications : edram, decoupling cap., DC-DC Drawbacks : additional cost, high internal series res. Slide 16

18 Deep Trench Cap. Based Loop Filter N. Butt et al., IEDM 2010 Dense deep trench cap. used for PLL s integrating cap. for the first time area reduction Thick-oxide cap. used as a ripple reject cap. no phase noise degradation Slide 17

19 Measured F max with Capacitor Types 1E-5 1E-6 1E-7 Deep Trench Thick Oxide 1E p i i p Both (640pF) Thick Oxide C i (320pF) Deep Trench C i (320pF) Deep trench vs. thick oxide integrating capacitor No noticeable difference in PLL performance Slide 18

20 Area Reduction with Deep Trench Cap. Capacitor area ratio = mm2 / mm2 = 1/56 Slide 19

21 Die Photo and Performance Summary Slide 20

22 Measured F max vs. Noise Amplitude % ~ 90mV (=10% of nom. VDD) Clockpath Config. No interconnect Short interconnect Medium interconnect Long interconnect 14.5% ~ 15.6% F max improvement for 90mV noise 100MHz F max improvement proportional to noise amplitude Slide 21

23 Measured F max vs. Noise Frequency 9.9% ~ 14.2% F max improvement for 40~320MHz Proposed PLL effective across a wide frequency range Slide 22

24 Summary Resonant supply noise is a growing concern in low voltage processors Existing PLL designs for enhancing CDC involve exhaustive search of key tuning parameters Proposed 32nm sensitivity-tracking PLL Timing-model based approach to optimize CDC Automatic supply-noise sensitivity tracking loop Low-area deep trench capacitor based loop filter 15% F max improvement, 92.1% PLL area reduction Slide 23