FTF-CON-F0403. An Introduction to Heterogeneous Multiprocessing (ARM Cortex -A + Cortex- M) on Next-Generation i.mx Applications Processors

Transcription

1 An Introduction to Heterogeneous Multiprocessing (ARM Cortex -A + Cortex- M) on Next-Generation i.mx Applications Processors FTF-CON-F0403 Glen Wienecke i.mx Systems Architect A P R TM External Use

2 Agenda Discuss embedded system use cases that drive the need for multiple execution environments Explore solutions for multiple execution environments including a heterogeneous multiprocessing (HMP) SoC that combines Cortex-A and Cortex-M cores Examine the system-level challenges of implementing HMP systems Introduce next-generation i.mx architectural features for supporting HMP Discuss the ways that the i.mx architectural features alleviate system-level HMP challenges Summarize the benefits of the i.mx HMP architecture External Use 1

3 Multiple Execution Environments External Use 2

4 Requisite for Multiple Software Execution Environments A growing number of embedded use cases require concurrent execution of isolated software environments within the system Motivation for multiple software execution environments: Real-time performance Power consumption Fast boot System integrity System security Leverage hardened or certified software solutions Reuse of legacy software External Use 3

5 Multiple Execution Environments Automotive Use Case Use case details: Automotive infotainment unit Based on rich OS Connected to vehicle bus (CAN) Connected to rear camera Environment Requirement Fast boot System security Leverage hardened/certified solutions System integrity Use Case Details CAN bus response Activation of rear-view camera CAN bus access separated from rich OS Certified CAN stack running in AUTOSAR-compliant environment Critical driver notifications available regardless of rich OS state External Use 4

6 Multiple Execution Environments Industrial Use Case Use case details: Industrial control system Rich OS for user interface Battery power or constrained power supply Environment Requirement Real-time performance Power consumption Reuse of legacy software Use Case Details Connected to sensors/controls that require real-time response Majority of active time spent aggregating data from sensors Reuse legacy software from standalone MCU External Use 5

7 Multiple Execution Environments Consumer Use Case Use case details: Portable consumer device Based on rich OS Battery power Low-power Bluetooth low energy (BLE) connection Environment Requirement Leverage certified solutions Power consumption Use Case Details Leverage BLE solution certified on standalone MCU Majority of active time spent maintaining BLE connection and monitoring sensors External Use 6

8 Multiple Execution Environment Solutions Solution Pros Cons Multi-chip System MCU/MPU connected to separate MCU Virtualization Heterogeneous Multiprocessing (HMP) Strict separation between execution environments No need for additional MCU Allows more software environments than MCUs Dynamic allocation of CPU bandwidth between software environments SoC resources can be efficiently shared and repurposed for new use cases Integrated MCU reduces BOM Potential to improve energy efficiency Efficient interprocessor communication Increased BOM Cannot directly share resources between chips Potential for high IPC overhead Complicates power management Performance impact Real-time impact Power impact Para-virtualization requires significant software Full virtualization requires significant hardware Shared resources require isolation/protection mechanisms or design changes to support multiple concurrent interfaces External Use 7

9 System-level Challenges of HMP External Use 8

10 HMP Challenges Resource Partitioning and Protection Split bus topology Provides immutable isolation of resources Lacks flexibility to repartition the resources to adapt to new use cases Resources such as memory may need to be duplicated Shared bus topology Provides flexibility to repartition the resources for new use cases Memory partitioning necessary to specify shared and isolated regions Potential issues with isolation and protection of resources Core0 Fabric Slave Split Topology Core1 Fabric Slave Shared Topology Core0 Slave Fabric Core1 Slave External Use 9

11 HMP Challenges Synchronization and Communication Interprocessor Synchronization Access to shared memory and peripherals must be synchronized Development of cooperative software is more challenging than SMP systems due to separate development environments Hardware support needed to enforce the development of cooperative software Interprocessor Communication Robust and efficient interprocessor communication is needed External Use 10

12 i.mx HMP Architecture External Use 11

13 Domain A Domain A Domain B Domain B Shared Domain B Domain A Resource Domains Use resource domains to partition the system Masters are assigned to a resource domain CPU0 Slave Slave access permissions are defined per resource domain CPU1 Slave Memory region access permissions are defined per resource domain Master Layered Fabric Slave Sideband signals of bus fabrics carry resource domain ID Master Slave External Use 12

14 Resource Domain Controller (RDC) Resource Domain Controller (RDC) is a new module integrated into next-gen i.mx devices RDC provides a centralized programming model to configure isolation and sharing of system resources Key RDC features: Assignment of master resources (CPUs and bus mastering peripherals) to a resource domain Cortex A Master Layered Fabric Bridge Memory Gasket Mem Ctrl Configuration of read/write access for slave peripherals based on resource domain Partitioning of memory into regions that can have separate domain access controls Configuration of read/write access for memory regions based on resource domain Integral semaphore hardware enables cooperative software to safely access peripherals with access by multiple domains Cortex M Master Layered Fabric Memory Gasket Bridge Mem Ctrl RDC SEMA4 Optional enforcement of semaphore usage to reject accesses by master resources that have not obtained the semaphore lock Resource Domain Access Rights External Use 13

15 IPC Hardware Summary Hardware Messaging Unit (MU) SEMA4 Shared Memory Exclusive Access Features Mailbox registers to send/receive messages Provided interprocessor interrupts Hardware-based general-purpose semaphore module topology allows shared memory RDC and CSU can provide memory protection/isolation ARMv7-A and ARMv7-M defines exclusive access instructions (LDREX/STREX) External Use 14

16 Messaging Unit (MU) Proven IP from cellular baseband SoCs Messaging control by interrupts or polling 4 RX/TX registers on each side 12 interrupt requests (IRQs) per side 4 RX register full IRQs 4 TX register empty IRQs 4 general-purpose IRQs 3 general-purpose flags per side Processor A Processor A eral Interrupts to Processor A interrupt controller Processor A side TX / RX Registers Status and Control Registers Sync and Control Registers Generate Interrupts Messaging Unit (MU) Processor B side TX / RX Registers Status and Control Registers Sync and Control Registers Generate Interrupts Processor B eral Interrupts to Processor B interrupt controller Processor B External Use 15

17 Semaphore (SEMA4) Provides a hardware mechanism for cooperative software to safely share resources in HMP systems Module reused from Vybrid and Freescale automotive MCUs Separate module from RDC semaphore Supports 16 general-purpose hardware semaphores Semaphore can only be unlocked by locking processor Optional interrupt notification after failed lock attempt to indicate when semaphore is unlocked Software conventions still required to ensure only processor with semaphore lock can access shared resources master == cp0 & (wdata == cp0_lock) 6 cp0_lock 01 master == cp0 & (wdata == unlock) 5 3 idle 00 master!= cp0 (wdata!= unlock) reset ~((master == cp0) & (wdata == cp0_lock)) &~((master == cp1) & (wdata == cp1_lock)) master == cp1 & (wdata == cp1_lock) 7 cp1_lock 10 master!= cp1 (wdata!= unlock) 8 master == cp1 & (wdata == unlock) External Use 16

18 Shared Memory Shared bus topology allows sharing of internal/external memories RDC hardware can be used to partition each memory individually and restrict access based on resource domain Cortex A Master Layered Fabric Bridge Memory Gasket Memory Gasket Mem Ctrl Mem Ctrl Cortex M Master Layered Fabric Bridge RDC SEMA4 Resource Domain Access Rights External Use 17

19 Exclusive Access Cortex-A (ARMv7-A) and Cortex-M (ARMv7-M) support exclusive access instructions (LDREX/STREX). Exclusive access bus signals generated by the CPUs are connected to monitors in the memory gaskets to support load/store exclusive instructions. Exclusive access is widely used for synchronization in SMP systems, but is applicable to HMP systems that have architectural support. For HMP systems, the memory referenced during exclusive accesses must be configured such that the access will occur at the point of coherency for the CPUs. External Use 18

20 Power Domain Partitioning System resources are partitioned into multiple power domains Power domains with unused resources can be powered down under software control to save leakage Cortex-M and low-power peripherals are located in a separate low-leakage domain to enable low-power processing High-Power CPU Domain High-Power eral Domain Low-Power CPU and eral Domain Cortex A Master Cortex M Master Layered Fabric Layered Fabric Resource Domain Bridge Memory Gasket Memory Gasket Bridge Access Rights Mem Ctrl Mem Ctrl RDC SEMA4 External Use 19

21 Summary of i.mx HMP Features Feature Integration of Cortex-A and Cortex-M processors Shared Topology Resource Domain Controller Messaging Unit (MU) Hardware Semaphore (SEMA4) Shared Memory Power Domain Partitioning HMP Benefits Execute rich OS on Cortex-A and real-time software on Cortex-M Cortex-M enhances low-power capability Use Cortex-M to increase system integrity and security Leverage proven Cortex-M software solutions Efficient use of system resources Flexibility to adapt to new use cases Allows software to partition peripherals and memories into resource domains with assignable access permissions Integrated hardware semaphore facilitates safe sharing of peripherals Flexible interprocessor communication HMP synchronization to shared resources Efficient interprocessor communication Flexibility to enable low-power processing External Use 20

22 Freescale Semiconductor, Inc. External Use