E L E C T R I C A L A N A L Y S I S R E P O R T. Use of Z-PACK 2mm HM for Fibre Channel Applications Application Note #20GC001-1 March 13, 2000

Transcription

1 E L E C T R I C A L A N A L Y S I S R E P O R T Use of Z-PACK 2mm HM for Fibre Channel Applications Application Note #20GC001-1 March 13, 2000 Copyright 2000 AMP Incorporated, Harrisburg, PA All Rights Reserved

2 Table of Contents Item Page # I. EXECUTIVE SUMMARY... 1 II. INTRODUCTION... 2 A. Connectors Connector Overview - 2mm HM 5 Row Connector Overview Universal Power Module... 4 III. 100Ω DIFFERENTIAL IMPEDANCE IN A FIBRE CHANNEL SYSTEM... 5 IV. CONNECTOR NOISE ANALYSIS... 9 A. Simulation Methodology... 9 B. Overview C. Connector Noise Analysis #1-150Ω /150Ω Environment General Simulation Assumptions Simulation Results D. Connector Noise Analysis #2-100Ω /150Ω Environment General Simulation Assumptions Simulation Results V. CONCLUSIONS VI. APPENDIX A AMP CUSTOMER DRAWINGS VII. APPENDIX B - AMP P/N S VIII. APPENDIX C CONTACT INFORMATION The information contained herein and the models used in this analysis are applicable solely to the specified AMP connector. Alternative connectors may be footprint-compatible, but their electrical performance may vary significantly, due to construction or material characteristics. Usage of the information, models, or analysis for any other connector is improper, and AMP disclaims any and all liability or potential liability with respect to such usage.

3 I. Executive Summary Use of Z-PACK 2mm HM for Fibre Channel Applications The Fibre Channel Working Group is currently considering switching the system impedance of the Fibre Channel Specification from 150Ω differential to 100Ω differential. Due to legacy issues, it is anticipated that mixed impedance systems will be developed. AMP examined the performance of the 2mm Z-PACK HM connector in various environments based on device parameters intended for Gb/s operation. For the Z-PACK HM connector, the variation in single-ended noise between a system based entirely on 150Ω and a mixed impedance configuration was 15 mv. The variation in differential noise between a complete system based on 150Ω or a mixed impedance configuration was 5 mv. Thus, the difference in performance was less than 1%. This type of performance indicates that the 2mm Z-PACK HM connector with the pinout AMP proposed could be an excellent candidate for a Fibre Channel system operating at Gb/s, regardless of the impedance configuration of the system. The system s capability to perform will depend on the overall architecture that the engineer develops and the manner in which it is implemented. AMP Incorporated strongly recommends that gigabit applications always be simulated. For mixed impedance Fibre Channel Systems, simulation could make the difference between a functional and non-functional design. AMP Circuits & Design PAGE 1 March 13, 2000

4 II. Introduction Developing a Fibre Channel System where serial data is transmitted at Gb/s can be a significant challenge. It is further complicated by the current state of the Fibre Channel Working Group, which is considering switching the system impedance from 150Ω to 100Ω. Such a switch will leave engineers with legacy issues that will need to be considered, which will greatly impact the definition of new product designs. This document provides some simulations that show the potential impact of a mixed 100Ω / 150Ω impedance system. This document explores the use of the Z-PACK 2mm HM connector in Fibre Channel applications. Connector noise analyses of the Z-PACK 2mm HM 5+2 connector in 150Ω system environments and mixed 100Ω / 150Ω system environments using worst-case driver characteristics are presented. AMP Circuits & Design PAGE 2 March 13, 2000

5 A. Connectors 1. Connector Overview - 2mm HM 5 Row Figure 1 2mm HM 5 Row Type A Connector (110 Position) The AMP Z-PACK 2mm HM 5 row connector shown in Figure 1. The pictured connector is a type A connector, which consists of 5 rows and 22 columns of pins (110 positions), plus a multi-purpose alignment center region. The 2mm HM 5 row is also available in connector types B and C, consisting of 25 and 11 columns of pins (125 and 55 positions), respectively. Unlike the type A and type C connectors, the type B connector does not have an alignment region. The type C resembles half of the type A, due to its partial alignment feature and 11 total columns. All three connector types are end-to-end stackable. The 2mm HM 5 row is also available in a ground return shielded version, which is referred to as the 5+2 row or 7-row version. The ground return shields are placed outside rows A and E of the connector to provide an additional signal reference for the outside rows. This connector is analyzed in this report. There are also various specialized versions of the 2mm HM 5 row designed specifically for the CompactPCI and VME 64 systems (see AMP flyer # and AMP data sheet #889134). Further detailed information on the Z-PACK 2mm HM connector family, see AMP catalog # AMP Circuits & Design PAGE 3 March 13, 2000

6 2. Connector Overview Universal Power Module Figure 2 Universal Power Module The AMP Universal Power Module, shown in Figure 2, is a three position, modular, Hard Metric board-to-board power connector designed to be compatible with Z-PACK 2mm HM Connectors. The design is an inverse-sex orientation, and the vertical receptacle module meets the IEC 950 safety requirements for finger probe protection. Both the headers and receptacles utilize AMP ACTION PIN press-fit leads for ease of assembly onto printed circuit boards. Additionally, the vertical receptacle leads are polarized to allow only one orientation onto the printed circuit board, eliminating the possibility of reverse placement. The housing is a high temperature thermoplastic, and the phosphor bronze contacts are gold-over-nickel plated on the mating surfaces. The modules are rated to carry a maximum of 23.5 amperes or 7.8 ampers per contact, fully energized for up to 250 mating cycles. The right angle header contacts are available with sequenced lengths for makefirst / break-last applications. Generous alignment features designed into the housings and optional guide pins and receptacles make the Universal Power Module ideal for blind mating applications. For more detailed information on the AMP Universal Power Module, see AMP catalog # AMP Circuits & Design PAGE 4 March 13, 2000

7 III. 100Ω Differential Impedance in a Fibre Channel System Currently, the Fibre Channel community is considering switching the characteristic impedance of the Fibre Channel specification from 150Ω to 100Ω. However, due to legacy issues, vendors of peripheral devices, such as disk drives, will be forced to continue to supply 150Ω-based devices. Therefore, the impact of designing a 100Ω / 150Ω system will need to be addressed. AMP considered a system topology minus the effects of any active devices. The topology was looked at in both directions. Figure 3 shows a net topology where a signal is being driven from a 150Ω environment into a 100Ω environment. Figure 4 shows a net topology where a signal is being driven from a 100Ω environment into a 150Ω environment. Sources and loads were set to match the impedance of their environment to minimize reflections. AMP simulated each configuration using the following parameters: All boards were based on FR-4 Lossy line models for 100Ω differential pairs were based on 12 mil lines. Lossy line models for 150Ω differential pairs were based on 8 mil lines. Vias at the driver, receiver, and connector were included. An ideal driver with a 1V swing and 100ps edge drove a K28.5 bit pattern operating at Gb/s into the topology under test. Figure 5 shows the results for when a signal is driven from a 150Ω environment into a 100Ω environment. The maximum eye opening was 31.75%, and the jitter encompassed 18.64% UI. Figure 6 shows the results for when a signal is driven from a 100Ω environment into a 150Ω environment. The maximum eye opening was 66.03%, and the jitter encompassed 9.32% UI. These results show the importance in considering both directions of operation when developing mixed impedance Fibre Channel applications. For the sake of comparison, AMP re-simulated the topology of Figure 3, replacing the 100Ω transmission lines with 150Ω transmission lines. The modified topology is shown in Figure 7. Maintaining a consistent 150Ω differential impedance throughout the entire system increased the maximum eye opening by 23% to 54.82%, and reduced the jitter by 11% to 7.63% UI. See Figure 8. This comparison illustrates the possible impact that a mixed impedance system can have on performance. The inclusion of terminations, actual device drivers, and specific system parameters can greatly affect the simulation results. This simulation effort was performed to show engineers the need to be cautious when developing mixed impedance systems and why a system should be simulated prior to being built. AMP Circuits & Design PAGE 5 March 13, 2000

8 Daughter Card 100 Ω Ω 3.0 Daughter Card Backplane Ω 2mm HM Z-Pack Straddle Mount SCA-II Notes 100Ω trace widths 12 mils wide 150Ω trace widths 8 mils wide Vias at driver, receiver, and connectors included K28.5 Data Pattern, Gb/s, 1V Swing / 100 ps Figure 3 150Ω Environment To a 100Ω Environment Daughter Card 100 Ω Ω 3.0 Daughter Card Backplane Ω 2mm HM Z-Pack Straddle Mount SCA-II Notes 100Ω trace widths 12 mils wide 150Ω trace widths 8 mils wide Vias at driver, receiver, and connectors included K28.5 Data Pattern, Gb/s, 1V Swing / 100 ps Figure 4 100Ω Environment To a 150Ω Environment AMP Circuits & Design PAGE 6 March 13, 2000

9 0.8 Max. Eye Opening = % Zero-Crossover Jitter = 18.64%UI Amplitude (V) Time (ns) Figure 5 150Ω Environment To a 100Ω Environment Simulation Results 0.8 Max. Eye Opening = 66.03% Zero-Crossover Jitter = 9.32%UI Amplitude (V) Time (ns) Figure 6 100Ω Environment To a 150Ω Environment Simulation Results AMP Circuits & Design PAGE 7 March 13, 2000

10 Daughter Card 150 Ω Ω 3.0 Daughter Card Backplane Ω 2mm HM Z-Pack Straddle Mount SCA-II Notes 150Ω trace widths 8 mils wide Vias at driver, receiver, and connectors included K28.5 Data Pattern, Gb/s, 1V Swing / 100 ps Figure 7 150Ω Differential System 0.8 Max. Eye Opening = 54.82% Zero-Crossover Jitter = 7.63%UI Amplitude (V) Time (ns) Figure 8 150Ω Differential System Simulation Results AMP Circuits & Design PAGE 8 March 13, 2000

11 IV. Connector Noise Analysis A. Simulation Methodology The goal of a connector noise analysis is to evaluate the noise introduced into the system by the connector. This goal is achieved by isolating the connector from the system and exciting specific pins with idealized drivers representing worst-case device switching characteristics. Validated multi-line mated pair models are used in all connector noise simulations presented here. The following concepts are used in a connector noise analysis. Near end noise is measured on the same end of the connector as the drivers, and far end noise is measured on the opposite end of the connector. Quiet pins are not driven with any signal and can be monitored for noise. Active pins are driven with a switching signal in the simulation. To simulate worst-case conditions, all active pins switch simultaneously, and each driver is excited to its maximum voltage swing in its minimum rise time. Static pins are driven with non-switching signals. Ground pins are connected to ground on both sides of the connector. Through knowledge of the connector and the performance of various signal patterns, a section of the pinout is chosen for simulation. Within a simulated section, critical signals and worst-case noise locations are monitored for noise. These sections will exhibit similar performance to comparable pin assignments in the connector. Connector noise is defined as the sum of crosstalk and common mode noise. Crosstalk is a result of currents caused by mutual capacitive and inductive coupling between two pins. Near- and far-end noise are a result of voltage drops due to these induced currents. Common mode noise is a result of ground pin return currents between the daughtercard and backplane ground planes. Because the ground pins of the connector have a finite impedance, the ground return currents cause voltage drops of equal and opposite magnitudes at the near and far ends of the connector. The manner in which signals are referenced to ground is one of the most important factors in reducing noise in high speed interconnect. When properly added to a pinout, ground pins can solve many noise problems. Therefore, the placement and quantity of ground pins in a connector should be carefully considered to maintain signal integrity. In addition, special emphasis should be given to ground pins near critical signals, such as clocks. Plots of the active pin input (near end) and output (far end) voltages are included in this report to show degradation in the driven waveform and signal propagation delay through the connector. These waveforms also demonstrate the effects of noise on the actual signal. In addition to active signal plots, noise plots are included which show the near and far end noise voltage waveforms for the monitored quiet pins. These waveforms depict crosstalk and common mode noise. AMP Circuits & Design PAGE 9 March 13, 2000

12 B. Overview The goal of this document is not to provide a solution for every conceivable Fibre Channel application, but to illustrate a pinout that was found to provide acceptable performance for a specific application. The engineer is then left to apply this knowledge to the system under development. Consider a JBOD (Just a Bunch of Disks) system. Figure 9 shows a typical architecture for a backplane intended to support JBOD functionality. The backplane provides interconnection between redundant I/O Cards that interface with an array of disk drives. Each I/O Card contains drive bypass circuitry, which interfaces through separate loops to the array of disk drives. I/O Card #1 Loop A JBOD Backplane I/O Card #2 Loop B = Vitesse 72xx Chipset = Disk Interface = I/O Card Interface Figure 9 Typical JBOD Architecture The group of signals between an I/O Card and a disk drive consists of control signals and two serial unidirectional Gb/s differential pairs. The pattern shown in Figure 10 shows how these signals were placed in the Z-PACK 2mm HM. This pinout is the best solution to address performance, crosstalk control, and ease of routing. Row Z Row A Row B Row C Row D Row E Row F 1 GND GND Enable_X GND Present_X Lock_X GND 2 GND RxX_P GND TxX_P GND Fit_X GND 3 GND RxX_N GND TxX_N GND Act_X GND Figure 10 Proposed Pattern for Individual Disk Drive AMP Circuits & Design PAGE 10 March 13, 2000

13 For the sake of clarity, Figure 11 defines which side of the connector signals are originating from and the direction that they will propagate. Tx I/O Card 2mm HM 5+2 Disk Drive Rx Figure 11 Definition of System and Signal Propagation The worst-case performance in the connector is exhibited in the area where there are multiple occurrences of the pattern shown in Figure 10 that are adjacent to each other. This new configuration is shown in Figure 12. This configuration was examined under multiple impedance configurations, as described in Table 1. Row Z Row A Row B Row C Row D Row E Row F 1 GND Rx7_P GND Tx7_P GND Fit_7 GND 2 GND Rx7_N GND Tx7_N GND Act_7 GND 3 GND GND Enable_6 GND Present_6 Lock_6 GND 4 GND Rx6_P GND Tx6_P GND Fit_6 GND 5 GND Rx6_N GND Tx6_N GND Act_6 GND 6 GND GND Enable_5 GND Present_5 Lock_5 GND 7 GND Rx5_P GND Tx5_P GND Fit_5 GND 8 GND Rx5_N GND Tx5_N GND Act_5 GND Figure 12 Simulated Pinout Connector Noise Analysis I/O Card Side Differential Impedance 1 150Ω 150Ω 2 100Ω 150Ω Disk Drive Side Differential Impedance Table 1 Connector Noise Analysis Description AMP Circuits & Design PAGE 11 March 13, 2000

14 C. Connector Noise Analysis #1-150Ω /150Ω Environment 1. General Simulation Assumptions The following assumptions were applied to the connector noise simulations discussed in this section of the report: Pinout implemented using the 2mm HM 5+2 row connectors, as defined in Figure 12. To simulate the environment that the pinout was proposed for differential transmit ( Tx ) signals were switched synchronously from 0 to 2.0 V with a rise/fall time of 100 ps (20%-80%), while differential receive ( Rx ) signals were switched synchronously from 0 to 3.0 V with a rise/fall time of 100 ps (20%-80%). Tx and Rx signals were modeled as propagating through the connector in opposite directions, as defined by Figure 11, to reflect the actual direction of signals. Single-ended board impedances of 75 Ω (150 Ω differential) were assumed on the I/O Card and Disk Drive sides of the connector. A plated through-hole capacitance of 1.0 pf was applied to both sides of the connector to simulate the effects of through-holes in both boards. 2. Simulation Results This analysis is provided as an indication of performance for the Z-PACK HM connector. The provided results provided are applicable to systems with similar conditions, and are not intended to cover all scenarios. Edge characteristics and driver differential output vary from device to device. Furthermore, it is very common at gigabit speeds for the edge of a signal to be degraded, resulting in a slower rise/fall time. The amount of degradation will vary depending on various parameters of the design, such as trace width or length. These differences can significantly alter the amount of connector noise that will be seen. To effectively understand the performance of a connector within the system, it was necessary to consider the location of the connector and the direction that signals would be propagating. The analysis of the system was further complicated by the different voltage swings of the drivers on both sides of the connector. First, the driven response of the high-speed differential signals through the connector in both directions was examined. Figure 13 shows an active Tx differential pair on the I/O Card side (Tx_in) and Disk Drive side (Tx_out). Figure 14 shows an active Rx differential pair on the Disk Drive side (Rx_in) and I/O Card side (Rx_out). The difference in propagation delay between the two graphs can be attributed to the Rx differential pairs which are located in the A row of the connector, which is physically shorter than the C row, where the Tx signals are located. It should also be noted that with this pinout the connector introduces no skew, since both signals in a differential pair are running through signal pins that have the same physical length. AMP Circuits & Design PAGE 12 March 13, 2000

15 Volts (V) AMP 2mm HM 5+2 Row Sim 150_021800_ideal_d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) Tx+_in Tx-_in Tx-_out Tx+_out Figure 13 Tx Driven Response in Row C (C1/C2) from Near-side (150Ω) Volts (V) Time (ns) AMP 2mm HM 5+2 Row Sim 150_021800_ideal_d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Rx+_in Rx-_in Rx+_out Rx-_out Figure 14 Rx Driven Response in Row A (A1/A2) from Far-side (150Ω) AMP Circuits & Design PAGE 13 March 13, 2000

16 Next, the near- and far-end noise voltages on a static signal were monitored to ensure that the amount of noise generated on this signal would be acceptable. The signal chosen resides at B3. This signal would exhibit the highest amount of noise due to its location s close proximity to neighboring switching Tx and Rx differential pairs. The near-end noise was 110 mv, and the far-end noise was 85 mv. See Figure 15. These levels should be acceptable, and should not cause any issues. Volts (mv) AMP 2mm HM 5+2 Row Sim 150_021800_ideal_s.sp Row Z A B C D E F X X Q X S S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) Figure 15 Crosstalk on Static Signal (B3) vnb03 vfb03 After this analysis, the near- and far-end noise voltages were monitored on a quiet Tx differential pair. Figure 16 shows a graph of the positive, negative, and differential nearend noise voltages. Figure 17 shows a graph of the positive, negative, and differential farend noise voltages. The differential noise was calculated by subtracting the noise induced on the negative pin from the noise induced on the positive pin. The differential near-end noise was approximately 8mV, while the far-end noise was approximately 2 mv. It is important to note which differential pair is being reviewed and the relative location of the differential receiver. For a Tx differential pair, the far-end noise, which is propagating towards the receiver that resides on the Disk Drive, will be the primary concern. The far-end noise created in the connector will be attenuated by the board traces en route to the receiver on the Disk Drive, and should not pose any issues for system operation. AMP Circuits & Design PAGE 14 March 13, 2000

17 Volts (V) 2.00E E E E E E E-02 AMP 2mm HM 5+2 Row Sim 150_021800_ideal_d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin -1.50E E Time (ns) vnc04 vnc05 differential_near Figure 16 Near-End Noise on Tx Differential Pair (C4/C5) Volts (V) 2.00E E E E E E E-02 AMP 2mm HM 5+2 Row Sim 150_021800_ideal_d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin -1.50E E Time (ns) vnc04 vnc05 differential_near Figure 17 Far-End Noise on Tx Differential Pair (C4/C5) AMP Circuits & Design PAGE 15 March 13, 2000

18 After this analysis, the near- and far-end noise voltages were monitored on a quiet Rx differential pair. Figure 18 shows a graph of the positive, negative, and differential nearend noise voltages. Figure 19 shows a graph of the positive, negative, and differential far-end noise voltages. The differential noise was calculated by subtracting the noise induced on the negative pin from the noise induced on the positive pin. The differential near-end noise was approximately 17 mv, while the far-end noise was approximately 24 mv. It is important to note which differential pair is being reviewed and the relative location of the differential receiver. For an Rx differential pair, the farend noise, which is propagating towards the receiver on the I/O Card, will be the primary concern. The far-end noise created in the connector will be attenuated by the board traces en route to the receiver on the I/O Card, and should not pose any issues for system operation. AMP Circuits & Design PAGE 16 March 13, 2000

19 Volts (mv) AMP 2mm HM 5+2 Row Sim 150_021800_ideal_d2.sp Row Z A B C D E F X Q X B X S X X q X b X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) vna04 vna05 rx_differential_near Figure 18 Near-End Noise on Rx Differential Pair (A4/A5) Volts (mv) AMP 2mm HM 5+2 Row Sim 150_021800_ideal_d2.sp Row Z A B C D E F X Q X B X S X X q X b X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) vfa04 vfa05 rx_differential_far Figure 19 Far-End Noise on Rx Differential Pair (A4/A5) AMP Circuits & Design PAGE 17 March 13, 2000

20 D. Connector Noise Analysis #2-100Ω /150Ω Environment 1. General Simulation Assumptions The following assumptions were applied to the connector noise simulations discussed in this report: Pinout implemented using the 2mm HM 5+2 row connectors, as defined in Figure 12 To simulate the environment that the pinout was proposed for differential transmit ( Tx ) signals were switched synchronously over 2.0 V from with a rise/fall time of 100 ps (20%-80%), while differential receive ( Rx ) signals were switched synchronously over 3.0 V with a rise/fall time of 100 ps (20%-80%). Tx and Rx signals were modeled as propagating through the connector in opposite directions, as defined by Figure 11 to reflect the actual direction of signals. Single-ended board impedances of 50 Ω (100 Ω differential) were assumed on the I/O Card side of the connector, while single-ended board impedances of 75 Ω (150 Ω differential) were assumed on the Disk Drive side of the connector. A plated through-hole capacitance of 1.0 pf was applied to both sides of the connector to simulate the effects of through-holes in both boards. 2. Simulation Results This analysis is provided as an indication of performance for the Z-PACK HM connector. The provided results provided are applicable to systems with similar conditions, and are not intended to cover all scenarios. Edge characteristics and driver differential output vary from device to device. Furthermore, it is very common at gigabit speeds for the edge of a signal to be degraded, resulting in a slower rise/fall time. The amount of degradation will vary depending on various parameters of the design, such as trace width or length. These differences can significantly alter the amount of connector noise that will be seen. To effectively understand the performance of a connector within the mixed impedance system, it was necessary to consider the location of the connector and the direction that signals would be propagating. The analysis of the system was further complicated by the different board impedances within the system, as well as the different voltage swings of the drivers on both sides of the connector. First, the driven response of the high-speed differential signals through the connector was examined. Figure 20 shows an active Tx differential pair on the I/O Card side (Tx_in) and Disk Drive side (Tx_out). Figure 21 shows an active Rx differential pair on the Disk Drive side (Rx_in) and I/O Card side (Rx_out). The difference in propagation delay between the two graphs can be attributed to the Rx differential pairs which are located in the A row of the connector, which is physically shorter than the C row, where the Tx signals are located. It should also be noted that with this pinout the connector introduces no skew, since both signals in a differential pair are running through signal pins that have the same physical length. AMP Circuits & Design PAGE 18 March 13, 2000

21 Volts AMP 2mm HM 5+2 Row Sim cna080599d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) Tx+_in Tx-_in Tx+_out Tx-_out Figure 20 Driven Response in Row C (C1/C2) from Near-side (100Ω) Volts AMP 2mm HM 5+2 Row Sim cna080599d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) Rx+_in Rx-_in Rx+_out Rx-_out Figure 21 Driven Response in Row A (A1/A2) from Far-side (150Ω) AMP Circuits & Design PAGE 19 March 13, 2000

22 Next, the near- and far- end noise voltages on a static signal were monitored to ensure that the amount of noise generated on this signal would be acceptable. The signal chosen resides at B3. This signal would exhibit the highest amount of noise due to its location s close proximity to neighboring switching Tx and Rx differential pairs. The near-end noise was 105 mv, and the far-end noise was 100 mv, as shown in Figure 22. These levels should not cause any issues. Volts (mv) AMP 2mm HM 5+2 Row Sim cna080599s.sp Row Z A B C D E F X X Q X S S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin vnb03 vfb Time (ns) Figure 22 Crosstalk on Static Signal (B3) After this analysis, the near- and far-end noise voltages were monitored on a quiet Tx differential pair. Figure 23 shows a graph of the positive, negative, and differential nearend noise voltages. Figure 24 shows a graph of the positive, negative, and differential far-end noise voltages. The differential noise was calculated by subtracting the noise induced on the negative pin from the noise induced on the positive pin. The differential near-end noise was approximately 8mV, while the far-end noise was approximately 4.5 mv. It is important to note which differential pair is being reviewed and the relative location of the differential receiver. For a Tx differential pair, the farend noise, which is propagating towards the receiver that resides on the Disk Drive, will be the primary concern. The far-end noise created in the connector will be attenuated by the board traces en route to the receiver on the Disk Drive, and should not pose any issues for system operation. AMP Circuits & Design PAGE 20 March 13, 2000

23 Volts (mv) AMP 2mm HM 5+2 Row Sim cna080599d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) vnc04 vnc05 differential_near Figure 23 Near-End Noise on Tx Differential Pair (C4/C5) Volts (mv) AMP 2mm HM 5+2 Row Sim cna080599d.sp Row Z A B C D E F X A X Q X S X X a X q X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) vfc04 vfc05 differential_far Figure 24 Far-End Noise on Tx Differential Pair (C4/C5) AMP Circuits & Design PAGE 21 March 13, 2000

24 After this analysis, the near- and far- end noise voltages were monitored on a quiet Rx differential pair. Figure 25 shows a graph of the positive, negative, and differential nearend noise voltages. Figure 26 shows a graph of the positive, negative, and differential farend noise voltages. The differential noise was calculated by subtracting the noise induced on the negative pin from the noise induced on the positive pin. The differential near-end noise was approximately 22 mv, while the far-end noise was approximately 29 mv. It is important to note which differential pair is being reviewed and the relative location of the differential receiver. For an Rx differential pair, the farend noise, which is propagating towards the receiver on the I/O Card, will be the primary concern. The far-end noise created in the connector will be attenuated by the board traces en route to the receiver on the I/O Card, and should not pose any issues for system operation. AMP Circuits & Design PAGE 22 March 13, 2000

25 Volts (mv) AMP 2mm HM 5+2 Row Sim cna080599d2.sp Row Z A B C D E F X Q X B X S X X q X b X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) vna04 vna05 differential_near Figure 25 Near-End Noise on Rx Differential Pair (A4/A5) Volts (mv) AMP 2mm HM 5+2 Row Sim cna080599d2.sp Row Z A B C D E F X Q X B X S X X q X b X S X Col A Rx+ switching signal a Rx- switching signal B Tx+ switching signal b Tx- switching signal Q Quiet pin X Ground pin S Static pin Time (ns) vfa04 vfa05 differential_far Figure 26 Far-End Noise on Rx Differential Pair (A4/A5) AMP Circuits & Design PAGE 23 March 13, 2000

26 V. Conclusions The Fibre Channel Working Group is currently considering switching the system impedance of the Fibre Channel Specification from 150Ω differential to 100Ω differential. Due to legacy issues, it is anticipated that mixed impedance systems will be developed. AMP examined the noise performance of the 2mm Z-PACK HM connector in a JBOD application, where the impedance was either a consistent 150Ω differential or a mixed 100Ω / 150Ω with parameters typical for devices intended for Gb/s operation. Table 2 summarizes the environments that were simulated. Connector Noise Analysis I/O Card Side Differential Impedance 1 150Ω 150Ω 2 100Ω 150Ω Far Side Differential Impedance Table 2 Connector Noise Analysis Description Table 3 shows that the variation in single-ended noise between a complete system based on 150Ω or a mixed impedance configuration was 15 mv, and that the variation in differential noise between a complete system based on 150Ω or a mixed impedance configuration was 5 mv. Thus, the difference in performance for either single-ended or differential operation was less than 1%. This type of performance indicates that the 2mm Z-PACK HM connector with the pinout AMP proposed would be an excellent candidate for a Fibre Channel system operating at Gb/s, regardless of the impedance configuration of the system. Signal Type Crosstalk CNA #1 Crosstalk CNA #2 Tx +/- Near-end 8 mv 8 mv Far-end 2 mv 4.5 mv Rx +/- Near-end 17 mv 22 mv Far-end 24 mv 29 mv Static Near-end 110 mv 105 mv Far-end 85 mv 100 mv Table 3 Connector Noise Analysis Summary The system s capability to perform will depend on the overall architecture that the engineer develops and the manner in which it is implemented. AMP Incorporated strongly recommends that gigabit applications always be simulated. For mixed impedance Fibre Channel Systems, simulation will make the difference between a functional and nonfunctional design. AMP Circuits & Design PAGE 24 March 13, 2000

27 VI. Appendix A AMP Customer Drawings AMP Circuits & Design PAGE 25 March 13, 2000

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38 VII. Appendix B - AMP P/N s Table 4 provides a list of the AMP parts that are recommended for the configuration suggested in this report. AMP P/N Description Universal Power Module Vertical Receptacle mm Z-PACK Type A HM Header mm Z-PACK Type C HM Header Guide Pin Universal Power Module Right Angle Header mm Z-PACK Type A Female Connector mm Z-PACK Type A Female Connector Lower Shield mm Z-PACK Type C Female Connector mm Z-PACK Type C Female Connector Lower Shield Female Guide Module Table 4 AMP Part Numbers AMP Circuits & Design PAGE 36 March 13, 2000

39 VIII. Appendix C Contact Information AMP Incorporated AMP Incorporated is a global company with local presence in over 50 countries. Founded in 1941 as Aero-Marine Products, AMP is today the world s leading supplier of electrical and electronic connectors and interconnection systems. Headquartered in the United States, AMP boasts 45,000 employees in the Americas, the Asia/Pacific region and Europe, the Middle East and Africa. AMP serves a variety of industries worldwide including aerospace, automotive, computer networking, consumer goods, industrial, power utilities and telecommunications with an array of interconnection solutions. A worldclass technology leader, AMP is frequently named as one of the top 50 patent-holding corporations worldwide. AMP (NYSE: AMP) sales reached nearly $5.7 billion in For more information about AMP Products, call us today or visit us on the web. Product Information Center Internet AMP Circuits & Design Offering interconnection expertise from concept to production, AMP can help validate your design and package it for manufacturing. At the front end, our end-to-end computer simulation and analysis of your system will evaluate the most critical parameters of your design. By identifying problems such as reflections, ground bounce, crosstalk, jitter, propagation delay, and timing, AMP can help you reduce costs and verify the performance of your design. Our advanced analysis and modeling techniques can help determine the optimal device drivers, board design and stackup, and board layout for your design. Thermal, EMI, and power analysis ensure signal integrity that is not affected by noise, heat, or poor airflow. And when you re ready for production, we can fabricate complex subassemblies, backplane, midplane, and mezzanine assemblies and subsystems- all with the aim of helping you meet your performance, time-to-market, and cost goals. AMP Circuits & Design PAGE 37 March 13, 2000

40 AMP has been instrumental in developing and verifying many of the world s most popular bus standards think of the ways we can help you. Our experience at bus design and analysis has helped many industry-standard and customer-specific buses perform better. Many popular buses have benefited from our system-level simulation and analysis. Here is a brief sampling. CompactPCI: Our recommendations helped make CompactPCI the rock-solid, industrial-strength bus that combines high performance with flexibility. CompactPCI Hot Swap: We provided the critical simulations that allowed mission-critical hot swapping to be a reality in CompactPCI. CT: AMP performed the simulations for the H.110 computer telephony extensions to CompactPCI. PXI: Our analysis of PXI resulted in several improvements for increased signal integrity. CPCI/CT/ATM Backplane: This is an AMP-designed bus that combines CompactPCI, CT, and Cellbus into a high-performance system that meets the growing needs of communications convergence. To find out more about our design services, contact us today. AMP Circuits & Design Internet Electrical simulation simulation@amp.com Electrical models modeling@amp.com AMP Circuits & Design PAGE 38 March 13, 2000