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1 CLICK TO EDIT MASTER SUBTITLE QUEENS-FPGA: Quality Evaluation of European New SW for BRAVE FPGA * Titles must be written in capital letters CLICK TO EDIT MASTERTITLE SEFUW 2018 ESTEC 11th April 2018 David Gonzalez-Arjona FPGA Design Engineer Tres Cantos Madrid (Spain) Contact: dgarjona@gmv.com GMV, 2015 Property of GMV All rights reserved
2 QUEENS-FPGA at SEFUW18 NanoXmap SW Tools 11/04/2018 Página 2
3 QUEENS-FPGA at SEFUW18 QUEENS-FPGA OBJECTIVES QUality assessment Evaluation of European NanoXplore SW for brave FPGA BRAVE project provided very promising European SRAM-based FPGAs for Space FPGA Development SW is really important to take full advantage of the technology Quality systematic Assessment Plan based on measurable FPGA SW Tools Metrics identification HW benchmarking identification based on consortium background knowledge (GMV, NTUA, NanoXplore) Performance and Reliability Evaluation FPGA and HDL-languages expertise on Space projects under ESA contracts Migration or Porting to BRAVE of in-house developed IP-core for space project 11/04/2018 Página 3
4 QUEENS-FPGA at SEFUW18 EVALUATION RESULTS BASES SW tools comparison DOES IT MAKE THE JOB? Can you use it for your mission? Usability, Flexibility, Reporting, Inference, Libraries HW devices comparison Power, Performances, Area 11/04/2018 Página 4
5 QUEENS-FPGA at SEFUW18 QUEENS-FPGA METRICS ABILITY TO: - synthesize a RTL code - ability to route a design - Inferred VHDL coding and mapping SW TOOL PC CONSTRAINTS: - Memory resources - Execution time - CPU usage QUALITY OF REPORTS - Organization - Synthesis estimations - Timing reports USER EXPERIENCE - Ease of use - Customization of the tools - Scripting capabilities DESIGN REUSE - IP cores provided - generating new IP cores - Support of reuse standards HARDWARE INTERACTION - Programming time - verification of bitstream - hardware debugging Area Timing Power ADVANCED DESIGN FLOWS - Floorplanning - Incremental design - Third-Party Integration (Simulation) MAIN DEV. PRODUCT METRICS - RTL Optimization - Area vs Timing vs Power - Constraints 11/04/2018 Página 5
6 QUEENS-FPGA at SEFUW18 QUEENS-FPGA METHODOLOGY Follow a systematic & unified approach throughout the tool assessment project 1. metrics & methodology (Task1) 2. benchmark selection (Task1) 3. synthesis (Task2) 4. Place & Route (Task3) 5. 3 rd party tools (Task4) 6. HW testing (Task5) QUEENS-FPGA Different complexity level circuits Fair selection of comparable devices Technology Resources Hardened Methodology serves a twofold purpose 1. explore/examine multiple tool issues parameters, load, trade-offs, etc. compare to 3 rd tools, show quality 2. avoid dead ends & erroneous reports use feedback paths, simulations 11/04/2018 Página 6
7 QUEENS-FPGA at SEFUW18 QUEENS-FPGA SYNTHESIS Built in same technology node 65 nm, SRAM-based Similar in architecture/technology 4 input LUTs DSPs (18*18 bits) Registers DFFs Similar available resources Embedded RAM blocks Number of LUTs, DSPs, DFF Space-grade devices Rad-hard High-performance devices (not so many) Each devices are supported by its vendor SW tool NanoXmap > NanoXmap (Not yet tested 2.8.5) Trade-off 11/04/2018 Página 7
8 QUEENS-FPGA at SEFUW18 BENCHMARK CIRCUITS SIMPLE CIRCUITS (DC1): Light in terms of area utilization Light in effort requirement for the SW tolos The basics Simplicity MID-COMPLEX CIRCUITS (DC2): Heavier in terms of area utilization More exigent for the SW tools Less complex than DC3 COMPLEX CIRCUITS (DC3): Most complex of the designs Worth to elaborate a specific section for the selection Stress the FPGA synthesis challenges PORTING: Image feature detection & tracking Re-design to fit in NG-MEDIUM up to the limits of resources VBN Porting Ad-hoc 11/04/2018 Página 8
9 BRAVE FPGA EVALUATION FIRST RESULTS DC1 Reference Vendors compared 11/04/2018 Página 9
10 BRAVE FPGA EVALUATION FIRST RESULTS DC2 Reference Vendors compared ~[+30% to +50%] Better maximum frequencies are not always achieved with Timing driven option than without it Timing driven option increases place and route time around 45% 11/04/2018 Página 10
11 BRAVE FPGA EVALUATION PORTING LEON3 NG-MEDIUM máx freq. <= 20 MHz 1. NG-MEDIUM technology and specific hardware resources 2. NG-MEDIUM technology added to gencomp pkg with following features: FPGA device SRAM resources (Embedded block RAMs and Register file blocks) Unavailable simultaneous read & write operations to same address in BRAMs 2 ports BRAMs True dual port BRAMs Pads Inverted output enable pad polarity Embedded clock and resources (Clock switch component CKS) Embedded clock generator resources (phase-locked loop component PLL) 3. clock generator of LEON 3 with NG-MEDIUM clock resources (PLLs and WFGs-Wave form generators). Clock and functionality with NG-MEDIUM resources (CKS). 4. different configurations of BRAMs are instantiated related with the size of data and address bus. In the case of memories up to 64 words the design instantiates register file blocks (RFBs) instead of BRAMs. 5. IO pads of LEON3 with the IO resources of NG-MEDIUM. 6. New technology is integrated in the GRLIB. Modify all files using the adapted components. Add IF_GENERATE 7. Different hardware in the board like DDR memories or PHY interfaces may need independent IPs to control the hardware 11/04/2018 Página 11
12 BRAVE FPGA EVALUATION PORTING VISION-BASED NAVIGATION IP 11/04/2018 Página 12
13 BRAVE FPGA EVALUATION RESULTS OF VISION-BASED NAVIGATION Last Version of NanoXmap v2.8.5 Metric NanoXmap Vendor 1 LUTs (6-in) DFFs DSPs BRAMs Options: UseNxLibrary: Yes DefaultFSMEncoding: Binary DefaultRAMMapping: RAM DefaultROMMapping: LUT MaxRegisterCount: ManageUnconnectedOutputs: Error ManageUnconnectedSignals: Error MappingEffort: High MergeRegisterToPad: Never AdderToDSPMapThreshold: 0 LessThanToDSPMapThreshold: 0 MultiplierToDSPMapThreshold: 1 TimingDriven: No Total Memory (Kbits) Max. Freq (MHz) Dynamic Power Consumption 0,37W 1,33W Static Power Consumption 0,73W 3,5W Página 13
14 BRAVE FPGA EVALUATION RESULTS - Very preliminary Demo, cheating just a bit: - Not in real-time - Not in closed loop - HW/SW split Página 14
15 BRAVE FPGA EVALUATION PRELIMINARY CONCLUSIONS Architecture Matters: Learn how to optimize design for the new board architecture Porting wrappers over specific HW resources (DSPs, BRAMs) Very responsive Vendor support team. Improvements version by version Corner cases or different improvement targets make some parameter worse NG-MEDIUM is in the market NanoXplore is an actual competitor Portfolio increasing Good for Industry ~[+30% to +50%] ~[+10% to +60%] Depends on reporting (LUTs for HDL, LUTs pass-through) [architecture matters]. 11/04/2018 Página 15
16 QUEENS-FPGA at SEFUW18 MORE FROM QUEENS-FPGA 11/04/2018 Página 16
17 GMV BACKGROUND EXPERIENCE Questions? Suggestions? Phobos EXOMARS Phobos Sample Return EDM-ExoMars 2016 GNC Exomars 2020 SVF+OBC Simulator Mars GNC-PHOOT NEOGNC2-IP-NPAL CAMPHORVNAV MREP Camera HW Reconfiguration ENABLE-S3 CORA-MBAD PEPS Itokawa Asteroid Sample Return NEOGNC-2 (Marco Polo-R) NEO Impact Prevention NEOShield-2 VEGA, ARION1, GETDEN TSN, TME Launchers Active Debris Removal e.deorbit HIPNOS/ORCO Didymos 1996FG3 Earth Moon Asteroid Deflection Mision AIM (AIDA) HW-in-the-loop test platform art Optical Nav Lab ATB Avionics Testbed Rovers Exploration Opportunistic Science, Spartan/Sext ant/compass LUCID/RAT Re-entrant Vehicle IXV Space Rider Moon Exploration Lunar Lander LL-VNHDA Pilot B+ ROSETTA Operations support, mission studies, IP Comet 67P/Churyumov-Gerasimenko Ganimedes JUICE Proposals for: JUICE Navcam, SW StarTracker Jupiter Callisto Europa
18 THANK YOU David Gonzalez-Arjona
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