CSP PROJECT VIRTUAL FPGA. Working with Microblaze on Alpha Data board

Transcription

1 CSP PROJECT VIRTUAL FPGA Working with Microblaze on Alpha Data board Tarundeep Singh 2008CS10195 Yogesh Kumar 2008CS10197 Sandeep Kr Bindal Ankit Kr Jain Anuj Chauhan 2008CS CS CS

2 Contents 1. Specifications Proposed block diagram and methodology... 4 Methodology Major components/blocks/kits etc Major tasks and assignments Time line (PERT chart) Weblink of our project

3 1. Specifications Steps are being taken by the IITs to virtualise the available resources make them available to other colleges. As part of these efforts we aim at developing some experiments involving FPGAs to demonstrate computer architecture concepts such as caching, pipelining etc. With the help of FPGAs installed in the lab machines using the PCI Interface students from remote locations will be able to perform experiments and see the results on their own systems. We will first design a setup using Microblaze running on the AlphaData board containing Virtex II FPGAs. The setup will consist of Microblaze running on the FPGA chip Instruction and Data memory on ZBTRAM Instruction and Data cache on BRAM Pipelined processor design Linux operating system (uclinux) running on Microblaze Thus the experiments that we will design on the above setup will test the following architecture related concepts: Impact of varying cache parameters such as set associativity, block size in perfomance Study stall cycles in a pipelined processor design The final deliverable will be an interface that allows students to experiment with computer architecture concepts using the infrastructure present remotely. 3

4 2. Proposed block diagram and methodology TERMINAL UART Interface OPB MICROBLAZE FPGA USER PROG. Microblaze ILMB µclinux Microblaze DLMB BRAM as ICACHE BRAM as DCACHE ZBTRAM ZBTRAM PCI Instruction Memory Data Memory PCI Figure 1: Block Diagram 4

5 Methodology As we are continuing our project from the summers we already have a simple interface of memory modules and interrupt, polling that runs on Microblaze. Thus we plan to build our project layer by layer adding functionalities for cache, pipelining, OS, UART etc. to the basic design sequentially. We will work on the running the OS on Microblaze and the UART design in parallel so that they can be integrated together to form an interface for the remote user. The work on pipelining will begin after work on the cache has been finished, while virtualization will take place after the successful implementation of caching and pipelining. 5

6 3. Major components/blocks/kits etc. (Status - availability, to be procured etc) Our project requires the following hardware/software: Board Alpha Data ADM-XRC-II based on the Xilinx Virtex-2 FPGAs The ADM-XRC-II is based on the Xilinx Virtex-2 FPGAs, provides up to 24MBytes of SSRAM and has an interface to allow specialised IO modules to be connected to the board. It is a complete processing system, memory, I/O and Host interface resources. It contains a PCI to local bus bridge providing the target design with a simple interface to the Host system. Board Format : PMC Host I/F : PCI Target Device(s) : Xilinx Virtex-2 SRAM : 6 independent ZBT SRAM banks 256K/512K/1024K x 36 DRAM : 256Mbyte via XRM-DDR FLASH : 16MByte Status The Alpha Data boards are already installed on two machines in the FPGA Lab. These machines can be accessed using SSH from a remote location too. User accounts on the above machines have already been created for our use. Software Xilinx EDK 9.1 Xilinx ISE 9.1 Status Licensed copies of these softwares are available from the DHD Lab and have already been procured by us. 6

7 4. Major tasks and assignments to individual group members Running Cache (Sandeep Kumar Bindal, Yogesh Kumar) Reading cache implementation policies (write back/through) Testing basic cache code Adding cache to microblaze and testing Adding functionalities such as set associativity, block size Testing improved cache with microblaze Tracing the hit/miss data for the cache Study the impact of varying cache parameters on performance Running UART (Yogesh Kumar, Sandeep Kumar Bindal ) Mapping UART pins to GPIO using level shifter to connect it to the CPU Testing UART for simple printf statements Integrating the UART with the OS (uclinux) Pipelining (Anuj Chauhan Ankit Kumar Jain) Study microblaze s pipeline implementation Tracing the stall cycles for pipelined Microblaze Monitor/OS (Ankit Kr Jain, Tarundeep Singh) Finding the code for uclinux (linux without MMU) Studying kernel dependencies and the code Compiling the uclinux code for microblaze Running it on microblaze Combining it with UART to create a terminal like interface for remote viewing Virtualization (Anuj Chauhan, Tarundeep Singh) Consolidating all the status signals from cache, pipelining etc. Creating an interface for the end user Website Updating and Reports (Anuj Chauhan) 7

8 5. Time line (PERT chart) Figure 2: PERT Chart The detailed timeline is present in the attached document. It contains description of the work to be done along with their time schedules. 8

9 6. Weblink of our project The site contains all the required information related to the project. 9

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