FPGA-based Transaction-Level Verification Through De Facto Standard Interfaces

Transcription

1 FPGA-based Transaction-Level Verification Through De Facto Standard Interfaces -- DVClub China Q4 -- Dec. 5, 2014 Ando Ki, Ph.D Dynalith Systems / Table of Contents Background Verification methods Simulation speed-up Co-verification modes Interfaces to FPGA Why transaction level Example cases AES encryptor and decryptor (comparison of co-simulation) H.264 encoder & decoder case (transaction-based co-verification) OSCI SystemC case (transaction-based co-verification) Synopsys Virtualizer to FPGA (virtual prototype co-verification) Reconfigurable computing for embedded system (Alternative usage of FPGA-based TLM) Summary DVClub Q ( 2 )

2 1) Simulation Verification Methods TB DUV Software simulator 2) Acceleration TB DUV Software simulator Hardware 3) Emulation (In-Circuit Emulation) Target Board Hardware 4) Prototype Target Board DUV HW or SW DUV Hardware (FPGA) TB: Test-bench DUV: Design Under Verification With accelerator Software-based simulation Design complexity Software-based simulation is getting slower when the design size is bigger or complex. Hardware assisted acceleration can give nearly constant speed, since it can utilize hardware parallelism However the speed-up is not realized when the design size is small due to communication overhead. Simulation performance DVClub Q ( 3 ) Simulation Speed-Up (1/2) Let say the whole design consists of Test-bench and DUA (Design Under Acceleration) The design takes time T or to do verification, i.e., simulation T OR = T TB + T DUA The verification time is reduced to T NEW by using acceleration T T OR S = = 1+ NEW T T DUA TB Then, speed-up is defined as S DVClub Q ( 4 )

3 Simulation Speed-Up (2/2) Acceleration speed-up depends on the ratio that can be reduced. The speed-up is limited by the time that can be reduced. In other words, test-bench should be small as much as possible comparing to the design in terms of dynamic characteristic Other things, Communication overhead between simulator and accelerator Even low speedup, it is still beneficial when simulation is very long Refer to [1] Amdahl s law [2] Ando Ki, How Much Speedup Can Be Achieved?, Internal Technical Memo, Dynalith Systems, July DVClub Q ( 5 ) Co-Verification Modes Cycle-based (or pin-level) Gives and takes necessary signal information between test-bench and the design in a fashion of lock-step Need to avoid combinational loop, that may cause infinite loop of lock-step Transaction-based Use commands instead of pin signals The command is a kind of transaction information carrying sufficient information about what to do Test-bench in HDL Verilog, VHLD, SystemC Gate/ RTL/ BCA UTF/ TF BFM/ Transactor Gate/ RTL/ BCA Test-bench in C Gate/ RTL/ BCA RTL: Register Transfer Level BCA: Bus Cycle Accurate BFM: Buf Functional Model UTF: Un-Timed Functional TF: Timed Functional DVClub Q ( 6 )

4 Test-bench in HVL (e.g., Verilog, SystemC,...) DUV (Desing Under Verification) Parser How to interface to FPGA (1/2) Interface generation Proxy Wrapper (or bridge or transactor) Behind techniques of interface PLI/VPI for proxy Hardware interface e.g., USB, PCI,... Device driver Proxy Wrapper or bridge Synthesizer & PnR Test-bench in HVL (e.g., Verilog, SystemC,...) Proxy Wrapper or bridge in netlist DUV in netlist Event-driven simulator (i.e., HDL simulator) FPGA Ando Ki, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung, Cycle-Accurate Co-Emulation with SystemC, SoC Design Conference 2003, COEX ASEM Hall, Seoul Korea, Nov. 5-6, Ando Ki and Young-Il Kim, Reducing Lock-Step Overhead of Hardware-Assisted Simulation Acceleration using Protocol Awareness, ISOCC-2005, Oct DVClub Q ( 7 ) How to interface to FPGA (2/2) Host interfaces PCI or PCI-Express USB 3.0 or 2.0 SATA Ethernet 1G or 10G PCI or PCI-Express is the best for cosimulation, since it requires fast turn around access with small payload. However it is a bit uncomfortable in terms of installation and maintenance. Some, e.g., laptop PC does not have one USB is alternative one It is very easy to use. However, it is not the best since USB is good at block-oriented one-direction communication, which may not be suitable to co-simulation On the other hands, it can be sufficient for transaction-level interface, which uses block-oriented data. DVClub Q ( 8 )

5 Usage of Interfaces: verification modes Hardware-assisted HDL simulation acceleration Cycle-controlled verification using high-level languages Transaction-level verification for higher performance TB: Test-Bench DUV: Design Under Verification IP: Intellectual Property DVClub Q ( 9 ) Why transaction-level? Processor SSRAM SSRM I/F Ethernet PHY Ethernet controller AHB Memory controller LCD LCD controller AHB2APB DMA PIC Timer Your block APB Most design block for SoC will be attached to system bus, e.g., AXI/AHB/APB. These block will be run under the control of the processor. As a result, the block should be verified through bus transactions, i.e., read and write. DVClub Q ( 10 )

6 Concept to adopt TLM for FPGA SW HW C program Transparent communication channel BFM (Bus Functional Model) system Bus Memory controller Peripherals Memory On-board memory HCLK HADDR A1 HWRITE AHB controls C1 HWDATA D1 HRDATA HREADY BfmWrite(...); HRESP HSEL OK1 BfmRead(...); HCLK MEM HADDR A2 HWRITE AHB controls C2 HWDATA HRDATA D2 HREADY HRESP OK2 HSEL BFM (Bus Functional Model) is a functional model generates bus transaction. DVClub Q ( 11 ) Co-simulation interfaces to model embedded processor Categorized in terms of interface between SoC model and processor model including ISS Core-model cosimulation Utilizing processing core model Run SW directly on the simulated HW Good for designing the processor. Real-chip cosimulation Utilizing real-chip Accurate simulation Linked-ISS cosimulation / integrated-iss cosimulation Embedding ISS within simulator Remote-ISS cosimulation / decoupled-iss cosimulation Connecting ISS through IPC ICE-based cosimulatin Connecting real board through RDI Similar to real-chip cosimulation, but less accurate, since low-speed communication is used for the RDI. It is used for embedded software development. L. Benini et. al., SystemC cosimulation and emulation of multiprocessor SoC designs, IEEE Computer, April 2003, p 기안도, 제 7 장 HW/SW 통합시뮬레이션, 시스템집적반도체설계검증환경과기법, 홍릉과학출판사, (Book written by Ando Ki) M I/F Real-chip ISS C program μp Real board DVClub Q ( 12 ) IPC RDI Processor RTL model Interface HDL simulator HDL simulator Rest of SoC model Rest of SoC model ISS Rest of SoC Wrapper model HDL simulator Rest of SoC BFM model HDL simulator Rest of SoC Interface model HDL simulator

7 Co-simulation with SystemC Ando Ki, HW-SW Co-Simulation (Korean), IDEC Newsletter, p.10-13, DVClub Q ( 13 ) Co-simulation with Verilog DVClub Q ( 14 )

8 Performance comparison (CPS and IPS) Simulation cycles per second Instructions per second 301, ,000 10,000,000 1,860, ,000 1,000, , ,000 98, , ,000 51,000 1,000 56,000 37,000 SystemC- SystemC SystemC- TLM IPC 25,000 22,000 14,400 5,900 3,400 Verilog Verilog- SystemC- Verilog- Verilogcore IPC PM PM 10,000 1, C-ISS SystemC-TLM 8,300 5,500 3,900 3,300 1, SystemC SystemC-IPC Verilog Verilog-IPC SystemC-PM Verilog-PM Verilog-core Sun Slaris 8 on Sun-Blade-1000, 750MHz, 2GByte SystemC with GNU GCC ModelSim 5.7c ARM7 RTL core from OpenCores ARM946E for PhysicalModeler from Dynalith Systems Unix message queue for IPC DVClub Q ( 15 ) Table of Contents Background Verification methods Simulation speed-up Co-verification modes Interfaces to FPGA Why transaction level Example cases AES encryptor and decryptor (comparison of co-simulation) H.264 encoder & decoder case (transaction-based co-verification) OSCI SystemC case (transaction-based co-verification) Synopsys Virtualizer to FPGA (virtual prototype co-verification) Reconfigurable computing for embedded system (Alternative usage of FPGA-based TLM) Summary DVClub Q ( 16 )

9 AES (Rijdael) Case Study AES: Advanced Encryption Standard Simulation Spped Improvements with Co-emulation 1.0E E Jae-Gon Lee, Woong Hwangbo, Seon-Pil Kim, and Chong-Min Kyung, "Top-down Implementation of Pipelined AES Cipher and its Verification with FPGA-based Simulation Accelerator," International Conference on ASIC (ASICON 2005), Shanghai, China, Oct E+00 DVClub Q ( 17 ) 1.0E E E Algorithmiclevel Behaviorallevel Encryption throughput (kbps) Register Transfer Level Cycle-level Transactionlevel co- co-emulation emulation Decryption Throughput (kbps) Transaction-Level Co-Verification: H.264 case DVClub Q ( 18 )

10 OSCI SystemC Co-Simulation SystemC Version 2.3 with TLM 2.0 ARM ISS extracted from GNU GDB Xilinx FPGA Spartan 3 in the incite-5000 ModelSim Questa 10.1d DVClub Q ( 19 ) Virtual Prototype Co-Verification Virtual prototype is a novel approach to model SoC or system in order to get reasonable simulation speed. IF Board Abstraction is a key role of virtual prototype. However, pin or gate-level are required to see actual results. To do this, TLM interface for FPGA is a right solution. DVClub Q ( 20 )

11 Virtual Prototype Co-Verification example: Synopsys Virtualizer icon USB Virtual Prototype Analyzer Platform Creator intuition Camera module DVClub Q ( 21 ) Reconfigurable computing Along with mobile device Android to FPGA Galaxy S case Along with compact embedded computer Linux to FPGA (Odroid case) The Heterogeneous Multi-Processing (HMP) Octa Core Linux Computer Samsung Exynos5422 Cortex-A15 2.0Ghz quad core and Cortex-A7 quad core Mali-T628 MP6(OpenGL ES 3.0/2.0/1.1 and OpenCL 1.1 Full profile) emmc5.0 HS400 Flash Storage USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4 XUbuntu or Android 4.4 Operating System Size : 90 x 70 x 18 mm improve-v7 (Dynalith) Virtex-7 200T with USB 3.0/2.0 Odroid-XU3 (Hardkernel) Linux on Samsung Exynous5534 Cotex-A15 2.0Ghz DVClub Q ( 22 )

12 Summary FPGA-based transaction-level verification through de facto standard interfaces Fast functional verification is a key part of successful SoC, while design to be integrated into SoC is getting bigger and complex and this makes verification process slower and difficult. To deal with this mismatch, FPGA-based verification is widely adopted and it includes simulation acceleration and prototyping. This talk gives FPGA-based verification methods that use de facto standard interfaces such as USB3.0/2.0 and PCI-Express between FPGA and the host computer. This environment supports cycle-based simulation, where HDL simulator runs on the host computer along with DUT (Design Under Test) in the FPGA. This environment also supports transaction-based co-emulation, where BFM (Bus Functional Model) is used to interface between DUT and host C program. DVClub Q ( 23 ) Copyright Notice. The contents addressed in this material is provided 'as-is', without any express or implied warranty. In no event will the author be held liable for any damages arising from the use of this contents. Some contents may need consent and/or license agreement from its corresponding copyright holder(s). -- Contact information -- Ando Ki, Ph.D. adki@dynalith.com DVClub Q ( 24 )