UNIT IV I/O PROGRAMMING AND SCHEDULE MECHANISM

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Geraldine York
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1 UNIT IV I/O PROGRAMMING AND SCHEDULE MECHANISM Intel I/O instruction Transfer rate, latency; interrupt driven I/O - Non-maskable interrupts; software interrupts, writing interrupt service routine in C & assembly languages; preventing interrupt overrun; disability interrupts. Multi threaded programming Context switching, premature & nonpremature multitasking, semaphores. Scheduling Thread states, pending threads, context switching, round robin scheduling, and priority based scheduling, assigning priorities, deadlock, and watch dog timers. OBJECTIVE: Intel I/O instruction Transfer rate, latency Basics of interrupt and interrupt driven I/O and Non-maskable interrupts Basics of software interrupts, writing interrupt service routine in C & assembly languages; preventing interrupt overrun; disability interrupts. Multi threaded programming Context switching, premature & non-premature multitasking semaphores. Scheduling

2 Thread states, pending threads, context switching, round robin scheduling, and priority based scheduling Assigning priorities, deadlock, and watch dog timers. INTEL I/O INSTRUCTIONS: The table-1 lists the various instructions for reading from or writing to an I/O port numbers are in the range and single byte. I/O address bus is 12 bits wide and valid port high as Instruction Operation flag IN AL,imm 8 IN AX,imm 8 acc port [imm] IN EAX,imm 8 IN AL,DX IN AX,DX acc port [DX] IN EAX,DX OUT imm 8,AL OUT imm 8,AX port [imm] acc unaffected OUT imm 8,EAX OUT DX,AL

3 OUT DX,AX port [imm] acc OUT DX,EAX INSB INSW INSD OUTB mem[edi] port [DX] If DF = 0; EDI EDI+1/2/4 If DF = 0; EDI EDI - 1/2/4 port [DX] mem[edi] These are part of the string instruction subset OUTSW If DF = 0; ESI ESI+1/2/4 OUTSD If DF = 0; ESI ESI - 1/2/4 Transfer rate: In telecommunications and computing, bit rate (sometimes written bit rate, data rate or as a variable R or fb) is the number of bits that are conveyed or processed per unit of time. It is simply a measure of the number of bytes per second transferred between the CPU and an external device. Maximum transfer rate is usually more important, since it gives a measure of the bandwidth capability of a particular method of doing I/O. Latency: Latency is often used to mean any delay or waiting that increases real or perceived response time beyond the response time desired. Specific contributors to computer latency include mismatches in data speed between the microprocessor and input/output devices and inadequate data

4 buffers.within a computer, latency can be removed or "hidden" by such techniques as prefetching (anticipating the need for data input requests) and multithreading, or using parallelism across multiple execution threads. POLLED I/O: In polled I/O the CPU must regularly check or poll each channel or port in turn to determine if it has information for input or is ready to accept data for output. A flag register can be used to check the port s status. Polling is time consuming. The CPU must pause between executing processing instructions and poll of each port. A port s status is examined in case action is required by the computer. The CPU reads or receives 8-bit encoded characters as they are typed on the keyboard. The CPU is programmed to read the input characters from an external device, in this case a keyboard. The keyboard inputs parallel 8-bit character codes for each depression of the keys. Characters are entered slowly as compared to the CPU s ability to process them. The dedicated CPU has to wait until the next character is entered each time. The CPU is programmed with what is known as an I/O wait loop. As the CPU executes the loop instructions, it periodically (say 20 times a second) checks the status code from the keyboard to see if a character has been entered. A data register, INBUF, in the keyboard interface receives the character data from the keyboard. It holds the data until read by the CPU.

5 INTERRUPT DRIVEN I/O:

13 Objective type questions:

16 Objective type Questions:

17 Scheduling:

23 DEADLINE DRIVEN SCHEDULING:

26 Objective type questions:

27 SUMMARY: * DTMF: DUAL-TONE MULTI-FREQUENCY Dual-Tone Multiple Frequency (DTMF) transmitters incorporate a multifunctional tone generator which supports: DTMF dialing (the tone you hear when you press a number on a touch tone telephone) Melody-on-hold (generate a simple melody when you are on hold) Pacifier tone functions (acknowledge button pressed) Dual-Tone Multiple Frequency (DTMF) receivers can detect and qualify DTMF signals. The 68HC05F5 DTMF utilizes a switched capacitor technology for filtering. Included is a Pre-emphasis filter (for high frequency gain) and two band separation filters (for high and low frequencies). There are an additional eight band pass filters for final frequency selection. * EEPROM: ELECTRICALLY ERASEABLE PROGRAMMABLE READ ONLY MEMORY EPROM: ERASEABLE PROGRAMMABLE READ ONLY MEMORY Electrically Erasable Programmable Read Only Memory (EEPROM) and Erasable Programmable Read Only Memory (EPROM) are both types of ROM that can be programmed by the user. EPROM can be erased by exposing it to ultraviolet light, whereas EEPROM can be erased electrically (i.e., in the application). Once erased, EPROMs and EEPROMs may be reprogrammed with new instructions and data. EEPROM and EPROM

28 information is non-volatile in that it does not change when power is removed. * I/O: BI-DIRECTIONAL INPUT AND OUTPUT PORT PINS I: INPUT ONLY PORT PINS O: OUTPUT ONLY PORT PINS Bi-directional Input and Output (I/O) ports couple the microcontroller to external devices. This interface can operate in parallel or serial form and is usually digital (0 to +5Vdc) logic. Parallel interfaces allow I/O data transfer of eight bits at a time to parallel ports on the microcontroller. The technology is typically used to transfer data between the microcontroller and the external logic it controls. * KBI: KEY BOARD INTERRUPT Typical micro controller applications have some sort of user input in the form of pressing a button or keypad. In battery powered applications it is desirable to have the MCU in a low power wait or stop mode while waiting for keypad input. When a user presses a key on the keypad an interrupt is generated. The interrupt wakes the MCU out of low power mode to execute the code that is appropriate for the key that was pressed. The KBI port pins eliminate glue logic by having pull-up resistors and logic that generates an interrupt if any of the port pins are pulled low.

29 A typical MCU key matrix has the ROW lines connected to the KBI input port pins and the COLUMN lines connected to MCU output port pins. If any key in the matrix is pressed: The row of the key is pulled low, generating an interrupt that wakes the MCU up from low-power mode Software debounces and scans the columns to determine which key was deep * SPI: SERIAL PERIPHERAL INTERFACE (SYNCHRONOUS) The Serial Peripheral Interface (SPI) is similar to the SCI, although it is used to communicate synchronously over shorter distances at up to 4 Mbit/s. The SPI allows the micro controller to communicate with peripheral devices, which could be anything from a simple TTL shift register to a complete subsystem such as an LCD display or an A/D converter system. The SPI is flexible enough to interface directly with numerous standard peripherals from many manufacturers. SPIs can also be used to expand the number of inputs and outputs of the micro controller with the minimum number of pins. Typical applications are in peripheral communications. * OTPROM: ONE TIME PROGRAMMABLE READ ONLY MEMORY

30 One-time Programmable Read Only Memory (OTPROM) is an EPROM that does not have a window on top of the package, which means that the memory cannot be exposed to ultraviolet light and therefore cannot be erased and reprogrammed. OTPROM versions of most microcontrollers are available to support your development and production needs. OTP information is non-volatile in that it does not change when power is removed. * PLL: PHASE-LOCK LOOP The phase-locked loop (PLL) is a frequency generator that takes an input clock frequency and multiples it to a much higher frequency. The 68HC08 has two different PLL modules, one uses a 32Khz crystal as its input and another uses a 1-4 Mhz crystal. Both versions generate the internal clocks used to support 8Mhz bus operation. Without the PLL, 68HC08s would require a 32Mhz oscillator which is expensive and can potentially generate unwanted noise in the MCU application. The 68HC05 has several different PLL modules used to generate the high frequencies needed for on screen displays and closed-captioning * SCI: SERIAL COMMUNICATIONS INTERFACE (ASYNCHRONOUS) The Serial Communications Interface (SCI) is an independent serial I/O subsystem (full-duplex UART-type asynchronous system). The SCI can be

31 used for communications between the microcontroller and a terminal, PC, or other microcontrollers in the form of a network. An on-chip baud rate generator derives standard baud-rate frequencies from the microcontroller oscillator. A typical SCI application is long-distance communications (RS- 232). * OSD: ON-SCREEN DISPLAY The on-screen display (OSD) module converts programmed character addresses and control information into digital color and blanking outputs to display user defined characters on a television screen for on-screen programming and closed-captioning applications. * MFT: MULTI FUNCTION TIMER The timer system is used to measure time and to produce signals of specific frequency periods. Timers can be used in multiple ways: The CPU can control the timing of output signals through the output compare mechanism and monitor incoming signals through the input capture mechanism, and the CPU can use the timer system as an internal reference (e.g., delay loops or multiplexing between various software tasks). The timer can be used for virtually any timing function, including waveform generation, simple D/A conversion, and so on.

32 * LVR: LOW VOLTAGE RESET The low voltage reset (LVR) circuit monitors the operating voltage of the MCU and forces a reset of the MCU if the voltage drops below a predefined minimum. MCUs can continue to operate below the specified minimum voltage rating but may experience unpredictable operation before they fail. The LVR circuit places the MCU in the reset state before any unpredictable behavior can occur. * LVPI: LOW VOLTAGE PROGRAM INHIBIT The low voltage program inhibit (LVPI) circuit monitors the operating voltage of the MCU and inhibits programming of the MCU if the voltage drops below a predefined minimum. MCUs can continue to program below the specified minimum voltage rating but may experience unpredictable operation before programming fails. The LVPI circuit inhibits programming before any unpredictable behavior can occur. * IC: INPUT CAPTURE (TIMER FUNCTION) The input capture (IC) mechanism of a timer can be used to detect the time of an event or measure the period of an input signal. When the selected edge occurs, the current value of the free-running counter is captured by the input capture register, which can later be read by the CPU. This is the timer mechanism typically used in the timing of external events.

33 * THREAD STATES new - an empty thread, with no system resources allocated; all you can do is start it. runnable - the start() method is called, and the thread is not dead or in the ``not runnable'' state. not runnable - sleep() is invoked, thread calls wait(), thread is blocking on I/O. dead - the end of the run() method has been reached.

34 2-Marks Questions: 1. Define process. A code that has its independent program counter values and an independent stack. A single CPU system runs one process at a time. A process is a concept. It defines a sequentially executing program and its state. A state, during the running of a process,is represented by its stats, its control block, called process control block(pcb) or process structure. 2.Define task. The basic building block of software written under an RTOS is the task. Tasks are very simply to write, under most RTOS is a task is simply a subroutine. 3.What are the three states of each task in an RTOS? Each task in an RTOS is always in one of the three states. 1.Running 2.Ready 3.Blocked 4.When is a task in RTOS said to be in running state? A task in RTOS is said to be in running state when the microprocessor is executing the instructions that make up this task. Unless yours is a

35 multiprocessor syste, there is only one microprocessor and hence only one task that is in the running state at any given time. 5.What is meant by ready state in RTOS? Ready which means that some other task is in the running state but that this task has things that it could do if the microprocessor becomes available. Any number of tasks can be in this state. 6.When a task is said to be blocked? A task is said to be blocked when task hasn t got anything to do right now, even if the microprocessor becomes available. 7.What are different task states of an RTOS? The different task states of an RTOS are Running, ready, blocked, suspended, pended, waiting dormant and delayed 8.What is called scheduler? A part of the RTOS called the scheduler keeps track of the state of each task and decides which one task should go into the running state. 9.How does the scheduler know when a task has become blocked or unblocked?

36 The RTOS provides a collection of functions that tasks can call to tell the scheduler what events they want to wait for and to signal that events have happened. 10.What happens if all the tasks are blocked? If all the tasks are blocked, then the scheduler will spin in some tight loop somewhere inside of the RTOS, waiting for something to happen. 11.What if two tasks with some priority is ready? This depends upon the type of RTOS.Some RTOSs will time slice between two such tasks. Some will run one of them until it blocks and than run the other. 12.What are preemptive RTOSs and non-preemptive RTOSs? A preemptive RTOS will stop a lower-priority task as soon as the higher priority task unblocks. A nonpreemptive RTOS will only take the microprocessor away from the lower priority task when that task blocks. 13.What is context? Each task has its own private context, which includes the register values, a program counter and a stack.

37 14.What are reentrant functions? Reentrant functions are functions that can be called by more than one task and that will always work correctly, even if the RTOS switches from one task to another in the middle of executing the functions. 15.List out the three rules to decide if a function is reentrant. The three rules are 1.A reentrant function may not use variables in a nonatomic way unless they are stored on the stack of the task that called the function or are otherwise the private variables of that task. 2.A reentrant function may not call any other functions that are not themselves reentrant. 3.A reentrant function may not use the hardware in a nonatomic way. 16.What is a gray area? functions. Gray area is an area between reentrant and nonreentrant 17.What are semaphores? Semaphores are tools than can solve the shared data problems. Since only one task can take a semaphore at a time, semaphores can prevent shared

38 data from causing bugs. Semaphores have two associated functions take and release. 18.What is called a binary semaphore? If tasks in semaphore call two RTOS functions, take semaphore and release semaphore, it is called as a binary semaphore. 19.What does trains do with semaphores? Trains do two things with semaphores a. When a train leaves the protected section of track, it raises the semaphore. B.when a train comes to a semaphore, it waits for the semaphore to rise, if necessary passes through it and lowers the semaphore. 20.What are the terms used by RTOS to indicate a semaphore? The terms used by RTOS are 1.get and give 2.take and release 3.pend and post 4.p and v 5.wait and signal

39 21.Define nucleus. The functions and data structures whose names begin with NU are those used in an RTOS called nucleus. 22.What are the advantages of having multiple semaphores? The advantage is, whenever a task takes a semaphore it is potentially slowing the response of any other task that needs the same semaphore, eventhough it has to perform different function. So to avoid this multiple semaphores are used. 23.How does the RTOS know which semaphore protects which data? It does not know. If you are using multiple semaphores, it is up to you to remember which semaphore corresponds to which data. A task that is modifying the error count must take the corresponding semaphore. 24.Specify some of the semaphore problems. Some of the semaphore problems are 1.Forgetting to take the semaphore 2.Forgetting to release the semaphore 3.Taking the wrong semaphore 4.Holding a semaphore for too long 5.Causing a deadly embrace.

40 25.What are the different kinds of semaphores? The different kinds of semaphores are 1.Counting semaphore 2.Resource semaphores 3.Mutex semaphore 16 MARK QUESTIONS: 1.Discuss in detail about process, tasks and threads. 2.Explain in detail about operating system services and goals of kernels. 3.Discuss in detail about File system organization and implementation. 4.Discuss in detail about RTOS task scheduling models. 5.Explain in detail about Inter process communication and organization. 6.Write in detail about Shared data problem. 7.Discuss in detail about Message queues and mailboxes.. 8.Discuss in detail about Remote procedure calls. 9.Discuss in detail about Cooperative round robin scheduling.

MicroProcessor. MicroProcessor. MicroProcessor. MicroProcessor

MicroProcessor. MicroProcessor. MicroProcessor. MicroProcessor 1 2 A microprocessor is a single, very-large-scale-integration (VLSI) chip that contains many digital circuits that perform arithmetic, logic, communication, and control functions. When a microprocessor