),17(558379(&725 $''5(66(6

Transcription

1 ),17(558379(&725 $''5(66(6 Figure F-0. Table F-0. Listing F-0. Table F-1 lists all processor interrupts according to their bit position in the IRPTL and IMASK registers. Four memory locations separate each interrupt vector. For each vector, Table F-1 also lists the address, mnemonic (not required by the assembler), and priority. The addresses in the vector table represent offsets from a base address. For an interrupt vector table in internal memory, the base address is 0x , the beginning of Block 0. For an interrupt vector table in external memory, the base address is 0x Table F-1. IRPTL/IMASK interrupt vectors and priorities 0 0x00 Reserved 1 0x04 RSTI Reset (read-only, nonmaskable) Highest 2 0x08 Reserved 3 0x0C SOVFI Status stack or loop stack overflow or PC full 4 0x10 TMZHI Timer high priority option 5 0x14 VIRPTI Vector interrupt 6 0x18 IRQ2I IRQ2 asserted 7 0x1C IRQ1I IRQ1 asserted ADSP-21065L SHARC Technical Reference F-1

2 Table F-1. IRPTL/IMASK interrupt vectors and priorities (Cont d) 8 0x20 IRQ0I IRQ0 asserted 9 0x24 Reserved 10 0x28 SPR0I DMA channel 0/1; SPORT0 receive A&B 11 0x2C SPR1I DMA channel 2/3; SPORT1 receive A&B 12 0x30 SPT0I DMA channel 4/5; SPORT0 transmit A&B 13 0x34 SPT1I DMA channel 6/7; SPORT1 transmit A&B 14 0x38 Reserved 15 0x3C Reserved 16 0x40 EP0I DMA channel 8; Ext. port buffer x44 EP1I DMA channel 9; Ext. port buffer x48 Reserved 19 0x4C Reserved 20 0x50 Reserved 21 0x54 CB7I Circular buffer 7 overflow 22 0x58 CB15I Circular buffer 15 overflow 23 0x5C TMZLI Timer low priority option F-2 ADSP-21065L SHARC Technical Reference

3 ,QWHUUXSW9HFWRU$GGUHVVHV Table F-1. IRPTL/IMASK interrupt vectors and priorities (Cont d) 24 0x60 FIXI Fixed-point overflow 25 0x64 FLTOI Floating-point overflow 26 0x68 FLTUI Floating-point underflow 27 0x6C FLTII Floating-point invalid 28 0x70 SFT0I User software interrupt x74 SFT1I User software interrupt x78 SFT2I User software interrupt x7C SFT3I User software interrupt 3 Lowest When an external source boots the processor s on-chip SRAM, the interrupt vector table is located in internal memory. When the processor is in no boot mode because it will execute from off-chip memory, the interrupt vector table must be located in the off-chip memory. When an external EPROM or host boots the processor s SRAM, the processor automatically sets bit 16 of IMASK (the EP0I interrupt for DMA channel 8) to 1 following reset to enable the DMA done interrupt for channel 8. It initializes IRPTL to all 0s following reset. Applications can use the IIVT bit in the SYSCON control register to override the booting mode, which determines the location of the interrupt vector table. If the processor is in no boot mode, setting IIVT to 1 selects an internal vector table, and setting IIVT to 0 selects an external vector table. IIVT has no effect when an external source boots the processor while it is in other than no boot mode. ADSP-21065L SHARC Technical Reference F-3

4 Figure F-1 on page F-5 shows the bit values in the IRPTL and IMASK registers. The default values are valid for the IMASK register only; the processor clears IRPTL after reset. For IMASK, 1 = unmasked (enabled), and 0 = masked (enabled). F-4 ADSP-21065L SHARC Technical Reference

5 ,QWHUUXSW9HFWRU$GGUHVVHV SFT3I interrupt 3 SFT2I interrupt 2 SFT1I interrupt 1 SFT0I interrupt 0 FLTII Flt.-pt invalid except. FLTUI Flt.-pt underflow except. FLTOI Flt.-pt overflow except. EPB0I Ext. Port Buf.0 DMA EPB1I Ext. Port Buf.1 DMA CB7I DAG1 Circular Buf.7 Overflow CB15I DAG2 Circular Buf.15 Overflow TMZLI Timer Expired (low priority) FIXI Fxd.-pt overflow SPT1I SPORT1 xmit A/B DMA chn 6/7 SPT0I SPORT0 xmit A/B DMA chn 4/5 SPR1I SPORT1 rcv A/B DMA chn 2/3 SPR0I SPORT0 Rcv A/B DMA chn 0/1 IRQ0I IRQ0 Asserted RSTI Reset (nonmaskable, read-only) SOVFI Stack Full/Overflow TMZHI Timer Expired (high priority) VIRPTI Multiprocessor Vector interrupt IRQ2I IRQ2 Asserted IRQ1I IRQ1 Asserted Figure F-1. IRPTL/IMASK register bit values ADSP-21065L SHARC Technical Reference F-5