ESL-Based Full System Simulation Platform

Transcription

1 EL-Based Full ystem imulation latform 陳中和 Department of Electrical Engineering Institute of Computer and Communication Engineering National Cheng Kung University NCKU-CALab

2 Term roject-reparation Lab1: Building QEU Experiment al Environment LAB 2: Building Linux Operating ystem Environment Create an environment that boots Linux kernel on AR Realview EB modeled by QEU. LAB3: Virtual achine & Linux Device Driver Design a virtual hardware running in AR Realview EB and interacting with Linux device driver and application LAB4: ystemc odule & Full ystem imulation using QEU-ystemC LAB5: Full ystem imulation using QEU & latformarchitect 2

3 roposal Due in three weeks. roposal report due (11/28) and presentation on 11/29 (5-mins) Final report and presentation 3

4 Electronic ystem Level Design Traditional VLI design flow oftware debug begins at late hour. ystem Design Hardware Design Hardware Verification rototype Build oftware Design oftware Coding oftware Debug roject Deadline 4

5 EL Early interaction with software ystem Design Hardware Design Hardware Verification rototype Build oftware Design oftware Coding oftware Debug roject Deadline 5

6 What is Full ystem imulation Full system simulation platform Hardware : processor cores, memories, interconnection buses, and peripheral devices, AICs, co-processor, etc. oftware : operating system, device drivers, and applications 6

7 Why full system simulation? Higher abstraction level, higher productivity. ake verification and optimization of complex systems possible. Validate specification requirements Function & erformance Function Verification Optimize HW architecture Interconnect topology, bus hierarchy, mem organization, Architecture Exploration EL HW/W artition & optimization Virtual latform for W development HW offload/acceleration or programs in D cores? ulti-thread programming in multi-core platform 7

8 One Example TC/I offloads Applications Operating ystem Host ystem Device Driver HOT - A Interface ( CI - Express, IDE, ) I / O ort ower I / O HY ystem Accelerator ( A ) DRA Host Bus Adapter 8

9 Limitation of Current EL imulation Tool EL ystemc simulation tool CoWare latform Architect Advantages Ready to use processor/bus models ultiple level of abstractions Transaction level Register transfer level rofiling tool Bus utilization, reads/writes, etc. However, Unacceptable O booting time (half an hour) 9

10 Acceleration of O Booting Take apart O and CU from EL tool (CoWare) Use other tool to simulate CU and to boot O Virtual machine Applications Operating ystem Device driver Bridge interface Bridge interface Hardware design ystem-on-chip EL tool (ystemc, HDL) 10

11 What is a Virtual achine Broad definition includes all emulation methods that provide a standard software interface, such as the Java V ystem Virtual achines provide a complete system level environment at binary IA V is an A of the host O Underlying HW platform is called the host, and its resources are shared among the guest Vs 11

12 Virtual achine Virtual machine V-Ware Virtual-C arallel Desktop for ac QEU (Quick Emulator) QEU ( (C/C++) Open source code Different IAs support (x86,ar,i etc) Fast simulation speed (Functional level) QEU-ystemC (Extension of QEU) Enable QEU and ystemc modelling through ABA interface in AR versatile baseboard 12

13 QEU Architecture QEU is made of several subsystems CU emulator (e.g. x86, AR, I) Emulator devices (e.g. VGA, IDE HD) Generic devices (e.g. network devices) Connecting QEU emulated devices to the corresponding host devices. achine descriptions Instantiating the emulated device. Debugger User interface 13

14 Add New Virtual Hardware QEU allows us to write a virtual hardware and emulate it teps Design your virtual machine in C code including initialization of the hardware, low level read/write (commands to hardware) functions for the hardware Design device driver for that hardware 14

15 A Fast Hybrid Full ystem imulation latform QEU Boot and run O with much less time (less 1 min) Only functional simulation CoWare ystemc based simulator & design environment in addition to C/C++, HDL Detailed profiling Booting Linux O long booting time Integration (QEU & CoWare) QEU runs O, upon which users develop A CoWare simulates hardware design Accurate level (RTL) Higher level 15

16 What is needed? Host Computer ersonal computer with Linux O CoWare latform Architect v QEU QEU-ystemC v

17 latform Overview A QEU (C, C++) AR ystem Emulator (AR Versatile baseboard ) AHB Interface Virtual Hardware QEU-ystemC Wrapper Host O ocket (): for interprocess Communication echanism communication A V bridge interface Communication echanism CoWare-ystemC Wrapper V Access ort Interrupt Controller On-Chip-Bus ( AHB, AXI, OC, ) DRA ystemc odule CoWare A (ystemc, HDL) AC 17

18 QEU ide Details imulated machine AR Versatile baseboard Debian Linux Integration schemes for QEU and CoWare AHB interface virtual hardware Character device driver (AI) for design in CoWare Interrupt service routine Qemu (C, C++) AR ystem Emulator (AR Versatile baseboard ) AR926EJ L190 Vectored Interrupt Controller Four L011 UARTs C 91c111 Ethernet adapter L050 KI with /2 keyboard and mouse.... AHB Interface Virtual Hardware Qemu-ystemC Wrapper ocket Interface (Client/erver) 18

19 CoWare ide Details Hardware AHB Bus D/AICs Other devices V interface bridge V interface bridge V access port Read/write data from QEU A to slave modules in CoWare Interrupt controller CoWare (ystemc, HDL) Bypass interrupt signal to QEU O 19 ocket Interface (erver/client) CoWare-ystemC Wrapper V Access ort Interrupt Controller On-Chip-Bus (AHB,AXI,OC...) DRA odule AC

20 Communication echanism ocket call Easy to use Flexible Other EL simulation tool ultiple computer support 20

21 ystem emory Allocation Allocate physical memory space of CoWare hardware into memory space of QEU virtual platform (simulated platform) 0 Qemu hysical emory pace QEU (C, C++) AR ystem Emulator (AR Versatile baseboard ) AHB Interface Virtual Hardware QEU-ystemC Wrapper ocket Interface CoWare hysical emory pace CoWare-ystemC Wrapper V Access ort ocket Interface Interrupt Controller On-Chip-Bus ( AHB, AXI, OC, ) DRA ystemc odule CoWare A (ystemc, HDL) AC 4G 21

22 Examples of Application Heterogeneous ulti-core AR + AC (D) GU (OpenGL/E) + ulti-view generation Network CT/I offload design 22

23 D Runs FFT rogram Develop applications using driver AI Use FFT program for example Functions for designer We should open the device first and close the device after using it. IO_init() /*standard I/O initialization operation*/ IO_exit() After opening the device, the FFT main program can use these functions to call AIs to read/write data from/to hardware in CoWare. IO_read_byte, IO_read_half, IO_read_word IO_write_byte, IO_write_half, IO_write_word 23

24 Heterogeneous ulti-core FFT main program runs in QEU O First open device using IO_init() end AC binary and data(fft.img) to CoWare IO_write_word(0xa , send_data) Call function fft() use IO_write_word to set AC to run fft use IO_read_word to read data calculated by AC Close the device, use IO_exit() Check FFT results 24

25 FULL YTE VERIFICATION LATFOR FOR ULTI-VIEW GU Qemu (C, C++) CoWare (ystemc, HDL) Qemu-ystemC Wrapper AHB aster OpenGL E Application Debian GNU/Linux O Device driver AR ystem Emulator (AR Versatile baseboard ) AHB Interface Virtual Hardware Qemu-ystemC Wrapper ocket Interface (Client) ocket Interface (erver) Interrupt Controller Geometry Engine QEU OpenGL E Application Customized device driver ystemc/rtl Co-imulation GU core Geometry module Rasterization module ulti-view generation Depth-Image Based Rendering AHB DRA odule Rasterizer Engine DIBR Engine 25

26 GU in ystem C GU with ystemc encapsulation Qemu (C, C++) OpenGL E Application Debian GNU/Linux O Device driver AR ystem Emulator (AR Versatile baseboard ) AHB Interface Virtual Hardware Qemu-ystemC Wrapper ocket Interface (Client) glfrustumf(-1.0, 1.0, -1.0, 1.0, 1.0, 20.0); glclear(gl_color_buffer_bit GL_DETH_BUFFER_ BIT); gltranslatef(0.5, 0.0, -2.0); ugolidpheref(1.0f, 24, 24); eglwapbuffers(egldisplay,eglurface); ocket Interface (erver) ystemc Qemu-ystemC Wrapper CoWare (ystemc, HDL) AHB aster Interrupt Controller Geometry Engine AHB DRA odule Rasterizer Engine DIBR Engine 26

27 GU in fresh RTL modules GU with RTL encapsulation Qemu (C, C++) OpenGL E Application Debian GNU/Linux O Device driver AR ystem Emulator (AR Versatile baseboard ) AHB Interface Virtual Hardware Qemu-ystemC Wrapper ocket Interface (Client) glfrustumf(-1.0, 1.0, -1.0, 1.0, 1.0, 20.0); glclear(gl_color_buffer_bit GL_DETH_BUFFER_ BIT); gltranslatef(0.5, 0.0, -2.0); ugolidpheref(1.0f, 24, 24); eglwapbuffers(egldisplay,eglurface); ocket Interface (erver) Qemu-ystemC Wrapper CoWare (ystemc, HDL) AHB aster Interrupt Controller Geometry Engine Debugging by comparing with ystemc models DRA odule AHB Rasterizer Engine DIBR Engine 27

28 100 % FULL YTE VERIFICATION Qemu (C, C++) OpenGL E Application GU with RTL encapsulation RTL verification confirmed Debian GNU/Linux O Device driver glfrustumf(-1.0, 1.0, -1.0, 1.0, 1.0, 20.0); AR ystem Emulator (AR Versatile baseboard ) glclear(gl_color_buffer_bit GL_DETH_BUFFER_ AHB Interface Virtual Hardware BIT); Qemu-ystemC Wrapper gltranslatef(0.5, 0.0, -2.0); ocket Interface (Client) ugolidpheref(1.0f, 24, 24); eglwapbuffers(egldisplay,eglurface); ocket Interface (erver) Qemu-ystemC Wrapper CoWare (ystemc, HDL) AHB aster Interrupt Controller Geometry Engine AHB DRA odule Rasterizer Engine DIBR Engine 28

29 Flexibility Qemu (C, C++) OpenGL E Application Debian GNU/Linux O Device driver AR ystem Emulator (AR Versatile baseboard ) AHB Interface Virtual Hardware Qemu-ystemC Wrapper ocket Interface (Client) QEU (fast emulator) OpenGL E benchmark suite Customized device driver For GU + DIBR Co-simulation ocket Interface (erver) odule name Design level Qemu-ystemC Wrapper ABA AHB Timed TL CoWare (ystemc, HDL) AHB aster Interrupt Controller Geometry Engine ABA bridge Timed TL RA Untimed TL AHB Geometry Engine RTL RA odule Rasterizer Engine DIBR Engine Rasterizer Engine DIBR Engine RTL RTL 29

30 CT/I Offload ystem Computer 1 CT: tream Control Transmission rotocol QEU Virtual Host 1 ( O/, Driver, Application ) Qemu-ystemC Interface Network Offload Engine Virtual AC hysical Host 1 QEU Virtual Host 2 ( O/, Driver, Application ) Qemu-ystemC Interface Network Offload Engine Virtual AC Computer 2 hysical Host 2 ( O/, Driver, Application ) 1. Functional verification 2. Connection with real world (path1) 3. erformance evaluation for 10 Gb (path 2) 2 1 Virtual Network CoWare (ystemc, C/C++, HDL) Raw ocket AI NIC (Network Interface Card) NIC Ethernet 30

31 CT/I Offload ystem CoWare on C 1, Host QEU on C 2 Network Offload Engine (CT, I, AC) FT client (run on your design) talks to FT server (real world) Virtual AC (model bit rates) Computer 1 Computer 2 QEU CoWare A Qemu-ystemC Interface Network Offload Engine Virtual Host FT Client Qemu-ystemC Interface Virtual AC FT erver Network Interface Card Network Interface Card Ethernet 31

32 Network Offload ystem Computer 1 Computer 2 QEU Virtual Host CoWare A Qemu-ystemC Interface Network Offload Engine FT Client Qemu-ystemC Interface FT client FT server Virtual AC FT erver Network Interface Card Network Interface Card Ethernet The FT client in the virtual platform was uploading files to the server. The FT server in the real world computer was receiving data from the client. Finally, the files had been received completely at the server. 32

33 ortability The same memory allocation and O No need to change device driver and application Different O Only need to change device driver Header files, different system calls No need to change application Different memory allocation Need to change device driver and application but only address dependent statements 33

34 erformance Issue imulation overhead Use socket call for communication between QEU and CoWare Hardware implementation (FGA) uses no socket call erformance improvement Reduce communication Rbyte+Rbyte+Rbyte+Rbyte => Rword Reconstruct Data flow 34

35 And in conclusion A full system simulation platform that enables Application, Linux operating system, Host processor, and RTL/ystemC design simulation. A convenient and easy-to-use integrated platform for software/hardware debugging and verification. Applications, drivers, RTLs. An EL tool that can tackle with designs of high complexity. Instruction profiling in QEU Instruction count (ID-based), type, user/kernel mode ower estimation 35