QEMU and SystemC. Màrius Màrius Montón
|
|
- Walter Patterson
- 6 years ago
- Views:
Transcription
1 QEMU and SystemC March March QUF'11 QUF'11 Grenoble Grenoble Màrius Màrius Montón
2 Outline Introduction Objectives Virtual Platforms and SystemC Checkpointing for SystemC Conclusions 2
3 Introduction Virtual Platforms Functional models of physical platforms Target SW unable to distinguish virtual platform from real HW Run SW or OS on Virtual HW Develop SW for non-existing HW Simulate complex system interconnectivity 3
4 Introduction Virtual Platforms 4
5 Introduction Virtual Platforms 5
6 Virtual Platform Design Engineering Resources Hardware Software Integration & Test time WindRiver (Virtutech) 6
7 Virtual Platform Design Engineering Resources Hardware Software Integration & Test time Engineering Resources Resources Software Hardware Integration & Test time Time to Market WindRiver (Virtutech) 7
8 Generic Virtual Platform Diagram User User User Target Operating System Target Drivers Boot code Memories Devices Devices ISS ISS VP Back-end functions Virtual Platform 8
9 Introduction SystemC & TLM-2 SystemC language for systems description (HW mainly) OSCI simulator TLM-2 standarizes communication model Sockets to emulate any memory-mapped bus De facto standard for system modeling 9
10 Introduction VP Languages Different Virtual Platforms uses different languages (C, C++, DLM,...) and APIs HW engineers know (or should) SystemC, not other languages Different VP Rewrite own models No interoperability 10
11 Objectives Add SystemC-TLM to any Virtual Platform Different strategies to add two simulators Add SystemC-TLM support to an open-sourced VP Add checkpointing support to SystemC C++ not checkpointable Overcome limitations 11
12 Generic Virtual Platform Diagram User User User Target Operating System Target Drivers Boot code SystemC Devices Memories Devices Devices ISS ISS Sync SystemC VP Back-end functions Virtual Platform 12
13 Virtual Platforms and SystemC Link together two simulators Synchronization strategy Generic bridge Support for generic TLM-2 devices LT, AT, DMI... 13
14 Virtual Platforms and SystemC Link together two simulators SystemC Synch VP Virtual time 14
15 Virtual Platforms and SystemC SystemC Synch VP Virtual execution Execution time 15
16 QEMU-SC Transition from RTL to TLM Generic fabric bus (TLM) any architecture QEMU master and SystemC slave (simulation) QEMU manages simulation Focus on few SystemC devices Application Linux Driver VP SC_Link SC_Bridge TLM Socket SystemC module 16
17 QEMU-SC Application Linux Driver VP SC_Link SC_Bridge TLM Socket SystemC module 17
18 Synchronization Only synchronize when needed (sc_start()) When SystemC devices are accessed When pending event in current simulation time SystemC events list When I/O to/from SystemC device Capture or notify all I/O in SystemC device QuantumKeeper asks to To adhere to standard 18
19 Communication QEMU works with zero-delay communication CPU accesses one device and the device responds immediately Fit to LT devices Need to manage AT devices Special synchronization Finish all protocol phases before return to VP 19
20 Communication - LT VP SC Bridge LT Device operation() b_transport() operation() 20
21 Communication - AT VP SC Bridge AT Device operation() nb_transport_fw() BEGIN_REQ nb_transport_bw() END_REQ nb_transport_bw() BEGIN_RESP nb_transport_fw() END_RESP operation() 21
22 Synchronization Manage external I/O from/to SC device Devices use QEMU callbacks for I/O Bridge knows when a I/O is performed Synchronize simulators Continue SystemC simulation when VP time arrives to first SC event Every quantum time (TLM-2) Advance SystemC time until transaction ends 22
23 QBox Change simulation manager QEMU becomes simulator slave SystemC manages simulation QEMU is a TLM-2 Initiator module Easy integration Focus on many SystemC models Wrapper QEMU SystemC simulation TLM Socket Target module 23
24 QBox SystemC simulation Wrapper QEMU TLM Socket Target module 24
25 QBox internal architecture QEMU Wrapper manage_int() SignalSocket Ghost PCI dev 1 Ghost PCI dev 2 SC_Link Start sc_write() sc_read() TLM 2 Socket PCI Bus Stop QEMU sc_dmi_write() DMI Pointer sc_dmi_read() 25
26 QBox complex example TILE TILE QEMU Wrapper NoC QEMU NIC TILE 26
27 Test & results Different tests and examples Validate implementation Extract performance metrics Results for performance relatives to same system in native language C in QEMU & Qbox 27
28 QEMU-SC Test System MPEG-2 decoder Linux Driver MPEG accelerator SystemC idct acc. IRQ IRQ QEMU SC_Link SC_Bridge DMI Pointer Reg. File irq_event TLM Socket 28
29 QEMU-SC Results No acc ,10 23,26 25,25 28,13 32,17 26,60 27,29 No acc. w/ drivers QEMU style 1 acc. SystemC 1 acc. Time in seconds ,10 A B C D E F G H QEMU style 2 acc. SystemC 2 acc. SystemC skel. (1 acc.) SystemC skel. (2 acc.) Configurations 29
30 QEMU-SC Results Penalty 8% ~ 14% 32,17 28,13 26,60 27,29 25,25 22,10 23,26 No acc. No acc. w/ drivers QEMU style 1 acc. SystemC 1 acc. Time in seconds ,10 A B C D E F G H QEMU style 2 acc. SystemC 2 acc. SystemC skel. (1 acc.) SystemC skel. (2 acc.) Configurations 30
31 QBox Test System QEMU Wrapper MPEG-2 decoder SignalSocket (IRQ) SystemC idct acc. IRQ Linux Driver QEMU TLM Socket GreenRouter Reg. File irq_event 31
32 QBox Results No acc. 80 No acc. w/ drivers 70 QEMU style 1 acc. Time in seconds SystemC 1 acc. QEMU style 2 acc. SystemC 2 acc A B C D E F G H SystemC skel. (1 acc.) SystemC skel. (2 acc.) Configurations 32
33 QBox Results 80 Penalty ~ 100%!!! No acc. No acc. w/ drivers 70 QEMU style 1 acc. Time in seconds SystemC 1 acc. QEMU style 2 acc. SystemC 2 acc A B C D E F G H SystemC skel. (1 acc.) SystemC skel. (2 acc.) Configurations 33
34 QBox Test System Penalty ~ 100%!!! QEMU Wrapper MPEG-2 decoder SignalSocket (IRQ) SystemC idct acc. IRQ Linux Driver QEMU TLM Socket GreenRouter Reg. File irq_event 34
35 Complex QBox system QEMU Wrapper Testbench Linux SignalSocket (IRQ) TLM 2 Socket NE2000 TLM 2 Socket (Ethernet) QEMU DMI Pointer GreenRouter NE
36 Conclusions SystemC Joined SystemC to two Virtual Platforms Tested two different strategies for joining two simulators QEMU-SC QBox Minor performance impact SystemC bridge Published as open-sourced projects 36
37 Conclusions SystemC Simulation Manager Penalty System for QEMU-SC Yes 10% SW QBox No 25~30% HW 37
38 Future Work Automagic configuration of QBox systems Manage map-address in QEMU, Router, BIOS, etc. Enhance QEMU time management Hard to measure virtual time in QEMU Add multiple instances from QEMU Current QBox library allows one Explore QEMU user mode Simplified version, only ISS, run applications 38
39 Future Work Merge SystemC methods into QEMU kernel Remove OSCI simulator and write an API SystemC <-> QEMU Merge QEMU functionality into OSCI kernel Make QEMU a truly SystemC ISS Both merges increase simulation speed due to removed synchronization 39
40 Proposal Join efforts and teams to develop just one QEMU & SystemC virtual platform 40
41 Thank you! Questions?
The TLM-2.0 Standard. John Aynsley, Doulos
The TLM-2.0 Standard John Aynsley, Doulos The TLM-2.0 Standard CONTENTS Review of SystemC and TLM Review of TLM-2.0 Frequently Asked Questions What is SystemC? System-level modeling language Network of
More informationAVIRTUAL platform (VP) or full-system simulation is a
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 1, JANUARY 2013 133 Checkpointing for Virtual Platforms and SystemC-TLM Màrius Montón, Jakob Engblom, and Mark Burton Abstract
More informationChecking for TLM-2.0 Compliance - Why Bother? Dr. Andrea Kroll VP Marketing and Business Development JEDA Technologies, Inc.
Checking for TLM-2.0 Compliance - Why Bother? Dr. Andrea Kroll VP Marketing and Business Development JEDA Technologies, Inc. Agenda Model Integration Challenges TLM2.0 Rules Beyond Transport Calls OSCI
More informationHardware Design and Simulation for Verification
Hardware Design and Simulation for Verification by N. Bombieri, F. Fummi, and G. Pravadelli Universit`a di Verona, Italy (in M. Bernardo and A. Cimatti Eds., Formal Methods for Hardware Verification, Lecture
More informationQEMU for Xilinx ZynqMP. V Aug-20
QEMU for Xilinx ZynqMP Edgar E. Iglesias V2 2015-Aug-20 ZynqMP SoC New Chip (Zynq NG) Aggressive target for QEMU as early SW platform emulating WiP chip BootROMs, Boot-loaders,
More informationIntroduction to Accellera TLM 2.0
Introduction to Accellera TLM 2.0 Aravinda Thimmapuram 10 th Sept 2015 Accellera Systems Initiative 1 Agenda Introduction to TLM and TLM 2.0 standard Case study of modelling a bus protocol using TLM 2.0
More informationIO virtualization. Michael Kagan Mellanox Technologies
IO virtualization Michael Kagan Mellanox Technologies IO Virtualization Mission non-stop s to consumers Flexibility assign IO resources to consumer as needed Agility assignment of IO resources to consumer
More informationVirtual PLATFORMS for complex IP within system context
Virtual PLATFORMS for complex IP within system context VP Modeling Engineer/Pre-Silicon Platform Acceleration Group (PPA) November, 12th, 2015 Rocco Jonack Legal Notice This presentation is for informational
More informationThe Architects View Framework: A Modeling Environment for Architectural Exploration and HW/SW Partitioning
1 The Architects View Framework: A Modeling Environment for Architectural Exploration and HW/SW Partitioning Tim Kogel European SystemC User Group Meeting, 12.10.2004 Outline 2 Transaction Level Modeling
More informationARM s IP and OSCI TLM 2.0
ARM s IP and OSCI TLM 2.0 Deploying Implementations of IP at the Programmer s View abstraction level via RealView System Generator ESL Marketing and Engineering System Design Division ARM Q108 1 Contents
More informationGreenBus Wolfgang Klingauf 14th ESCUG Meeting FDL 06 Darmstadt
GreenBus Wolfgang Klingauf w.klingauf@tu-braunschweig.de 14th ESCUG Meeting FDL 06 Darmstadt 1 GreenSocs THE Open Source community based SystemC infrastructure project. Open to all to contribute / join
More informationVeloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics
Veloce2 the Enterprise Verification Platform Simon Chen Emulation Business Development Director Mentor Graphics Agenda Emulation Use Modes Veloce Overview ARM case study Conclusion 2 Veloce Emulation Use
More informationSCope: Efficient HdS simulation for MpSoC with NoC
SCope: Efficient HdS simulation for MpSoC with NoC Eugenio Villar Héctor Posadas University of Cantabria Marcos Martínez DS2 Motivation The microprocessor will be the NAND gate of the integrated systems
More informationExtending Fixed Subsystems at the TLM Level: Experiences from the FPGA World
I N V E N T I V E Extending Fixed Subsystems at the TLM Level: Experiences from the FPGA World Frank Schirrmeister, Steve Brown, Larry Melling (Cadence) Dave Beal (Xilinx) Agenda Virtual Platforms Xilinx
More informationCo-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms. SAMOS XIV July 14-17,
Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms SAMOS XIV July 14-17, 2014 1 Outline Introduction + Motivation Design requirements for many-accelerator SoCs Design problems
More informationUVM: The Next Generation in Verification Methodology
UVM: The Next Generation in Verification Methodology Mark Glasser, Methodology Architect February 4, 2011 UVM is a new verification methodology that was developed by the verification community for the
More informationExperiences and Challenges of Transaction-Level Modelling with SystemC 2.0
Experiences and Challenges of Transaction-Level Modelling with SystemC 2.0 Alain CLOUARD STMicroelectronics Central R&D (Grenoble, France) STMicroelectronics TLM is useful SoC HW/SW design flow Standard
More informationCode Generation for QEMU-SystemC Cosimulation from SysML
Code Generation for QEMU- Cosimulation from SysML Da He, Fabian Mischkalla, Wolfgang Mueller University of Paderborn/C-Lab, Fuerstenallee 11, 33102 Paderborn, Germany {dahe, fabianm, wolfgang}@c-lab.de
More informationOn the Co-simulation of SystemC with QEMU and OVP Virtual Platforms
On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms Alessandro Lonardi 1 and Graziano Pravadelli 1,2(B) 1 Department of Computer Science, University of Verona, Verona, Italy alessandro.lonardi@univr.it
More informationIntroduction to TLM Mechanics Presented by David C Black
Introduction to TLM Mechanics Presented by David C Black Topics Simulation Use Cases Basic Concepts Generic Payload Information API - The Transaction Call Sockets Connectivity Loosely Timed Fast Approximately
More informationSTARC Compliant Models
STARC Compliant Models Software for Semiconductors Copyright 2009 CircuitSutra Technologies Pvt Ltd All Rights Reserved Page 1/21 Document History: Date Name Comment Version 2 nd March, 2009 CircuitSutra
More informationQBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.0
QBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.0 Guillaume Delbergue, Mark Burton, Frederic Konrad, Bertrand Le Gal, Christophe Jego To cite this version: Guillaume
More informationEE382N: Embedded System Design and Modeling
EE382N: Embedded System Design and Modeling Lecture 9 Communication Modeling & Refinement Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu Lecture
More informationTransaction Level Modeling with SystemC. Thorsten Grötker Engineering Manager Synopsys, Inc.
Transaction Level Modeling with SystemC Thorsten Grötker Engineering Manager Synopsys, Inc. Outline Abstraction Levels SystemC Communication Mechanism Transaction Level Modeling of the AMBA AHB/APB Protocol
More informationOSCI Update. Guido Arnout OSCI Chief Strategy Officer CoWare Chairman & Founder
OSCI Update Guido Arnout OSCI Chief Strategy Officer CoWare Chairman & Founder Chief Strategy Officer charter Ensure that OSCI strategy is created, coordinated, communicated & executed Identify OSCI technical
More informationSPACE: SystemC Partitioning of Architectures for Co-design of real-time Embedded systems
September 29, 2004 SPACE: Partitioning of Architectures for Co-design of real-time Embedded systems Jérome Chevalier 1, Maxime De Nanclas 1, Guy Bois 1 and Mostapha Aboulhamid 2 1. École Polytechnique
More informationEE382V: Embedded System Design and Modeling
EE382V: Embedded System Design and Communication & Refinement Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu : Outline Communication layers Application
More informationIntroduction to the SystemC TLM Standard Stuart Swan Cadence Design Systems, Inc June 2005
Introduction to the SystemC TLM Standard Stuart Swan Cadence Design Systems, Inc June 2005 1 Copyright 2005 CADENCE DESIGN SYSTEMS, INC. SystemC Transaction Level Modeling What is TLM? Communication uses
More informationPerformance Verification for ESL Design Methodology from AADL Models
Performance Verification for ESL Design Methodology from AADL Models Hugues Jérome Institut Supérieur de l'aéronautique et de l'espace (ISAE-SUPAERO) Université de Toulouse 31055 TOULOUSE Cedex 4 Jerome.huges@isae.fr
More informationA Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design
A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design Ahmed Amine JERRAYA EPFL November 2005 TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble CEDEX, France Email: Ahmed.Jerraya@imag.fr
More informationTowards a SystemC Transaction Level Modeling Standard. Stuart Swan Senior Architect Cadence Design Systems, Inc. June 2004
Towards a SystemC Transaction Level Modeling Standard Stuart Swan Senior Architect Cadence Design Systems, Inc. June 2004 SystemC Transaction Level Modeling What is TLM? Communication uses function calls
More informationGetting Started with TLM-2.0
Getting Started with TLM-2.0 A Series of Tutorials based on a set of Simple, Complete Examples John Aynsley, Doulos, June 2008 Tutorial 1 Sockets, Generic Payload, Blocking Transport Introduction The TLM-2.0
More information... Application Note AN-531. PCI Express System Interconnect Software Architecture. Notes Introduction. System Architecture.
PCI Express System Interconnect Software Architecture Application Note AN-531 Introduction By Kwok Kong A multi-peer system using a standard-based PCI Express (PCIe ) multi-port switch as the system interconnect
More informationA comparative analysis of Precision Time Protocol in native, virtual machines and container-based environments for consolidating automotive workloads
A comparative analysis of Precision Time Protocol in native, virtual machines and container-based environments for consolidating automotive workloads Speaker: Co-authors: Ong Boon Leong boon.leong.ong@intel.com
More informationHardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015
Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs August 2015 SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal Software DSP Software Bare Metal Software
More informationChapter 2 M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration
Chapter 2 M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration Hector Posadas, Sara Real, and Eugenio Villar Abstract Design Space Exploration for complex,
More information2. HW/SW Co-design. Young W. Lim Thr. Young W. Lim 2. HW/SW Co-design Thr 1 / 21
2. HW/SW Co-design Young W. Lim 2016-03-11 Thr Young W. Lim 2. HW/SW Co-design 2016-03-11 Thr 1 / 21 Outline 1 Software Engineering Young W. Lim 2. HW/SW Co-design 2016-03-11 Thr 2 / 21 Based on Software
More informationIntroduction to gem5. Nizamudheen Ahmed Texas Instruments
Introduction to gem5 Nizamudheen Ahmed Texas Instruments 1 Introduction A full-system computer architecture simulator Open source tool focused on architectural modeling BSD license Encompasses system-level
More informationFast and Accurate Source-Level Simulation Considering Target-Specific Compiler Optimizations
FZI Forschungszentrum Informatik at the University of Karlsruhe Fast and Accurate Source-Level Simulation Considering Target-Specific Compiler Optimizations Oliver Bringmann 1 RESEARCH ON YOUR BEHALF Outline
More informationEmbedded System Design and Modeling EE382V, Fall 2008
Embedded System Design and Modeling EE382V, Fall 2008 Lecture Notes 4 System Design Flow and Design Methodology Dates: Sep 16&18, 2008 Scribe: Mahesh Prabhu SpecC: Import Directive: This is different from
More informationSystem On Chip: Design & Modelling (SOC/DAM) 1 R: Verilog RTL Design with examples.
System On Chip: Design & Modelling (SOC/DAM) Exercises Here is the first set of exercises. These are intended to cover subject groups 1-4 of the SOC/DAM syllabus (R, SC, SD, ESL). These questions are styled
More informationEfficient use of Virtual Prototypes in HW/SW Development and Verification
Efficient use of Virtual Prototypes in HW/SW Development and Verification Rocco Jonack, MINRES Technologies GmbH Eyck Jentzsch, MINRES Technologies GmbH Accellera Systems Initiative 1 Virtual prototype
More informationSpaceWire. Design of the SystemC model of the SpaceWire-b CODEC. Dr. Nikos Mouratidis
SpaceWire Design of the SystemC model of the SpaceWire-b CODEC Dr. Nikos Mouratidis Qualtek Sprl. 36 Avenue Gabriel Emile Lebon B-1160, Brussels, Belgium 19/09/2011 Activity objectives: High-level modeling
More informationDesign methodology for multi processor systems design on regular platforms
Design methodology for multi processor systems design on regular platforms Ph.D in Electronics, Computer Science and Telecommunications Ph.D Student: Davide Rossi Ph.D Tutor: Prof. Roberto Guerrieri Outline
More informationContents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)
1 Introduction............................................... 1 1.1 Functional Design Verification: Current State of Affair......... 2 1.2 Where Are the Bugs?.................................... 3 2 Functional
More informationAssembling and Debugging VPs of Complex Cycle Accurate Multicore Systems. July 2009
Assembling and Debugging VPs of Complex Cycle Accurate Multicore Systems July 2009 Model Requirements in a Virtual Platform Control initialization, breakpoints, etc Visibility PV registers, memories, profiling
More informationModeling and Simulation of System-on. Platorms. Politecnico di Milano. Donatella Sciuto. Piazza Leonardo da Vinci 32, 20131, Milano
Modeling and Simulation of System-on on-chip Platorms Donatella Sciuto 10/01/2007 Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20131, Milano Key SoC Market
More informationVirtual Machine Virtual Machine Types System Virtual Machine: virtualize a machine Container: virtualize an OS Program Virtual Machine: virtualize a process Language Virtual Machine: virtualize a language
More informationPre-Silicon Host-based Unit Testing of Driver Software using SystemC Models
Pre-Silicon Host-based Unit Testing of Driver Software using SystemC Models Aravinda Thimmapuram Somarka Chakravarti Tamal Saha Rathina Thalaiappan Accellera Systems Initiative 1 Agenda Introduction Problem
More informationSystem Level Design with IBM PowerPC Models
September 2005 System Level Design with IBM PowerPC Models A view of system level design SLE-m3 The System-Level Challenges Verification escapes cost design success There is a 45% chance of committing
More informationThe Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System
The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System Laurent VUILLEMIN Platform Compile Software Manager Emulation Division Agenda What is
More informationValidation Strategies with pre-silicon platforms
Validation Strategies with pre-silicon platforms Shantanu Ganguly Synopsys Inc April 10 2014 2014 Synopsys. All rights reserved. 1 Agenda Market Trends Emulation HW Considerations Emulation Scenarios Debug
More informationAusgewählte Betriebssysteme - Mark Russinovich & David Solomon (used with permission of authors)
Outline Windows 2000 - The I/O Structure Ausgewählte Betriebssysteme Institut Betriebssysteme Fakultät Informatik Components of I/O System Plug n Play Management Power Management I/O Data Structures File
More informationModelling, simulation, and advanced tracing for extra-functional properties in SystemC/TLM
Modelling, simulation, and advanced tracing for extra-functional properties in SystemC/TLM Philipp A. Hartmann philipp.hartmann@offis.de OFFIS Institute for Information Technology R&D Division Transportation
More informationWhat is gem5 and where do I get it?
What is gem5 and where do I get it? Andreas Sandberg & Nikos Nikoleris ARM Research Why gem5? Runs real workloads Runs complex workloads like Android & ChromeOS System-level insights Device interactions
More informationKVM PV DEVICES.
K DEVICES dor.laor@qumranet.com Agenda Kernel Virtual Machine overview Paravirtualized s intro & brief history VirtIO Enhanced VirtIO with K support 2 Kernel Virtual Machine overview is a regular Linux
More informationAMBA Programmer s View Extensions to OSCI TLM v2.0. Nizar ROMDHANE Technical Marketing Manager RealView Tools, DSTG April, 2007
AMBA Programmer s View Extensions to OSCI TLM v2.0 Nizar ROMDHANE Technical Marketing Manager RealView Tools, DSTG April, 2007 1 Presentation Structure ARM Activities within OSCI AMBA Protocols: AXI focus
More informationKVM PV DEVICES.
K DEVICES dor.laor@qumranet.com 1 Agenda Introduction & brief history VirtIO Enhanced VirtIO with K support Further implementation 2 General & history Fully virtualized devices performs bad 55 Mbps for
More informationOptimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd
Optimizing ARM SoC s with Carbon Performance Analysis Kits ARM Technical Symposia, Fall 2014 Andy Ladd Evolving System Requirements Processor Advances big.little Multicore Unicore DSP Cortex -R7 Block
More informationIntel Graphics Virtualization on KVM. Aug KVM Forum 2011 Rev. 3
Intel Graphics Virtualization on KVM Aug-16-2011 allen.m.kay@intel.com KVM Forum 2011 Rev. 3 Agenda Background on IO Virtualization Device Operation on Native Platform QEMU IO Virtualization Device Direct
More informationA Beginner's Guide to Using SystemC TLM-2.0 IP with UVM
A Beginner's Guide to Using SystemC TLM-2.0 IP with UVM Dr David Long and John Aynsley Doulos Ringwood, UK Doug Smith Doulos Austin, Tx, USA www.doulos.com ABSTRACT UVM 1.x includes support for the communication
More informationReplacement Policy: Which block to replace from the set?
Replacement Policy: Which block to replace from the set? Direct mapped: no choice Associative: evict least recently used (LRU) difficult/costly with increasing associativity Alternative: random replacement
More informationESE Back End 2.0. D. Gajski, S. Abdi. (with contributions from H. Cho, D. Shin, A. Gerstlauer)
ESE Back End 2.0 D. Gajski, S. Abdi (with contributions from H. Cho, D. Shin, A. Gerstlauer) Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu 1 Technology advantages
More informationSystem Simulator for x86
MARSS Micro Architecture & System Simulator for x86 CAPS Group @ SUNY Binghamton Presenter Avadh Patel http://marss86.org Present State of Academic Simulators Majority of Academic Simulators: Are for non
More informationCoFluent Design FPGA. SoC FPGA. Embedded. Systems. HW/SW
CoFluent Design www.cofluentdesign.com Embedded HW/SW Systems SW SoC FPGA FPGA Integration Systems & Verification of GreenSocs Models in a CoFluent Testbench jerome.lemaitre@cofluentdesign.com NASCUG IX,
More informationOCCN: A Network-On-Chip Modeling and Simulation Framework. M.Coppola, S.Curaba, M.Grammatikakis, R.Locatelli, G.Maruccia, F.Papariello, L.
OCCN: A Network-On-Chip Modeling and Simulation Framework M.Coppola, S.Curaba, M.Grammatikakis, R.Locatelli, G.Maruccia, F.Papariello, L.Pieralisi Outline Introduction SoC trends SoC: Towards a NoC centric
More informationWorkshop 1: Specification for SystemC-AADL interoperability
Workshop 1: System Design in Avionics & Space Specification for -AADL interoperability Eugenio Villar Eduardo de las Heras Microelectronic Engineering Group University of Cantabria Outline Motivations
More informationTolerating Malicious Drivers in Linux. Silas Boyd-Wickizer and Nickolai Zeldovich
XXX Tolerating Malicious Drivers in Linux Silas Boyd-Wickizer and Nickolai Zeldovich How could a device driver be malicious? Today's device drivers are highly privileged Write kernel memory, allocate memory,...
More informationA Methodology for NoC
OCCN On-Chip Communication Architecture OccN A Methodology for NoC AST Grenoble Marcello Coppola Outline SoC today NoC OCCN Case study Conclusion Soc Today: A Variety of Networks & Terminals Ad-Hoc-Net
More informationThe Metaport. A Technique for Managing g Code Complexity. Jack Donovan HighIP Design Company
The Metaport A Technique for Managing g Code Complexity Jack Donovan HighIP Design Company jackd@highipdesign.com Outline Context, Motivation, and Definition Overview of An Example Example Code Snippets
More informationPorting AMS to RTEMS. Utilizing the Operating System Abstraction Layer (OSAL) David Edell
Porting AMS to RTEMS Utilizing the Operating System Abstraction Layer (OSAL) David Edell Overview What is AMS? VxWorks vs RTEMS What is OSAL? APL AMS Implementation (history) Porting to OSAL in VxWorks
More informationVertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation)
Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation) Pranav Kumar, Staff Engineer Digvijaya Pratap SINGH, Sr. Staff Engineer STMicroelectronics, Greater NOIDA,
More informationVALE: a switched ethernet for virtual machines
L < > T H local VALE VALE -- Page 1/23 VALE: a switched ethernet for virtual machines Luigi Rizzo, Giuseppe Lettieri Università di Pisa http://info.iet.unipi.it/~luigi/vale/ Motivation Make sw packet processing
More informationA Distributed Network Architecture for PC-Based Telemetry Systems
A Distributed Network Architecture for PC-Based Telemetry Systems by Paul A. Thoreson, Lockheed Martin Telemetry & Instrumentation Presented to Ground Systems Architectures Workshop February 26, 1997 frank:/550/gndsysws
More informationAdvanced Computer Networks. End Host Optimization
Oriana Riva, Department of Computer Science ETH Zürich 263 3501 00 End Host Optimization Patrick Stuedi Spring Semester 2017 1 Today End-host optimizations: NUMA-aware networking Kernel-bypass Remote Direct
More informationKnut Omang Ifi/Oracle 6 Nov, 2017
Software and hardware support for Network Virtualization part 1 Knut Omang Ifi/Oracle 6 Nov, 2017 1 Motivation Goal: Introduction to challenges in providing fast networking to virtual machines Prerequisites:
More informationEasy Steps Towards Virtual Prototyping using the SystemVerilog DPI
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI Dave Rich Mentor Graphics, Inc. Fremont, CA dave_rich@mentor.com Abstract The hardware and software worlds have been drifting apart ever
More informationTLM-2 Base Protocol Analysis for Model-Driven Design
TLM-2 Base Protocol Analysis for Model-Driven Design Salaheddine Hamza Sfar and Rached Tourki Department of physics, electronic and microelectronic lab Faculty of sciences at Monastir Monastir, Tunisia
More informationImplementing Multicast Using DMA in a PCIe Switch
Implementing Multicast Using DMA in a e Switch White Paper Version 1.0 January 2009 Website: Technical Support: www.plxtech.com www.plxtech.com/support Copyright 2009 by PLX Technology, Inc. All Rights
More informationPrecision Time Protocol, and Sub-Microsecond Synchronization
Linux Foundation End User Summit May 1, 2012 Precision Time Protocol, and Sub-Microsecond Synchronization Mike Kravetz IBM Linux Technology Center kravetz@us.ibm.com 2009 IBM Corporation Agenda Background/History
More informationThe Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006
The Use Of Virtual Platforms In MP-SoC Design Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006 1 MPSoC Is MP SoC design happening? Why? Consumer Electronics Complexity Cost of ASIC Increased SW Content
More informationIntegrating Instruction Set Simulator into a System Level Design Environment
Integrating Instruction Set Simulator into a System Level Design Environment A Thesis Presented by Akash Agarwal to The Department of Electrical and Computer Engineering in partial fulfillment of the requirements
More informationFunctional Verification of the SiCortex Multiprocessor System-on-a-Chip. Oleg Petlin, Wilson Snyder
Functional Verification of the SiCortex Multiprocessor System-on-a-Chip Oleg Petlin, Wilson Snyder wsnyder@wsnyder.org June 7, 2007 Agenda What we ve built Verification challenges Verification productivity
More informationBetter Approach To Mobile Adhoc Networking
Better Approach To Mobile Adhoc Networking batman-adv - Kernel Space L2 Mesh Routing Martin Hundebøll Aalborg University, Denmark March 28 th, 2014 History of batman-adv The B.A.T.M.A.N. protocol initiated
More informationRTD cpumodule LX-Series Migration Guide
RTD cpumodule LX-Series Migration Guide ISO9001 and AS9100 Certified SWM-640000023 Rev. D Page 1 of 9 Revision History Rev. A 02/29/2007 Preliminary Draft Rev. B 06/23/2008 Added information about the
More informationStandardized Firmware for ARMv8 based Volume Servers
presented by Standardized Firmware for ARMv8 based Volume Servers UEFI Spring Plugfest March 29-31, 2016 Presented by Jonathan Zhang, Robert Hsu Cavium Inc. & AMI Updated 2011-06-01 UEFI Plugfest March
More informationCosimulation of ITRON-Based Embedded Software with SystemC
Cosimulation of ITRON-Based Embedded Software with SystemC Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada Graduate School of Information Science, Nagoya University Information Technology
More informationNoC Generic Scoreboard VIP by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions
NoC Generic Scoreboard VIP by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions Abstract The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects
More information2. System Interconnect Fabric for Memory-Mapped Interfaces
2. System Interconnect Fabric for Memory-Mapped Interfaces QII54003-8.1.0 Introduction The system interconnect fabric for memory-mapped interfaces is a high-bandwidth interconnect structure for connecting
More informationAbstraction Layers for Hardware Design
SYSTEMC Slide -1 - Abstraction Layers for Hardware Design TRANSACTION-LEVEL MODELS (TLM) TLMs have a common feature: they implement communication among processes via function calls! Slide -2 - Abstraction
More informationProjects on the Intel Single-chip Cloud Computer (SCC)
Projects on the Intel Single-chip Cloud Computer (SCC) Jan-Arne Sobania Dr. Peter Tröger Prof. Dr. Andreas Polze Operating Systems and Middleware Group Hasso Plattner Institute for Software Systems Engineering
More informationEEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools
EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw March 2013 Agenda Introduction
More informationModeling Software with SystemC 3.0
Modeling Software with SystemC 3.0 Thorsten Grötker Synopsys, Inc. 6 th European SystemC Users Group Meeting Stresa, Italy, October 22, 2002 Agenda Roadmap Why Software Modeling? Today: What works and
More informationA novel way to efficiently simulate complex full systems incorporating hardware accelerators
ARM Research Summit 2017 Workshop A novel way to efficiently simulate complex full systems incorporating hardware accelerators Nikolaos Tampouratzis Technical University of Crete, Greece Motivation / The
More informationLong Term Trends for Embedded System Design
Long Term Trends for Embedded System Design DSD 2004 A. A. Jerraya TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble Cedex France Tel: +33 476 57 47 59 Fax: +33 476 47 38 14 Email: Ahmed.Jerraya@imag.fr
More informationInterconnecting Components
Interconnecting Components Need interconnections between CPU, memory, controllers Bus: shared communication channel Parallel set of wires for data and synchronization of data transfer Can become a bottleneck
More informationTim Kogel. June 13, 2010
Generating Workload Models from TLM-2 2.0-based Virtual Prototypes for Efficient Architecture Performance Analysis Tim Kogel NASCUG 13 June 13, 2010 1 Outline Motivation and TLM-2.0 Virtual Prototyping
More informationA Flexible SystemC Simulator for Multiprocessor Systemson-Chip
A Flexible SystemC Simulator for Multiprocessor Systemson-Chip Luca Benini Davide Bertozzi Francesco Menichelli Mauro Olivieri DEIS - Università di Bologna DEIS - Università di Bologna DIE - Università
More informationLEON2/3 SystemC Instruction Set Simulator
LEON2/3 SystemC Instruction Set Simulator Luca Fossati Luca.Fossati@esa.int European Space Agency Outline 1 LEON2/3 IP Model Contract Aim 2 Instruction Set Simulator 3 Results 4 Conclusion 1 / 17 Overview
More informationXen VT status and TODO lists for Xen-summit. Arun Sharma, Asit Mallick, Jun Nakajima, Sunil Saxena
Xen VT status and TODO lists for Xen-summit Arun Sharma, Asit Mallick, Jun Nakajima, Sunil Saxena R Outline VMX Guests Status Summary Status Domain0 restructuring PCI/IOAPIC X86-64 VMX guests enhancements
More information