Integrated Development Environment

Transcription

1 Integrated Development Environment 1

2 IDE Page 2 2

3 Toolchains IDE AndESLive Simulator AICE AndESLive Builder AndeShape AndeSight AndESLive Page 3 3

4 AndeSight IDE Window View Perspective Editor Preferences Help Advanced features Page 4 4

5 Andes Total SW Solution user Integrated Development Environment (IDE) AndeSight SoC Builder Simulation Engine AndESLive Toolchains: Compiler Assembler Linker Debugger AndeShape ICE Evaluation Board Andes SW Solution = AndESLive + AndeSight + AndeShape Page 5 5

6 Integrated Development Environment Toolbar Page 6 6

7 Windows What is window The overall outer frame New window Menu bar Window New Window Same workspace and perspective Start another AndeSight Different workspace Page 7 7

8 Windows Page 8 8

9 Views What is view View provides alternative presentations as well as ways to navigate the information in your Workbench. Page 9 9

10 Views Page 10 10

11 Perspectives What is perspective The initial set and layout of views in the Workbench window. Each perspective provides a set of functionality aimed at accomplishing a specific type of task or works. We provide C/C++ coder Debug VEP Config (Andeslive) Profiling Page 11 11

12 Perspectives Page 12 12

13 Perspectives Debug and Profiler Page 13 13

14 Perspectives VEP (Virtual Evalution Platform) Config Page 14 14

15 Perspectives Others Page 15 15

16 Editor Editors we provide C/C++ Makefile Assembly Binary Hex VEP Page 16 16

17 Features of C/C++ Editor Content assistant Function Definition Auto completion Syntax highlight Formatter Page 17 17

18 Content assistant Page 18 18

19 Show Function Definition Page 19 19

20 Text Auto Completion Page 20 20

21 Template Support Page 21 21

22 Formatter Page 22 22

23 Preferences What settings are provided? Is used to set user preferences Can be searched using the filter function Page 23 23

24 Preferences Page 24 24

25 Preference to Change Fonts Page 25 25

26 Commands and Functions Page 26 26

27 Help System Context sensitive help Hot key: F1 Help Content Search Page 27 27

28 Profiling Andesight IDE Trigger Profiling Prof.out Profiling data preparation Profiling Analysis Engine Andeslive Simulator Page 28 28

29 Profiling Options Function Level Pure function profiling without branch and cache information With Branch Summary With Cache Summary With Branch and Cache Summary Branch Level Pure branch profiling without cache information With Cache Summary Views Flat View Call View Timeline View Chart View C and C++ Support Fast Mode and Extended Mode Goto Source Page 29 29

30 Profiling Options Page 30 30

31 Performance Tuning Co-Sim Tune Performance by CPU Configuration Profiling Meet Spec. No Yes END Tune Performance by Software Works Page 31 31

32 Tune Performance by Profiler Profile Result of 8KB I$/D$ Profile Result of 64KB I$/D$ Page 32 32

33 Profiling Timeline View Page 33 33

34 Profiling Call View Page 34 34

35 Profiling Flat View Page 35 35

36 Branch Level with Cache Summary Page 36 36

37 Build Options Page 37 37

38 Endian SW SW endian setting gives EL or EB option to compiler Page 38 38

39 Endian HW HW endian setting gives option to simulator Page 39 39

40 Library SW SW library setting gives mlib option to linker Page 40 40

41 Library HW HW library setting should enable Virtual IO support and select proper library for simulator Window > Show View > Other VEP > System Call Emulation Page 41 41

42 Toolchain SW Toolchain includes one for hardcore, one for softcore Page 42 42

43 CPU Selection Virtual SoC Builder provides one hardcore and one softcore Page 43 43

44 Virtual Platform Introduction From physical to virtual and vice versa Page 44 44

45 What is Virtual Platform? It is a system-level simulation model that characterizes real system behavior. It operates at the level of processor instructions, function calls, memory accesses and data packet transfers, as opposed to the bit-accurate, nanosecond-accurate logic transitions of a register transfer level (RTL) model. * Andes Development Platform Andes Virtual Platform *from the book ESL Design and Verification: A Prescription for Electronic System Level Design Methodology. B. Bailey, G. Martin and A. Piziali. Elsevier Morgan Kaufmann, 2007 Page 45 45

46 S/W Development with Physical H/W Platform SW Developer Desktop Target Hardware Integrated Development Environment Other plug-in tools CM Profiling Tools Debugger Build Compiler Source Code Analysis Editor Applications Applications Middleware Middleware Operating Systems Operating Systems BSP/Device Drivers BSP/Device Drivers DEVICE SOFTWARE STACK PHYSICAL HARDWARE Physical Target Connection On-Chip-Debug, Ethernet, USB, External System Connectivity Page 46 46

47 S/W Development with Virtual Platform SW Developer Desktop Integrated Development Environment Other plug-in tools CM Profiling Tools Debugger Build Compiler Source Code Analysis Editor Tools/API Applications Applications Middleware Middleware Operating Systems Operating Systems BSP/Device Drivers BSP/Device Drivers DEVICE SOFTWARE STACK Virtual Platform External System Connectivity Page 47 47

48 Andes Virtual Evaluation Platform Page 48 48

49 Andeshape Platform SoC: AG101 N1213 Bus Controller MAC USB2.0 10/100 AHB Bus LCD Controller PWM II 2 C SDRAM Controller GPIO INTC DMA Controller WDT Timer SRAM Controller RTC AHB to APB Bridge APB Bus Power Manager ST UART BT UART SSP CF II 2 S SD/ MMC Page 49 49

50 Virtual Evaluation Platform Page 50 50

51 S/W Development with Andes Tools SW Developer Desktop (AndeSight) Integrated Development Environment Other plug-in tools SOC Builder Profiler Debugger Program Builder Compiler Assembler Editor AndESLive/API AndeSoft Applications Applications Middleware Middleware Operating Systems Operating Systems BSP/Device Drivers BSP/Device Drivers DEVICE SOFTWARE STACK VEP (AndESLive) Virtual I/O Connectivity Page 51 51

52 AndeESLive VEP Environment User-defined Models Peripheral IP Models AndesCore Model Customer SoC Andes AG101 AndESLive VEP module Module descriptor SID component C/C++ Page 52 52

53 VEP Module slave port User-defined Models Essential IP Models AndesCore Customer SoC Andes AG101 AndESLive write port VEP module Module descriptor SID component C/C++ read port master port bus port Page 53 53

54 Andes VEP (a quick summary) SID, an open-source framework for building simulated Embedded Systems, has been integrated into AndESLive as backbone simulator Simulated component, or a SID component, can be written in C/C++, or Tcl to which the SID API is bound VEP module is a SID component wrapped with XMLbased Module Descriptor in which the parameters and attributes are described Andes provides sample code (C++-based) and SID example for modeling target (bus slave) and initiator (bus master) components that run on Andeslive Depending on the requirements from customers, Andes can provide Modeling Training and Services as well Page 54 54

55 SID Simulator The AndESLive simulation backbone Page 55 55

56 SID Overview The SID simulator consists of an engine that loads and connects simulated components, based on a simulator configuration file, and runs simulation sessions. The SID simulator configuration file is a text file that configures a SID simulation run. The configuration file defines the simulation contents, connections, and initial states. SID comes with a number of simulated components (or SID components), each of which can be modified, configured, or connected to any other independently. Adding new components is straightforward and does not require any modifications to SID. More info on SID Component Library, refer to the SID Component Developer s Guide. While running a simulation, SID can interface with standard I/O, such as a Tk-based visual simulation monitor, the gdb debugger, and the gprof profiler. Page 56 56

57 SID Architecture (1 of 2) SID is a simulation framework for supporting embedded systems software development. SID features a modular architecture of loosely-coupled software components that interact with each other to simulate the behavior of physical hardware parts. SID components share a fixed low-level API, which defines all possible inter-component communication mechanisms. SID is packaged as a standalone command-line program that reads and executes a configuration file. A typical session with SID begins with compiling or assembling code for the simulated system to run, using standard cross-development toolchain, and proceeds through loading the target binary into the simulation environment. Page 57 57

58 SID Architecture (2 of 2) Four Component Types are supported in SID Hardware model (hw-xxx) Software model (sw-xxx) Bridge (Tcl/Tk bridge) Special function (event scheduler, host network interface, etc) Communication mechanisms between Components: SID API is used to model these mechanisms: pin, bus, attribute, and relation The SID API can be thought as the socket on a circuit board. The SID Component is like the IC that plugs into these sockets and the SID simulator configuration file is like the circuit wiring that connects the sockets to each other Page 58 58

59 SID Configuration File The configuration file consists of three major sections: A listing of component libraries to be loaded (dynamically loaded libraries) load A command to instantiate components new A set of commands that connect and configure the components set connect-pin, disconnect-pin (point-to-pint) connect-bus, disconnect-bus (broadcast) relate, unrelate Page 59 59

60 Component Connection in SID CPU (master) out1 read port in1 Timer (slave) write port connect-pin CPU out1 -> Timer in1 CPU (master) bus slave port Memory (slave) system-mem (accessor) bus master port port data-bus (bus) connect-bus CPU system-mem Memory data-bus Page 60 60

61 SID Component Modeling Page 61 61

62 Basic Component Outline (Class Declaration) #include <sidcomp.h> #include <sidtypes.h> #include <iostream> using sid::component; using sid::host_int_4; SID and C++ header files Namespace using class sp_timer : public virtual component { public: sp_timer(); ~sp_timer() throw() {}; Declare this class as SID component and use other predefined utilities protected: input_pin a, b, c; output_pin d, e, f; Data I/O private: in_out_handler(); } Page 62 Inaccessible data and function 62

63 Component Declaration (1/3) common header files & utility Header files sidattrutil.h sidbusutil.h sidcomp.h sidcomputil.h sidmiscutil.h sidpinattrutil.h sidpinutil.h sidscheutil.h sidtypes.h sidwatchutil.h Tens of utilities For simplicity issue using namespace sid; using namespace sidutil Page 63 63

64 Component Declaration (2/3) class inheritance class sp_timer : public virtual component //each component class need to inherit from this, public fixed_attribute_map_component //if the component provide configure attribute such as verbose? else use // no_attribute_map_component, public fixed_pin_map_component //if the component provide input/output pin else use no_pin_map_component, public fixed_bus_component //if the component provide bus access else use no_bus_map_component, public no_relation_component //no relation utility requirement, public no_accessor_component //not a bus master Page 64 64

65 Component Declaration (3/3) Data I/O //input type input_pin din_pin; friend class callback_pin<sp_timer>; callback_pin<sp_timer> rst_pin; //output type output_pin intr_pin; //clock type (connected to scheduler) friend class scheduler_event_subscription<sp_timer>; scheduler_event_subscription<sp_timer> clk; Page 65 65

66 Integrating SID Component in AndESLive Wrapping SID component with VEP module 66

67 Integrating SID Component in AndESLive Wrapping SID component with VEP module Page 67 67

68 Integrating Component in AndESLive To integrate SID component in AndESLive, an XML-based component descriptor is created for each component. The component descriptor defines the properties to be used in AndESLive (such as bus, pin, and attributes) write port slave port VEP module component descriptor SID component read port Once the user-defined component descriptor is completed, save the XML file in the folder: $ANDESIGHT_ROOT/vep/component/user master port bus port Page 68 68

69 Sample Component Descriptor Component Definition: <defcomponent name="hw-sample" shortname="sample" type="sid"> <sid-lib dlsym="sample_component_library" name="libsample.la" /> Bus Definition: <busmaster name="master" type="ahb"/> <busslave name="registers" type="ahb"/> Pin Definition: <defpins name="sample-out-" from="0" to="5" direction="out"/> <defpins name="sample-in-" from="0" to="5" direction="in"/> Page 69 69

70 Questions We want to know how a component is modeled in AndESLive and what language/description by which the modeling is based upon? Where can we find the document/tutorial for modeling user-defined components and if Andes can provide modeling training/services? Will Andes support SystemC as a modeling constructor and what if we have SystemC models, how can we incorporate them into AndESLive? Page 70 70

71 Answers We The behavior want to know of user-defined how a component model can be is written modeled in in AndESLive C/C++ and the and SID what API is language/description used to compose a SID by which component the modeling by which a is VEP-based upon? module is created that runs on AndESLive. There is a document in User Manual (release 1.3.1) for Where creating can a user-defined we find the model. document/tutorial Tutorial is also being for modeling user-defined components and if Andes can provide modeling training/services? prepared as well as application notes. Andes can provide modeling training and/or services based on customer requests. In the current release (1.3.2), SystemC modeling/import Will Andes support SystemC as a modeling is NOT supported in AndESLive. Andes is now interface and what if we have SystemC models, how can we incorporate them into AndESLive? developing SID-SystemC bridge which can communicate SystemC interface with SID-based pin and bus. Untimed SystemC models will be supported first. Page 71 71

72 SystemC Modeling How VEP can be used in Development Cycle Enable early S/W development Page 72 72

73 VEP Use Models VEP as an Early (or pre-silicon) Software Development and Software Validation Platform Reduce SW bring-up and system test time Ideally start SW dev. in parallel to HW dev. Leave more time for SW dev. and quality assurance VEP as an Architecture Exploration Platform Evaluate HW/SW configuration and/or system partitioning Optimize system architecture VEP as a RTL Verification Platform Golden reference models for functional verification Verify architecture and system validation Page 73 73

74 VEP as Early SW Development & Validation VEP can be used for developing & testing SW (only if the VEP can run as fast as HW board does) Low-level device drivers and kernel OS and middleware porting App. SW development One scenario is as follows: SW team extends existing device drivers based on updated IP spec At the same time, Platform team enhances/creates models (ex. new features added) based on the VEP SW team completely debugs and tests the driver functionality early on the VEP SW bring-up in a shorter time after the HW (FPGA) is available Page 74 74

75 Development Cycle Impact Traditional (or Past) Approach: Platform Specification Hardware Development SW Development (OS & Device Driver Dev, Apps Dev) Integration & Bring-up Debug Final System Testing VEP-based Approach: Platform Specification SW Development Scalable VEP Pre-silicon System Test Hardware Development Integration Bring-up Debug Final System Testing Enable Early SW Development Enable Scalable Development Pre-Silicon System Test Reduce Bring-up time Reduce Post-Silicon System Test Scalable Development Reducing bring-up and final system test time Page 75 75

76 VEP as Architecture Exploration VEP can be used to explore design alternatives to determine the appropriate architecture (or system) Some alternatives to evaluate are: AndesCore configuration Cache, MMU, Local memory, branch prediction, etc SW profiling (in AndESLive) code optimization HW/SW partitioning HW accelerator engine or SW oriented Performance and cost tradeoff Bus Matrix or Multi-layer currently NOT supported in AndESLive Page 76 76

77 VEP as RTL Verification Currently NOT supported in AndESLive! Team-up Partnership possibilities GUC (porting AndesCore ISS with SystemC TLM2.0) EVE (compiling AndesCore on ZeBu) CoWare (porting AndesCore ISS with SystemC/AMBA) Carbon (porting AndesCore ISS with CASI/SystemC) Cadence/Synopsys/Mentor Speed is always an important concern and incentive Transaction-based interface is the key HW accelerator/emulator may be too expensive to be justified Page 77 77

78 Thank You!!! 78