SCOC3 (Spacecraft Controller On Chip) ESTEC, Noordwijk, 7 th and 8 th March 2007

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Augustus Godfrey Welch
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1 COC3 (pacecraft Controller On Chip) ETEC, Noordwijk, 7 th and 8 th arch 2007 Page 1 COC3 - ETEC - PD 7th/8th arch 2007

2 Contents 1. Project history 2. Project applications 3. Activities 4. CoC3 specification (main outlines) 5. CoC3 architecture 6. CoC3 /W 7. CoC3 development methodology (including testability/validation) 8. Planning 9. Conclusions Page 2 COC3 - ETEC - PD 7th/8th arch 2007

3 1) Project history CoC1 : First contract 2000: EA contract called "Building Blocks for ystem on a Chip" to: Define a methodology for the integration of system within an AIC Design a large COC1 AIC through FPGA prototyping based on LEON1. Contract stopped at FPGA prototyping step CoC2 : ATRIU CoC2 development continuation based on LEON2 with AEVA FPGA prototype board to improve the architecture and develop new IPs CoC3 : The aim of the current EA contract CoC3 is a continuation process: by moving to the LEON3 and improving the architecture in terms of performance, by developing new IPs and improving existing IPs to simulate and validate the CoC3, to assess the gate level design phase by performing synthesis and static timing analysis on a selected technology. Page 3 COC3 - ETEC - PD 7th/8th arch 2007

4 2) Project Applications ain issue: P/F applications Telecommunication satellites: High Reliability Earth Observation and cience satellites: From High Reliability to simplex implementation icro satellites with same reliability factor as EO & cience but also low cost approach Others like Probes, Launchers, Navigation, Formation flying, Page 4 COC3 - ETEC - PD 7th/8th arch 2007

5 3) Activities Phase 1 (TRP) Financing EA EA ATRIU ATRIU Tasks Initial analysis and requirement specification Architectural design: Architecture study of block interconnect scheme Functional specification of the IP macros Development / modification for adaptation of the IP macros imulation at VHDL RTL level / Environment developed in VHDL on a «standard» basis /W development (drivers, boot, self-tests, ) OC approach is verified / debugged on a FPGA demonstration board with OC function integrated in a reprogrammable FPGA: Activity performed in parallel with the simulation and /W development Progressive integration of the IP macros Page 5 COC3 - ETEC - PD 7th/8th arch 2007

6 3) Activities Phase 2 (GTP under construction) Financing EA EA ATRIU Tasks Asic back-end Foundry Board validation Page 6 COC3 - ETEC - PD 7th/8th arch 2007

7 4) CoC3 pecification AOC/Data Handling on single chip including I/O (1553, pw, CAN, UART, ), CCD TC, CCD T, CCD Time ngt Processor LEON3-FT with GRFPU-FT at 120 Hz ABA architecture Power management IP onitor: ABA statistics and trace ature technology: ATC18RHA with qualified package BGA472 Page 7 COC3 - ETEC - PD 7th/8th arch 2007

8 5) COC3 Architecture The processor bloc is based on LEON3 µp with GRFPU, a memory controller, UART and pacewire interfaces communicating via the CPU-AHB ABA bus The on-board I/O subsystem providing UART, CAN, pw, IL1553 BC/RT. Data exchanges are of DA type in the I/O memory The T/TC subsystem provides one packet telemetry encoder (PTE) and one telecommand decoder (TCDA) unit, with AP interface The CCD time generator and an event switch matrix, clock and reset distribution, debug support Page 8 COC3 - ETEC - PD 7th/8th arch 2007

9 5) COC3 Architecture CPU EORY TCDA AP TC R & CONF pw 1 APBR CPU LEON3/ GRFPU Inst/Data Cache DU Inst TraceBuffer AHBTraceBuffer LEON3 CTL (RA, DRA) TTC APB CPU APB CPU AHB BU (arbiter, decoder) PTE APBR TTC HDA AHBR 2nd IRQ controller UART 1 UART 2 VC0-6 VC7-Idle pw 2 pw 3 TraceBuffer tatsbuffer IP onitor IO AHB BU (arbiter, decoder) APBR IO IO CTL (RA, DRA, PROs) IO EORY HKPF IO APB Ccsds Timeng IC Clock & Reset UART GP1 UART GP2 CAN 1 CAN 2 pw JTAG & CAN CPU function T/TC function IO functionalities General ain clock/other clock interface IO Count: 307 Gates Count: 900 kgates Date: 2007/03/07 PD EA Page 9 COC3 - ETEC - PD 7th/8th arch 2007

10 5) COC3 Architecture - ain IP block module LEON3-FT PARC µp IP U, GRFPU-FT AHB/APB odule pacewire IP with RAP functionality CCD T IP CCD TC IP CCD Time ngt IP ource Gaisler Research EAD Astrium EA EAD Astrium EA 1553 IP EAD Astrium CAN IP UART IP emory Controller IP (RA, DRA) iscelaneous (AHB/AHB, Clocks, Housekeeping) onitor IP (real time debug and tests) EA Gaisler Research EAD Astrium EAD Astrium EAD Astrium Page 10 COC3 - ETEC - PD 7th/8th arch 2007

11 5) COC3 Architecture - Operating modes Full mode - COC3 acts as spacecraft main computer Processor and I/O only - COC3 can be used for payload data handling and processing T/TC only - COC3 can replace a conventional T/TC subsystem using discrete components Processor and T/TC - COC3 can be used as main computer next to a separate on-board communication structure Page 11 COC3 - ETEC - PD 7th/8th arch 2007

12 6) CoC3 oftware Drivers with IPs Development environment based on C Tools: GRON, TI, CoC3 simulator created RTE and/or VxWORK Operating ystem ervice Interface software Reuse of DH layers from Pleïades or Bepi-Colombp Page 12 COC3 - ETEC - PD 7th/8th arch 2007

13 7) CoC3 Development methodology OC Design leads to find out solutions for: tandardization of the interfaces, internal and external Internal for easy interconnect of IP based on the use of a catalogue of IP External to reduce the number of IP to develop Current standardization of the methodology of validation of OC model (RTL) Hardware/oftware Co-simulation with proprietary solutions Prototype of the CoC on FPGA and deliver to users/software developers models imulation remains simulation and only emulates the use of the OC in modelled environment Accelerate the bug discovery CoC validation in equipment environment Page 13 COC3 - ETEC - PD 7th/8th arch 2007

14 8) CoC3 planning Phase 1: Phase 2: Under discussion Page 14 COC3 - ETEC - PD 7th/8th arch 2007

15 9) Conclusion Product: On Board Computer core low power/low cost/ low volume ethodology: Ever improving the reuse from IPs and standard bus oftware: Development improved using commercial tools and could be provided with dedicated software support Integration: One AIC allowing different operating modes and several architecture Contacts: Roland Weigand ETEC roland.weigand [at] esa.int Franck Koebel EAD Astrium franck.koebel [at] astrium.eads.net arc ouyri EAD Astrium marc.souyri [at] astrium.eads.net Jean-Francois Coldefy EAD Astrium jean-francois.coldefy [at] astrium.eads.net Page 15 COC3 - ETEC - PD 7th/8th arch 2007

Building Blocks For System on a Chip Spacecraft Controller on a Chip

Building Blocks For System on a Chip Spacecraft Controller on a Chip PIO/TEST/WDOGN/ 19 ERRORN 2 Clock, Reset CT_PULSE CT_EVENT 4 4 4 SWB0 : Space Wire SWB1 : Space Wire SWB2 : Space Wire HKP Housekeeping Packetizer Context RA CT CCSDS Time anager SWT SWITCH ATRIX IT from