Next Generation Multipurpose Microprocessor. Activity Overview

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1 Next Generation ultipurpose icroprocessor Activity Overview DAIA 2010 June 1st,

2 Overview NGP is an EA activity developing a multi-core system with higher performance compared to earlier generations of European pace processors Part of the EA roadmap for standard microprocessor components Aeroflex Gaisler's assignment consists of specification, the architectural (VHDL) design, and verification by simulation and on FPGA An FPGA prototype will be delivered by the end of 2010 and followed by synthesis on AIC technology This presentation is an overview of the first part of NGP development and covers: chedule Overview of the hardware architecture New features, target technology, open items oftware support (toolchains, Os, drivers) Additional development support (debugger, I) 2

3 Development chedule Aug 2009: Kick-off Feb 2010: Definition and specification June 2010: First versions of FPGA prototypes Dec 2010: Final RTL code, FPGA Demonstrator Aug 2011: Verified AIC netlist anufacturing of prototype parts not yet decided Development of flight model in a separate contract 3

4 Architectural Overview Quad-core with GR floating point units 128-bit L1 caches, 128-bit bus 256 KiB L2 cache, 256-bit cache line, 4-way LRU 64-bit DDR2-800/DR-PC100 DRA memory interface 32 ib on-chip DRA (if feasible) 4x GRPW2 pacewire 200 bit/s 32-bit, 66 Hz interface 2x 10/100/1000 bit 4x HL (if available on target technology) Debug links:, JTAG, UB, dedicated pw RAP target Target frequency: 400 Hz aximum power consumption: 6W. Idle power 100 mw. 4

5 Architectural Overview 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 5

6 Architecture Processor bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 6

7 Architecture emory bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 7

8 Architecture I/O buses 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 8

9 Architecture lave I/O bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 9

10 Architecture aster I/O bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 10

11 Architectural Overview Debug bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 11

12 Architecture Processor bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 12

Architecture - IEEE-1754 PARC V8 compliant 32-bit processor 7-stage pipeline, multi-processor support eparate multi-set L1 caches with LRU/LRR/RND, 4-bit parity 64-bit single-clock load/store

13 Architecture - IEEE-1754 PARC V8 compliant 32-bit processor 7-stage pipeline, multi-processor support eparate multi-set L1 caches with LRU/LRR/RND, 4-bit parity 64-bit single-clock load/store operation 64-bit register file with BCH 64- or 128-bit bus interface Write combining in store buffer Branch prediction CA support Performance counters On-chip debug support unit with trace buffer Local timer and interrupt controller 1.7 DIP/Hz, 0.6 Wheatstone FLOP/Hz Estimated 0.35 PECINT/Hz, 0.25 PECFP/Hz 2.1 Coreark/Hz (comparable to AR11) 13

14 Architecture - L2 Cache 256 KiB baseline, 4-way, LRU 256-bit internal cache line with 64-bit BCH ECC Copy-back and write-through operation 0-waitstate pipelined write, 3/4-waitstates read hit upport for locking one more more ways Fence registers for backup software protection Essential for P performance scaling Reduces effects of slower memory (DRA) if DDR2 cannot be used Timers IRQCTRL emory crubber DDR2 AND DRA CTRLs emory bus 400 Hz L2 Cache U U Processor bus On-Chip DRA 14

15 Architecture emory bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 15

16 Architecture - emory scrubber Can access external DDR2/DRA and on-chip DRA Performs the following operations: Initialization crubbing emory re-generation Configurable by software Counts correctable errors with option to alert CPU User can define data pattern used for initialization emory crubber DDR2 AND DRA CTRLs emory bus 400 Hz L2 Cache On-Chip DRA 16

17 Architecture - emory Controllers Primary memory interface: DDR2/DRA DDR2-800/DRA PC bit data 16 and 32 bit Reed-olomon ECC Corrects two or four 4-bit errors On-chip DRA (if available on target tech.) Performance of external interfaces: Interface Cache line fetch (ns) ustainable bandwidth (ib/s) in. sys. freq. (Hz) ax. sys. freq. (Hz) DRA PC DDR

18 Architecture lave I/O bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 18

19 Architecture lave I/O bus cores Uni-directional / bridge Reduced load on Processor bus Performs read/write combining 8/16-bit PRO/IO controller with BCH ECC master slave interface bridges connecting all APB slave interfaces to be used in flight: Timers, s, interrupt controllers, GPIO port, arbiter, clock gating unit, pacewire controller, ACs, interrupt time stamp unit, etcetera All core registers are placed on 4 KiB boundaries 19

20 Architecture aster I/O bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 20

21 Uni-directional bridge with IOU Connects all DA capable I/O master through one interface onto the Processor bus Performs pre-fetching and read/write combining Provides address translation and access restriction Will not be required to use the same page tables as the processor aster can be placed in groups where each group can have its own set of page tables IOU 400 Hz aster DA Target aster IO bus PW PW PW PW HL HL HL HL 21

22 Architecture - pacewire 4x Aeroflex Gaisler GRPW2 cores aximum link bit rate will be at least 200 b/s Hardware RAP target in each core Two ports per core (redundant port) Each core has its own DA engine 22

23 Architecture - interface Provides master/target interface 32-bit interface supporting 66 Hz operation Target DA interface is placed on the aster I/O bus while the slave interface is on the lave I/O bus Target has two bars of sizes 256 ib and 64 ib pecification based on GR core. AG is currently developing a new core which is planned to replace GR. / PRO & IO CTRL CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster 400 Hz DA tatus aster IO bus IOU Target PW PW PW PW HL HL HL HL Arbiter 23

24 High-peed erial Link Design has been specified to include 4 HL cores The High-speed erial Link back-end is TBD Inclusion of HL depends on availability of macros on target technology Current status: Target technology will have erdes macros capable of 6.25 Gbit/s operation AG is working with EA to, at a minimum, be able to provide a simple descriptor based DA cored based on GRETH_GBIT or GRPW2 24

25 Gigabit 2x interfaces upports 10/100/1000 bit in both full- and half-duplex DA engine for both receiver and transmitter Internal buffer allows core to buffer a complete packet upports II and GII interfaces to connect an external transceiver upports scatter gather I/O and IPv4 checksum offloading Provides Debug Communication Link 2 KiB E buffer 100 b/s oft configurable E IP/AC addresses E can also be connected to Debug bus Debug bus 400 Hz aster IO bus 400 Hz 25

26 Architectural Overview Debug bus 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 26

27 Architecture - Cores on Debug bus Debug upport Unit Hardware breakpoints/watchpoints upports debugging multiple cores in parallel Used to monitor processor status Interface to instruction and (Processor bus) trace trace buffer trace buffer monitoring aster I/O bus APB bridge allows direct access to LEON4 statistics unit Wide range of debug communication links 32-bit 400 Hz LEON4 PERF. CNT. DU TRACE Debug bus 400 Hz / TRACE RAP JTAG UB 27

28 Debug Communication Links JTAG Debug Communication Link RAP target Bandwidth: 20 b/s Provides DU access over pw UB Debug Communication Link Bandwidth: 500 kb/s Bandwidth: 20 b/s Debug Links Bandwidth: 100 b/s Can optionally be connected to master I/O bus 28

29 Improved Debugging upport The NGP will have improved debugging support compared to the LEON2FT and many existing LEON3 implementations. The new features include: everal high-speed debug interfaces Non-intrusive debugging through dedicated Debug bus trace buffer with filtering Instruction trace buffer with filtering Hardware data watchpoints Data area monitoring 29

30 Improved Profiling upport (1) The NGP has improved profiling support compared to the LEON2FT and LEON3. The new features allow to measure the following metrics: Processor statistics Instruction/Data cache/tlb miss/hold Data write buffer hold Total/Integer/FP instruction count Branch predication miss Total execution time (excluding debug mode) pecial filters allow counting number of: Integer branches CALL instructions Regular type 2 instructions LOAD and TORE instructions LOAD instructions TORE and instructions 30

31 Improved Profiling upport (2) In addition the processor statistics you can also measure: L2 cache hit/miss rate utilization utilization per master Total utilization Interrupt time stamp unit allows users to measure interrupt handler latencies 31

32 ummary of New Features Features in NGP not found in most present day LEON/LEON-P architectures: Quad core L2 cache with locking Large on-chip RA (32 ib, if available on target) Wider ABA buses Better support for partitioning: IOU Per-processor timers and interrupt cntrlrs Improved debug support (# links, filters, perf. cnt) Improved support for AP Boot options (PRO, RAP) Interrupt time stamping Hardware memory scrubber 32

33 Target technology Baseline is T 65nm space technology Requirements DDR2 PHY I/O standards: LVTTL, TL, emory: 1-port RA, 2-port RA High density 1-port RA/DRA Backup options: UC 90 nm with DARE library Tower 130 nm with Ramon library 33

34 Operating ystems Operating systems that will be ported in this activity: RTE 4.8 and 4.10 WindRiver VxWorks 6.7 with P support ecos 2.0 Linux 2.6 Other Os already ported to LEON include: LynxO (LynuxWorks) Thread (Express Logic) Nucleus (entor Graphics) 34

35 Toolchain The GNU C/C++ toolchain will be used Versions and have been successfully tested OpenP requires GCC 4.4+ and a pthreads implementation RTE 4.8 uses GCC 4.2.4, RTE 4.10 uses GCC 4.4 VxWorks 6.7 uses GCC KPRO2 with support for booting P and AP systems 35

36 imulator NGP simulator based on GRI C models of IP cores linked into a final simulator LEON4 L2 cache and DDR memory interface GRPW, GRETH, GR Reentrant and thread safe library Accuracy goal is above 90% over an extended simulation period 36

37 Debug tools NGP will be fully supported by the GRON debug monitor Complemented by standard RTO trace tools 37

38 Thank you for listening For updates and to download the NGP specification, please see: 38

39 ETRA LIDE 39

40 election of Open Items Choices that are still open include: On-chip DRA (desirable but not likely to be included) 2 or 4 CPU cores hared or individual s (3 possible configurations) External memory type (DDR/DDR2) Configurable DRA width (32/64 data bits) L1/L2 cache size IOU implementation High-speed interfaces Different frequencies of processor bus and other buses pare-column of external memory 40

41 Fault-Tolerance ummary Fault-tolerance in the NGP system is aimed at detecting and correcting EU errors in on-chip and offchip RA L1 cache and register files in are protected using parity and BCH L2 cache will use BCH External DRA will be protected using Reed-olomon Boot PRO will use BCH RA blocks in on-chip IP cores will be protected using BCH or TR, smaller buffers can be synthesized as flipflops Flip-flops will be protected with EU-hardened library cells if available or TR otherwise 41

42 Architecture Interrupt infrastructure 32-bit 400 Hz LEON4 PERF. CNT. IRQCTRL1 IRQCTRL2 IRQP = aster interface(s) = lave interface(s) = noop interface IRQCTRL3 IRQCTRL4 32-bit 400 Hz Timers IRQCTRL emory crubber 64-bit DRA DDR2-800/ DR-PC100 DDR2 AND DRA CTRLs PRO IO 8/16-bit PRO & IO CTRL emory bus 400 Hz L2 Cache / On-Chip DRA CLKGATE 400 Hz tatus lave IO bus Timers IRQTAP GPIO aster U U Processor bus U U 400 Hz Target TRACE Debug bus 400 Hz / JTAG TRACE RAP 400 Hz IOU DA Timers IRQCTRL DU UB tatus aster IO bus PW PW PW PW HL HL HL HL Arbiter 42

43 Interrupt infrastructure pecified to support AP and P Internal processor interrupt controllers hared multiprocessor interrupt controller (IRQP) 4x secondary interrupt controllers General topology: econdary IRQCTRL 3 econdary IRQCTRL 4 IRQP econdary IRQCTRL 1 econdary IRQCTRL 2 43

44 Interrupt infrastructure Cont.. IRQP is connected to each processor Each processor has an internal interrupt controller (not used when the processor core is listening to IRQP) Each secondary interrupt controller is connected to IRQP and to each internal interrupt controller. econdary IRQCTRL 3 econdary IRQCTRL 4 IRQP econdary IRQCTRL 1 econdary IRQCTRL 2 44

45 P Configuration All internal interrupt controllers are disabled Processor cores listen to IRQP ask register in IRQP is used to listen to one or several of the secondary interrupt controllers econdary IRQCTRL 3 econdary IRQCTRL 4 IRQP econdary IRQCTRL 1 econdary IRQCTRL 2 45

46 A()P Configuration Processor cores use their internal interrupt controllers IRQP is not used Each processor uses the internal interrupt controllers mask register to listen to one dedicated secondary interrupt controller econdary IRQCTRL 1 econdary IRQCTRL 2 econdary IRQCTRL 3 econdary IRQCTRL 4 46

47 Interrupt infrastructure round-up Infrastructure also allows mixed configurations: 1x P + (1x or 2x) AP ynchronization via interrupts can be achieved via IRQP or by writing the force register of a secondary interrupt controller Each configuration has the same view of the interrupt lines (local timers only available to the processor in which they are located) 47

designs ilinx L510 ynopsys HAP-51 Aeroflex Gaisler

48 Prototypes Investigations into AIC prototypes is currently ongoing FPGA prototypes with reduced NGP designs ilinx L510 ynopsys HAP-51 Aeroflex Gaisler GR-C-C4V with L200 FPGA Aeroflex Gaisler GR--C5V 48

Technical Note on NGMP Verification. Next Generation Multipurpose Microprocessor. Contract: 22279/09/NL/JK

Technical Note on NGMP Verification. Next Generation Multipurpose Microprocessor. Contract: 22279/09/NL/JK NGP-EVAL-0013 Date: 2010-12-20 Page: 1 of 7 Technical Note on NGP Verification Next Generation ultipurpose icroprocessor Contract: 22279/09/NL/JK Aeroflex Gaisler AB EA contract: 22279/09/NL/JK Deliverable: