DFI-PHY DFI 2.1 Pre-configured for major SDRAM vendors including Samsung, LPDDR4 DRAM JESD209-4 Hynix, and Micron

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1 Memory VIP Comprehensive Memory Models Portfolio Today s SoCs and FPGAs utilize advanced DRAM and Flash memory interfaces that are integral to meet their crucial system features and performance requirements. Comprehensive functional and timing verification of these external memory interfaces and chip configurations is essential to ensure the SoCs and FPGAs operate under a broad range of system operating conditions. The Avery memory VIP portfolio implements a complete set of models, protocol checkers, and compliance testsuites utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation. DDR-Xactor DDR-Xactor supports memory models for the JEDEC DDR4, DDR3, and DDR2 and the JEDEC mobile memory standards including LPDDR3 and LPDDR2, DRAM module standards for RDIMM/LRDIMM, and a DFI-PHY. DRAM memory chip and DIMM models including stand-alone DFI- PHY, RCD, and DB models Memory controller model and compliance testsuites verify DFI-PHY and RCD/DB DUT types Comprehensive timing and protocol checks DFI and DRAM protocol analyzer trackers DDR4 DRAM JESED79-4A DFI-PHY DFI 3.1 RCD DDR4RCD02 DB DDR4DB02 RDIMM LRDIMM I2C UM10204 DDR3 DRAM JESD79-3F DFI-PHY DFI 2.1 RCD JESD82-29A MB JESD82-xx v0.95c Memory models support a full SDRAM/DIMM user API with many RDIMM advanced features not included in many free models such as LRDIMM DRAM models support both active and passive monitor modes DDR2 DRAM JESD79-2F Customizable SystemVerilog timing class models all timing parameters DFI-PHY DFI 2.1 Pre-configured for major SDRAM vendors including Samsung, LPDDR4 DRAM JESD209-4 Hynix, and Micron DFI-PHY DFI 3.1 Dynamic runtime configuration of memory parameters between DDR4/3/2 (type, vendor, density, speed grades, CL/CWL) and random DQ/DQS timing and jitter LPDDR3 NAND DRAM DFI-PHY ONFI JESD209-3B DFI 2.1 ONFI 4.0 Comprehensive protocol checks for all DDR4 commands and sequences, ODT, write leveling, temp control, data mask and DBI, Flash HMC Toggle 2 Rev2.0 JESD230A Rev1.1 ZQ calibration, Gear Down, Row hammer ACT threshold, and detailed timing checks including jitter and write DQS checks HBM emmc JESD235 emmc 5.1 Rev1.40 JESD84-B51 Optional DDR commands supported for DLL off-mode SD SDIO SDIO Ver4.10 operations, Input clock frequency change, Extended temperature UHS-II Ver1.02 usage UFS UFS Device UFS 2.0 Back door block read/write access of memory and MRS registers UFS Host UFSHCI 2.0 Extensive callbacks/analysis ports/tlm ports for error injection UAS/BOT UASP UAS 1.0 and FSM monitor and control USB BOT BOT 1.0 Tracker log monitors improves debug including MRS configuration, memory controller source ID mapping, and logical-to-physical address translation, and DDR and DIMM-wide trackers DFI-compliant PHY verification is performed using the Avery provided plug n play testbench and compliance testsuite focusing on DFI functional requirements such as reset, write leveling, refresh, power down, frequency change, and PHY update. RDIMM and LRDIMM includes stand-alone RCD and DB models and support advanced features: Provides configurable RDIMM/LRDIMM topologies for programmable number of ranks and slices of all components including RCD, DB, DRAM Stand-alone RCD and DB models for custom memory arrays Supports bit, nibble, and word flyby delays and jitter: RCD to DRAM (LRDIMM/RDIMM), DB to DRAM (LRDIMM)

2 Supports DRAM, RCD, and DB callbacks to control error insertion Supports RDIMM features including DQ mapping, address mirroring, Alert_n signalling Supports DB features including initialization, dual frequency support, clock frequency change, MRS and BCW register accesses, training, transparent mode, ZQ calibration Supports RCD features including initialization, parity, power saving modes, dual frequency support, output inversion, ZQ calibration, latency equalization, and CA bus training, RC access, and I2C bus interface Memory controller model and RDIMM/LRDIMM compliance testsuite verify RCD and DB modes of operation Tracker log monitors all levels and improves debug DDR Tracker shows memory configuration, DDR commands, logical to physical address mapping, and memory controller channel ID FLASH-Xactor Flash-Xactor supports memory models for the ONFI 4.0 and Toggle 1/2 NAND flash standards. Advanced features: Dynamic configuration of chip features including all sizes, commands (ONFI and multi-plane operations), interface modes (SDR, NV-DDR, NV-DDR2, Toggle DDR transitions), CE_n reduction, and volume addressing Supports sparse memory model and direct block-based backdoor access of page data and parameter pages Open and unencrypted timing class supports mode 0-7 predefines, general timing and SDR, NV-DDR, NV-DDR2 timing parameters including static offset and duty cycle jitter, and quicksim modes including reset timing Inject errors at all layers through callbacks Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster Tracker log monitors all levels and improves debug HBM-Xactor HBM-Xactor is a comprehensive memory VIP solution portfolio for High Bandwidth Memory (HBM) targeting a new standard in memory performance, density, power consumption, and cost. HBM-Xactor targets SoC and memory controller designers using external HBM modules and PHY developers to ensure comprehensive verification and protocol and timing compliance. HBM-Xactor implements a complete set of models and timing and protocol checkers utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation. HBM-Xactor features include: HBM model supports DUT is HBM memory controller and PHY and processes all commands, and supports legacy and pseudo-mode commands Models support flexible and unencrypted timing class for customization including random constraints for DRAM access times and self-refresh Supports other power state management Inject errors at all layers through callbacks Direct configuration register access via IEEE 1500 port Comprehensive protocol and timing checks

3 Timing and functional coverage monitor for average bandwidth, read ratio, and min/max latency Tracker log monitors all levels and improves debug HMC-Xactor HMC-Xactor is a comprehensive memory VIP solution portfolio for Hybrid Memory Cube (HMC) targeting a new standard in memory performance, density, power consumption, and cost. HMC-Xactor targets SoC and memory controller designers using external HMC modules and PHY developers to ensure comprehensive verification and protocol and timing compliance. HMC-Xactor implements a complete set of models and timing and protocol checkers utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation. HMC-Xactor features include: Host Memory Controller model supports DUT as HMC array and includes Power-on and initialization, automatic tag generation, supports random configuration of capability registers for more comprehensive testing, and automatic completion queue processing HMC Cube model supports DUT is HMC memory controller and processes all commands, and supports command completion coalescing, randomly delayed and out of order responses (link-vault-rbc addr) Models support flexible and unencrypted timing class for customization including random constraints for link/vault switch, DRAM access times, and refresh and scrubbing Supports other features including serial and parallel interfaces, bypass mode to skip power-on reset, lane polarity and reversal, independent link power state management, chaining, and automatic flow control and retry Inject errors at all layers through callbacks Random constraint sets for packet reordering at link input buffer and vault controller, and out of order, split, delayed responses Direct and ERI configuration register access supported (I2C and JTAG interfaces) Comprehensive protocol and timing checks Timing and functional coverage monitor for average bandwidth, read ratio, and min/max latency, coverage of commands, access sizes, and link/vault/rbc parameters Tracker log monitors all levels and improves debug emmc-xactor emmc-xactor is a comprehensive VIP solution portfolio for emmc 5.1 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. emmc host and device models that support latest emmc 5.1 features including command queuing with concurrent command execution, cache barrier, cache flush, background operation, and enhanced strobe features emmc host model performs bring-up including configure partitions including general purpose and extended or enhanced user data, and boot and device identification, all commands and data transfer types including packed commands, power and interrupt modes emmc models support active and passive monitor modes and support switching timing and power class mode, all bus sizes and speeds, byte and sector addressing, and HS200/HS400 sampling tuning sequence, RPMB access Open and unencrypted timing class models all timing parameters (randomize, modifiable) SV constraint set on all transaction classes generates rich set of normal and error packets Host randomly configures emmc device DUT including device registers OCR, CID, CSD, EXT_CSD, RCA and DSR for more thorough emmc host verification Inject errors at all layers through callbacks Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster Tracker log monitors all levels and improves debug Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage SD-Xactor SD-Xactor is a comprehensive VIP solution portfolio for SDIO 4.0 and UHS-II used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance Perform bring-up of I/O Aware and Non-I/O Aware, Non-UHS-II and UHS-II, and Combo devices and supports bus modes and speeds including SPI, 1-bit & 4-bit SD Data (HS, LS), and UHS-II (FD: 2D1U-FD, 1D2U-FD, 2D2U-FD and 2L-HD) Supports all commands including erase, trim, sanitize, discard, and write protect commands, power modes including legacy power down (SD memory) and suspend/resume (SDIO Card), and UHS-II Hibernate, and suppots SDIO interrupt modes Host and Device models can be used in active and monitor only modes and supports bypass mode to skip poweron reset

4 Open and unencrypted timing class models all timing parameters (randomize, modifiable) SV constraint set on all transaction classes generates rich set of normal and error packets Host randomly configures SD DUT including card registers, function extension registers, CIA Inject errors at all layers through callbacks Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster Tracker log monitors all levels and improves debug Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage UFS-Xactor UFS-Xactor is a comprehensive VIP solution portfolio for UFS Host Controller (UFSHCI), UFS 2.0, and UME used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance to the JEDEC standards. UFS host supported 2 ways: 1) UFSHC 2.0 Driver model supports UME 1.0 and implements UFSHCI programming interface including host adapter to various host bus interfaces including AMBA AXI and AHB, 2) Generic Host model emulates UFSHC host driver and UFSHCI-based controller UFS Device model emulates simple UFS device including sparse logical block storage and processes over 20 SCSI commands using SCSI command layer shared by all SCSI-based VIPs in portfolio Supports UFS DME and CPort Users Supports command sets: Native UFS and SCSI SPC-4, SBC-3, and SAM-5 CPort adaptor interfaces to Avery or 3rd party UniPro IP/VIP enabling mix and match between UFS and Unipro layers support module-level integration and verification Inject errors at all layers through callbacks Comprehensive assertions track UFS and MIPI compliance coverage Functional coverage tracks range of packet traffic, FSMs, and complex operational sequences Tracker log monitors all levels and improves debug Comprehensive directed and constrained random compliance testsuite for UFSHCI and UFS device achieves high protocol coverage UFS UPIU Stage Tracker File UAS/BOT-Xactor UAS/BOT-Xactor is proven VIP enabling SoC and IP developers to perform comprehensive functional verification of their IP and SOCs incorporating USB Attached SCSI (UAS) and Bulk Only Tranfer (BOT) USB device classes and ensure compliance to the USB-IF and T10.org UAS, BOT, and SCSI SPC/SBC/SAM standards. UAS/BOT Host and Device Models including full SCSI initiator and target for USB 2.0 and 3.0 operation UAS/BOT adapter to USB host and device models including xhci host and generic USB host BFMs UAS/BOT and SCSI/TMF command classes include random constraint for automatic sequence generators including Bulk Stream support and overlapping processing Inject errors at all layers through callbacks

5 Compliance testsuite supports USB-IF UAS and BOT test specifications and Microsoft HDD SCSI testsuite ensures SCSI command compliance, performance, and power states, and provides coverage monitoring of the USB throughput and SCSI command completion status Comprehensive UAS/BOT protocol checklist and assertions track compliance coverage and isolate DUT bugs faster Functional and performance coverage monitors for commands, transfer lenghts, and througput Multi-level protocol trackers (SCSI command, UAS/BOT stage, and USB protocol) analyzer tracker for effective debug CORPORATE LOCATIONS US 1565 Main Street #207 Tewksbury, MA Tel: Fax: Scott Blvd #434 Santa Clara, CA Tel: TAIWAN 76, 1st Section, Chung-Hsiao E. Rd., suite 1203 Taipei, Taiwan, ROC Tel SALES US Europe BlackForest EDA Trademarks/Copyright 2015 Avery Design Systems, Inc. All Rights Reserved UK/Nordic Aremberg Solutions +44 (0) Japan Vtech TokyoNanoFarm Korea ELM Systems