A 622/155 Mbps ATM Line Terminator Mono-chip

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1 A 622/155 Mbps ATM Line Terminator Mono-chip M. DIAZ NAVA, D. BELOT, P. DELERUE, J. BULONE SGS-THOMSON, 850, Rue Jean Monnet BP Crolles, France ABSTRACT The ATM Line Terminator Mono-chip (LTM) provides a highly integrated and cost effective implementation of the Physical layer of the ATM network for cell-based interface. The LTM was designed in a BiCMOS process allowing the merge of CMOS data processing together with the high speed transceiver functions requested by ITU-T bit rates of and Mbps. Internal design for testability provides easy testing at device and system levels. KEYWORDS: ATM, Physical Layer, TC, PMD, Line terminator, cell header, HEC, scrambling, cell delineation, OAM, ITU, DFT, Bit error rate. 1: INTRODUCTION The Line Terminator Mono-chip (LTM) provides a highly integrated and cost effective implementation of the TC (Transmission Convergence) and PMD (Physical Media Dependent) sub-layers of ATM network for cellbased interface according to ITU-T Recommendation I.432 [1] except operation administration and maintenance (OAM) functions. The intended use of this chip is to provide the ATM interface for the applications operating at ITU bit rates 622 and 155 Mbps. The circuit is usable with coaxial cables and optical fibers as well. The LTM presented in this paper is the monolithic version of the Line Terminator hybrid module [2] designed for the European project RACE 1022 (Technology for ATM) [3]. The LTM consists of a digital processing block (LTP for ATM-TC functions) and a high speed analogue transceiver block (LTS for ATM-PMD functions) integrated together on the same chip in a 0.7 µm BiCMOS process.the integration of the digital and analogue functions in the same chip reduces drastically the transmission problems as cross-talk, critical wire length, current switching in the input-output CMOS buffers. The LTM also allows a reduction in power dissipation and in PCB area using a standard package. 2: DESIGN OF THE CIRCUIT. The design of LTM circuit was divided into two main blocks: a CMOS block (LTP) and a BiCMOS block (LTS). The LTP block has a simple 8-bit data interface for transmit and receive which easily connects to available circuits supporting the ATM/AAL layers. The LTS will connect to the cable media through specific circuitry which provides isolation and the required filtering. To transmit data, the LTP block receives the standard 53-bytes ATM cell at or MHz according to the bit rate selected, scrambles the data, generates the Header Error Control (HEC) on the 4 first bytes of the cell header. The scrambled data and the byte clock are provided to the LTS block. The LTS generates the bit clock at 622 or 155 MHz, serializes the data and transmits them onto the cable media. The bit stream is received by the LTS block which recovers the clock and data. The data are de-serialized and transmitted with the byte clock to the LTP block. The LTP performs the cell delineation, de-scrambles the data, generates the HEC and transmits the data to the 8-bit parallel interface. 2.1 : CMOS PROCESSOR: LTP (Line Terminator Parallel). Figure 1 shows the LTP and its 3 major blocks: a reception block (LTP_RX), a transmission block (LTP_TX), a microprocessor interface block (LTP_INTER) and the associated input/output buffers. The LTP performs the cell processing functions associated to the Line Terminator Monochip: idle cell insertion/extraction, distributed sample scrambling (DSS), HEC generation/verification, Cell delineation based on HEC syndrome calculation, DSS de-scrambling. It should be noted that the gate level design of LTP_TX and LTP_RX blocks was reused from the CMOS design of the LTP circuit [4] used in the previous Line

2 ATM_IN up Interface ATM_in LTP_TX LTP_INTER ATM_OUT ATM_out Idle_cell_det LTP_RX + + DEC Scrambler HEC up Controller Alarms HEC LTP + Descrambler Control Masks Status Error Counters Correction DECH Cell_delineation LTP - LTS Interface Cell_in Byte_clk_tx Status Control Cell_out Skip 3 4 Byte_clk_rx Parallel/ Serial Master Timing out PLL Serial/ Parallel Master Timing in Reg LTS External Loopback Internal Loopback Ck recovery PLL LTS_TX LTS_RX SDO SDON Serial Interface SDI SDIN Figure 1: Line Terminator Monochip block diagram Terminator Hybrid Module, defined in the RACE 1022 project. These two blocks were designed to operate at 80 MHz in worst case conditions. However, the microprocessor interface (LTP_INTER) was completely re-designed to support the most popular standard microprocessors.the LTP was also improved adding design for testability features to facilitate the test of the whole LTM circuit : Design Methodology: The LTP was designed following a top-down approach starting from a VHDL RTL description and using a CMOS cell library. After achievement of CMOS design, the layout of the CMOS standard cells was automatically transformed in BiCMOS layout. This was possible thanks to the full compatibility between the CMOS and its corresponding BiCMOS process.this process consisted of generating and adding some specific layers using special tools and procedures developed for this purpose. The place and route of the LTP macro-block was performed using the BiCMOS library. Each design level (RTL, gate) has been validated by simulation, this includes the simulation of back-annotated netlist to consider the delays introduced by the parasitic capacitances and routing. The simulation results were compared at each level, one to each other, to validate the functional consistency of the whole LTP design. VHDL DESCRIPTION Validation Validation SYNTHESIS SYNOPSYS NETLIST TRANSLATOR PLACE & ROUTE BACKANNOTATION Validation VERIFICATION FUNCTIONAL CMOS LIBRARY CMOS TO BICMOS LAYOUT DRC HIERARCHICAL LVS Figure 2: LTP Design Methodology

3 The last step in the LTP design was the BiCMOS layout verification: DRC (Design Rules Check) and LVS (Layout Versus Schematic). Figure 2 shows the methodology followed in the design of LTP : Design for Testability: To facilitate the test of the LTP block, design for testability was introduced in the design. Different functional tests have been implemented to verify the whole LTP function, these modes are: transmission mode, reception mode, micro-processor mode and transparent mode. An additional mode (LTS mode) was defined at chip level to facilitate the test of LTS and LTP blocks independently. Further, partial SCAN- PATH was introduced to provide controllability and observability of each block of the LTP (TX,RX, Micro- Inter), this test allows to verify the circuit structure using Design For Testability (DFT) techniques. All these modes are programmable via 5 test pin-inputs which control the finite state machine used to generate the commands to drive the multiplexers. 2.2 : BIPOLAR PART: LTS (Line Terminator Serial) The LTS is the high speed parallel/serial interface of the Line Terminator Monochip. The design characteristics require modules operating at a very high frequency (622 MHz). These modules use bipolar transistors to perform this frequency. Figure 1 shows the different functions implemented in the LTS block. The transmission (LTS_TX) and reception (LTS_RX) parts can work independently according to the bit rate selected at 622 and 155 Mbps. The main constraints in the design of the LTS block were the following: + In the transmitter, synchronization of the bit clock at 622 MHz with the byte clock at 78 MHz. + In the receiver, 622 MHz bit clock recovery from the incoming serial data. + In the LTS block, avoid the digital noise coming from the LTP block and the cross-talk between transmitter and receiver parts. The transmitter is essentially composed by a 8 to 1 multiplexer and a PLL. To transmit data before the end of the locking process, the phase tolerance on the input of the multiplexer is increased to 0.9 radians using a shift register architecture. Figure 3 shows the voltage controlled oscillator (VCO) of the PLL designed to operate at 622 MHz. It is based on an emitter coupled capacitor architecture. The period of the oscillator varies as T 4 Capa VD = Iosc The VCO free running frequency is centered by an external trimmer. Simulation results (figure 4) show that the PLL is locked in 200ns. The only off-chip PLL components are in the RC filter. The receiver is primarily composed of a clock recovery and a 1 to 8 de-multiplexer. To handle low transition densities without losing any bit, a similar broadband PLL with decision based on a double sampling of incoming data is implemented using a VCO identical to the transmitter one. In the case of a no transition sequence, the VCO returns slowly to its free running frequency. The demultiplexer de-serializes the bit stream, using the clock recovered into an 8-bit parallel data. The de-multiplexer module includes a shift function allowing to skip one bit at a time under request of the LTP to perform the byte delineation process. VD Q3 D1 R1 R2 D2 Q1 Q2 Figure 3: VCO Schema Q4 V1 V2 Q5 Vf Q7 Q8 Vf Q6 VCS Iosc1 (Bandgap) Iosc2 R3 VCC GND NOUT V3 V4 R5 dv(capa) OUT R6 VD R4 The following precautions were taken to resolve the noise coupling problem announced above: the two PLL contained in the LTS are isolated from their environment by triple wall isolation. Each LTS sub-block (LTS_TX and LTS_RX) uses two separate power supplies, the first one for the PLL, and the second one for the ECL digital cells. The LTS Inputs/Outputs power supplies are independent from the sub-blocks. Finally, to minimize the noise coming through the substrate from the LTP digital block and the CMOS I/Os, the Nmos bulk was isolated from the substrate by a N-iso buried layer available in the process used.

4 Volt Min technology, VCC = 4.5 Volts, T=-40deg C, Rext = 20 K. DIN VCO/8 VERR VERRN time Figure 4: Simulation Results of Tx-PLL 2.2.1: Design Methodology of LTS: A double approach was followed in the LTS design: a top-down design starting from the LTS specifications and going down to the specifications and design of the library cells (ECL and ANALOGUE), and a bottom-up approach to build the circuit starting from the library cells. Figure 5 shows the methodology followed in the LTS design. ARCHITECTURE BLOCK DESIGN CIRCUIT LAYOUT BLOCK LAYOUT 2.2.2: Design for Testability: To facilitate the test of the LTS part, some features were added to the design. Each module (TX_PLL, RX_PLL, MUX, DEMUX, I/O 622 MHz) can be independently tested using specific test control pins. For instance, the functional test of the transmitter PLL is performed with an external clock. The same facility is also offered for the clock recovery. The test of the MUX and DEMUX modules is also done using two external clocks. Other test facilities included in the design are two loops: the internal loop back which permits to test the complete circuit function: transmission-reception, and the external loop back which permits to test the I/O buffers. MODULE DESIGN CELL DESIGN DEVICES LIBRARY ECL LIBRARY MODULE LAYOUT ANALOG LIBRARY Figure 5: LTS Design Flow

5 DEMUX LTP_RX CLOCK RECOVERY LTP_INTER PLL LTP_TX MUX Figure 6: LTmono-chip micro-photography 2.3 : LTM (LTP + LTS) When the LTP and LTS designs were completed and the layout finished, both blocks were assembled together by a single abutment. A back-annotated simulation of LTP-LTS interface was performed with a mixed-mode simulator to verify the right functional operation of the whole circuit. DRC and LVS were performed to verify the LTM layout. 3: RESULTS 3.1 : Results from the design phase of LTM Figure 6 shows the LTmono-chip (LTP+LTS) micro-photograph. The results obtained from the LTM design phase are the following: + Size: 34.8 mm 2. The chip is pad limited with 124 bonding pads. + Complexity: transistors for the CMOS part devices for the BiCMOS part. 3.2 : Electrical Results. The LTM circuit was tested at the typical operation frequency of MHz in the LTP and of MHz in the LTS. The main measurement results at typical conditions are the following: Table 1: (Tamb = 25 _C, Vdd=Vcc = 5 Volts) Parameters Power Consumption. Free running frequency (FRF) VCO drift Capture range Transmitter Serial output jitter Transmitter Capture range Lock range Byte clock jitter Parallel Data jitter Results 3.2 W 570 MHz, The VCO is adjustable if its FRF is inside [ MHz] F/dVdd = 120 ppm/mv F/dT = 370 ppm/ 0 C +/- 2.6 MHz centered at MHz 150 ps between Byte_CK and serial data. +/- 16 MHz centered at MHz +/- 30 MHz centered at MHz 250 ps between serial data and Byte_Ck 150 ps between Byte_Ck and parallel data

Figure 7: Eye Diagram measured on the serial output of LTM Table 1: (Tamb = 25 _C, Vdd=Vcc = 5 Volts) Parameters Bit Error Rate Transceiver Results 4x1E-12 measured inside an ATM system using PRBS

6 Figure 7: Eye Diagram measured on the serial output of LTM Table 1: (Tamb = 25 _C, Vdd=Vcc = 5 Volts) Parameters Bit Error Rate Transceiver Results 4x1E-12 measured inside an ATM system using PRBS X31 + X28 +1 generated by the LTP block. No evidence of cross talk noise between transmitter and receiver. Figure 7 shows the eye diagram measured on the serial output of LTM. 4: CONCLUSIONS The Line Terminator mono-chip, which worked satisfactorily at the first cut, is packed in a 172-pin CQFP. The LTM design in a BiCMOS process offers major improvements over the hybrid version developed in the frame of the RACE 1022 project such as: reliable operation at 622 MHz, reduced power from 5 to 3 W, no evidence of cross talk between transmission and reception, reduced package dimensions, drastic reduction of the part cost. These results demonstrate the advantages of the BiCMOS technology to merge complex and high speed logic on the same chip. REFERENCES. [1] ITU-T Recommendation I.432. B-ISDN User Network Interface - Physical Layer Specification March 1993 [2] M. Diaz Nava, J. Bulone, D. Belot, L. Dugoujon. A 622Mp/s Line Terminator for the ATM network. ISSCC Digest of technical papers, February [3] The R1022 ATD Technology Testbed. A description TGE- RACE 1022 project. September [4] J. Bulone, M. Diaz Nava. A CMOS ASIC to Implement the TC sublayer in the Physical Layer of the ATM network Euro-ASIC 92 Proceedings, February 1992.

Technical Committee. E3 Public UNI. af-phy

Technical Committee. E3 Public UNI. af-phy Technical Committee E3 Public UNI August 1995 1995 The ATM Forum. All Rights Reserved. No part of this publication may be reproduced in any form or by any means The information in this publication is believed