CSE241 VLSI Digital Circuits Winter Lecture 17: Packaging

Transcription

1 CSE241 VLSI Digital Circuits Winter 2003 Lecture 17: Packaging CSE241A L17 Packaging.1 Kahng, UCSD 2003

2 Logistics Plan for next four meetings: Today: Packaging Thursday: I/O, Cost Next Tuesday: Memories and IP Next Thursday: Project summaries Reading: pointers CSE241A L17 Packaging.2 Kahng, UCSD 2003

3 Reading Industry tools / websites Cadence Advanced Package Designer (Spider Route) Zuken Advanced IC Packaging (Radial Router) Innoveda (PADS) PowerBGA (BGA Route Wizard, BlazeRouter) CSE241A L17 Packaging.3 Kahng, UCSD 2003

4 Packaging Goals Get signals on and off the chip Get power into chip Get heat away from chip Avoid Electrostatic Discharge (ESD) Avoid incorrect operation due to noise from switching Styles Logic - BGA (Ball Grid Array) - QFP (Quad Flat Pack) Memory - TSOP (Thin Small Outline Package) - CSP (Chip Scale Package) Materials Ceramic Plastic CSE241A L17 Packaging.4 Kahng, UCSD 2003

5 Criteria Differ With Application Logic (microprocessor, ASIC) High power, high I/O count Small number per board (okay to be bigger) Higher ASPs (average selling price) Memory (DRAM, flash) Lower power, lower I/O count Large number per board (smaller is better) Cost is everything Stanford EE 271 CSE241A L17 Packaging.5 Kahng, UCSD 2003

6 Percentage of ASIC Design Starts by Pin Count 20 Peak moving to higher pins in future % of Designs 0 < >1,000 Package Pins Source: Altera Pkg analysis CSE241A L17 Packaging.6 Kahng, UCSD 2003

7 IC Package Type Usage CSE241A L17 Packaging.7 Kahng, UCSD 2003

8 Plastic Package Assembly Process Source: ICKnowledge.com CSE241A L17 Packaging.8 Kahng, UCSD 2003

9 Chip-Package-PCB Interface Problem Before Package PCB Trace PCB affinity Die After Escape route Package Trace Package pin Bond Wire Bond Pad CSE241A L17 Packaging.9 Kahng, UCSD 2003

10 Wire Bond BGA Package and Die Interfaces Package Die BGA Package Balls/Pins Core Logic IO Cells Bond pad Package Trace 70um Bond Wire PCB Traces CSE241A L17 Packaging.10 Kahng, UCSD 2003

11 Flip Chip BGA Package and Die Interfaces Package BGA Package Balls/Pins Die IO Cells IO/Bump Macro Block Core Logic RDL: IO cell to Bump connections Bumps (signal/ Pwr/Gnd) Note: Landing pads of Die Bumps and Package Solder Bumps are aligned PCB Traces Package Trace CSE241A L17 Packaging.11 Kahng, UCSD 2003

12 Wire Bonding Gold wire bonded to pads on IC, connected to pins of plastic or ceramic package Logic chips: pads placed around die periphery 1 row: 70µ pitch 2 rows: 40-50µ staggered pitch Memory (DRAM) chips: pads placed in line at center of die 1 row: µ pitch Pros Low cost Access to front side of die for probing Packages sealed, circuits protected by package Cons Pads must surround circuitry (mechanical stress during bonding would destroy circuits High thermal resistance from circuitry to heatsinks due to sealed package High-inductance connections (bond wires 1nH/mm, bond wire length typically 3-5mm) #bonds proportional to sqrt(die area) Not good for high power or #I/Os Stanford EE 271 CSE241A L17 Packaging.12 Kahng, UCSD 2003

13 Tiers of Wires When wire bonding a package,wires are grouped into tiers Each group of wires that shares the same approximate length and start/end locations can be bonded using a common loop height E.g., wires of length um use a low loop height Wires of length um use a higher loop height Wirebonding machine programmed by tiers (all wires with common tier or loop height bonded in one pass) CSE241A L17 Packaging.13 Kahng, UCSD 2003

14 Wirebond DRC s Avoid forbidden angles (stresses), shorts (flexing), crossing (planar topology), excessive length (parasitics), CSE241A L17 Packaging.14 Kahng, UCSD 2003

15 I/O cell placement optimization Spacing CSE241A L17 Packaging.15 Kahng, UCSD 2003

16 Area Savings/Usage of Corner Space Die Before Die After Wasted Corner Space Utilized Corner Space Area is wasted or underutilized in pad-limited designs Can save up to 1mm on each side depending upon height of the pads Pad/IO limited chips corner problem may increase die size CSE241A L17 Packaging.16 Kahng, UCSD 2003

17 IBM Microelectronics CSE241A L17 Packaging.17 Kahng, UCSD 2003

18 The Package Interconnect Problem Plating Bar Ball Field Bond Ring P/G Rings IC Mounted P/G above Ball Field the Package K. Wadland, Cadence Design Systems CSE241A L17 Packaging.18 Kahng, UCSD 2003

19 Connecting to the Plating Bar Each net splits the design in two K. Wadland, Cadence Design Systems CSE241A L17 Packaging.19 Kahng, UCSD 2003

20 Topological View Bond1 Bond2 Bond3 Bond4 Bond5 Net1 Net2 Net3 Net4 Net5 Each net splits the design in two Topology The study of properties of objects that remain unchanged when the object is stretched or bent, but not torn A branch of Geometry where distance has no meaning but "between" does Famous Examples: 7 Bridges of Königsberg (1736), Moebius strip (1858), Klein Bottle (1882) K. Wadland, Cadence Design Systems CSE241A L17 Packaging.20 Kahng, UCSD 2003

21 Topological Routing (cf. Maley, Leiserson 1980) 1. Build the Topological Map 2. Find a Topological Solution 3. Convert to a Geometric Solution K. Wadland, Cadence Design Systems CSE241A L17 Packaging.21 Kahng, UCSD 2003

22 Global Topological Routing 1. Build a Topological Representation 2a. Find a Topological Solution 2b. Refine the Topological Solution 3. Pass to the Detail Router for a Geometric Solution K. Wadland, Cadence Design Systems CSE241A L17 Packaging.22 Kahng, UCSD 2003

23 Detailed Topological Routing Pads Track Etch Free Space between objects Geometric View Topological View CSE241A L17 Packaging.23 Kahng, UCSD 2003

24 Flip-Chip Entire surface of die can be covered with bonding sites Placed on 250µ centers Small balls (bumps) added at wafer level Chip flipped over, connected to package Substrate is at top of package Pros Cons Reduced signal inductance (0.1 mm interconnect length vs 1-5 mm) enabling for high-speed communication and switching devices Higher signal density: entire surface of the die can be used for interconnect; multilayered substrate provides additional wiring layers (recall two-level clock, power distribution ideas) Die shrink: for pad limited die Reduced package footprint (reduced die to package edge requirements, higher-density substrate technologies) Good thermal interface (devices are closer to heat sink) Cost Debug Slide courtesy of Stanford, Amkor CSE241A L17 Packaging.24 Kahng, UCSD 2003

25 Bumps Flip-chip Power (Vdd/Vss) Signals Advantages Signals - Are locally fed - Reduces skew - Reduces delay of pushing to chip boundary Power: - Local power - Multiple Vdd sources - Different Vdd CSE241A L17 Packaging.25 Kahng, UCSD 2003

26 How Many Bumps Are Needed? Each chip supports interfaces = connections to outside world Memory, Bus (e.g., PCI), Clocks Each connection has defined #pins, recommended #power/ground connections to power, shield the interface Worksheet: Interfaces, #IO s, #supply bumps Additional bumps: spares, test/control Separate calculation for bumps that provide core power Based on current density; these bumps often a group in center of die CSE241A L17 Packaging.26 Source: Kahng, UCSD 2003

27 Arraying Bumps on Chip Surface Depends on chip dimensions, bump diameter/pitch Basic patterns Square Face-centered (symmetric) rotate square array by 45 degrees and chop off corners Face-centered (asymmetric) Bump labeling JEDEC (left) good for square patterns Ascending-Y (right) good for face-centered patterns CSE241A L17 Packaging.27 Source: Kahng, UCSD 2003

28 Assigning Interfaces to Bumps Planning tools such as from Artwork Conversions, Example: bump plan after assigning PCI, SCSI, VDD0 and VSS0 CSE241A L17 Packaging.28 Source: Kahng, UCSD 2003

29 Template Cells Task: Place > 1000 buffers and route each to the appropriate bump Automated solution: use library of hard macros (= predesigned circuitry placed into device at layout level) consisting of bumps, buffers and connecting traces Typically, 5-16 pre-placed and routed buffers Template = pattern of one or more bumps (on bump grid), buffer placement, and routing between bumps and buffers No underlying circuitry Several templates may be needed for large chip CSE241A L17 Packaging.29 Source: Kahng, UCSD 2003

30 Buffer Cells Each has origin,can be inserted with rotation (no mirroring) Openings for IO, power and ground Properties include voltage, function (uni/bidirectional, etc.) Dimensions fit into the grid system (e.g., pass power and ground by abutment) Buffers prerouted to a bump when everything placed, also implicitly routed CSE241A L17 Packaging.30 Source: Kahng, UCSD 2003

31 Tiling + Fanout Package Routing to Edge of IC B. Carlson, Cadence CSE241A L17 Packaging.31 Kahng, UCSD 2003

32 Ball Map Generation Excel, color-coding, 2 or more columns ASCII data JEDEC label, signal name, A1 VSS A2 VDD A3 CONTROL HIGH A4 CLOCK LINE 1 CSE241A L17 Packaging.32 Source: Kahng, UCSD 2003

33 Green Packaging Driven by Japanese OEMs, EC (standards in place 2006) U.S.: CHIP (Computer Hazardous Waste Infrastructure Programs) under consideration E.g., lead removed from solder balls, plating finish, package terminations Eutectic solder (63% Pb, 37% Sn) melting point: 183 degrees C Pb-free solder (3-4% Ag, 0.5-1% Cu, Sn) melting point: 220 degrees C Package, IC must tolerate degrees C peak temperatures during reflow Thermal expansion mechanical stresses CSE241A L17 Packaging.33 Source: Amkor Kahng, UCSD 2003

34 I/O Pads Traditional: peripheral I/O (pads at edge of die) Flip-chip: area-array I/O (pads anywhere on die) Types Generic (input, output, in/out, tri-state) Analog (differential) Memory Bidirectional High-speed (>1GHz) High-voltage (>5V) CSE241A L17 Packaging.34 Kahng, UCSD 2003

35 I/Os Electrical interface from IC to world (package = mechanical interface) Driver design = challenging analog design problem 3 rd -party IP is typically integrated (Nurlogic, Dolphin, ) Backwards compatibility a key problem Core supply voltages changing Older devices will have larger swings than new ones - Old: TTL level - Modern: 1.5v, 2.0v Bandwidth requirements increasing Need to have more pins or higher bandwidth per pin or both - Memory interface widths - Encryption keys CSE241A L17 Packaging.35 Kahng, UCSD 2003

36 System-in-Package Avoids costs of single-chip integration E.g., memory-logic E.g., RF-digital Better than individuallypackaged ICs Smaller, faster (closer) Less overall packaging Reduces system board complexity, area, layer count ECOs don t affect system board Plug-and-play insertion into multiple systems CSE241A L17 Packaging.36 Source: Amkor Kahng, UCSD 2003

37 Address CSELj CSELj_buf GIOLi BLi SA SA BLi+1 column predecoder data bus GIOLi+1 CSELi CSELi_buf Bootstrap WL driver column multiplixer column decoder Raw predecoder data bus circuit of PE-tree 3-8 decoder DSP+DRAM Integration in Boeing STAP Processor >100 GOPs/Watt DSP core being developed in DARPA MSP program. 26 parallel high-speed DRAM access, 26 discrete DRAM chips, > 1000 IOs. DRAM can not be embedded due to the cost and DRAM size required (> 150Mb). Performance limited by DRAM interface; DDR or QDR DRAM increases design complexity and difficulty of skew management Current solution duplicates DSP core, each copy accessing 13 DRAM chips (degrades performance 4X (2X area, 2X power) SiP solution integrates conventional DRAM and DSP core in a package. Area-IO architecture enables the DRAM to be customized to provide high bandwidth access. Package routability analysis Memory architecture optimization Design Methodology STAP Processor Custom DRAM SiP DRAM/Logic Integration Design Driver Thermal analysis and modeling GTX Framework DoD Applications Roadmap, Limits Internal IO performance analysis SiP power/ground structure CSE241A L17 Packaging.37 Source: W. Dai, UCSC Kahng, UCSD 2003

38 Chip-Laminate-Chip (CLC) SIP for Memory-Logic Integration Address problem of large-scale memorylogic integration, provide cost-effective alternative to embedded DRAM ARCHITECTURAL DOMAIN FUNCTIONAL DOMAIN Synthesis Flash up Fix missing link between architectural domain and physical domain DRAM Implementation Missing Spur innovation of memory architecture and IO circuit design PHYSICAL DOMAIN up Achieve high speed (>500MHz), high IO count (>1000) DRAM access Provide robust power/ground/clock distribution and adequate routing resource Flash DRAM Module can be seamlessly integrated into system as standard package Logic side Decoupling C Logic Memory side Laminate DRAM BGA ball CSE241A L17 Packaging.38 Source: W. Dai, UCSC Kahng, UCSD 2003

39 SIP Questions What is the most cost-effective implementation platform for memory and logic integration, embedded DRAM, SiP, or PCB? What are the trade-offs? What are the trends? What is the maximum bandwidth achievable by SiP? What is the maximum achievable IO speed in SiP? How to model IO performance in SiP? How should the IO be re-designed for the SiP electrical environment? How to integrate area IO into memory array? How to manage noise? How should the memory architecture be re-optimized when large amount of IOs are available? How to reduce the timing overhead in multiplexing? Can column decoder be removed? What is the routability issue of IO redistribution, how many routing layers are needed? What will be the optimal power/ground/clock structure on laminate, what is the IR drop and simultaneous switching noise? How to manage package level clock skew? How to integrate passive components? How much decoupling capacitance? Where to place it? How to model the junction temperature in SiP module? How to generate compact thermal model for multi-chip structure? How to standardize the SiP platform? What is the commercial path? CSE241A L17 Packaging.39 Source: W. Dai, UCSC Kahng, UCSD 2003

40 Chip-Package Co-Design Chip I/O Planner Product Concept IC Design Package Design PCB Design Die Size Physical Feasibility Study I/O Buffer Limits I/O Requirements I/O Layout I/O Model Electrical Feasibility Study I/O Template Definition Stack-up Definition Package Performance Analysis Interconnect Feasibility Timing & Coupling Margins Verification Package Modeling Signal Prediction B. Carlson, Cadence CSE241A L17 Packaging.40 Kahng, UCSD 2003

41 Chip-Package Codesign Issues Signal Assignment I/O pads of IC to balls of package Good analysis, assignment required for routability Power Distribution Adequate power supply to core IC logic and pad ring Multiple voltage levels and ground Assign power in corners to avoid IC routing congestion Package selection Package type, #signals, voltage levels, power distribution, electrical and thermal requirements IC to package fit analysis Physical die size of IC what if it grows? Wirebond length and angle constraints larger die size? Compatibility of signal and ball counts B. Carlson, Cadence CSE241A L17 Packaging.41 Kahng, UCSD 2003

42 Signal Simulation and Modeling 3D modeling of package/chip/board interconnect I/O buffer through chip, package and board I/O buffer provides well defined interface to IC Wirebonds Solder balls Any angle routing!/o buffer Package Substrate IC PCB B. Carlson, Cadence CSE241A L17 Packaging.42 Kahng, UCSD 2003

43 Integrated Timing Analysis: Affinity Logic to IO Before Bond pad I/O Cell D1 D2 CLK D3 D4 D5 Logic which drives the IO cell is scattered Manual placement of the affinity logic Real problem when one logic drives multiple IO cells. After Bond pad I/O Cell affinity D1 D2 CLK D3 D4 D5 Logic is placed close to the IO cell to meet user constraints Soft regioning of the Placement of the affinity logic CSE241A L17 Packaging.43 Kahng, UCSD 2003

44 Flip-Chip Cut Through Pentium Slot-1 1 = CPU core 2 = Coating 3 = Substrate 4 = Solder bumps C4 (IBM, 1964) 5 = Slot CSE241A L17 Packaging.44 Kahng, UCSD 2003

45 Flip-Chip Cut Through Celeron 533A FC-PGA 1 = CPU core 2 = Coating 3 = Substrate 4 = Solder bumps C4 (IBM, 1964) CSE241A L17 Packaging.45 Kahng, UCSD 2003

46 TSOP Thin Small Outline Package (TSOP) Most popular DRAM package Very cheap Wires bond to lead frame Bond pads sometimes at center of die Leaded surface mount Photo courtesy of Stanford CSE241A L17 Packaging.46 Kahng, UCSD 2003

47 BGA Ball Grid Array Most popular ASIC package Basically a small printed circuit board Multiple planes available in package Possible to route larger numbers of signals Better signal integrity Photo courtesy of Stanford CSE241A L17 Packaging.47 Kahng, UCSD 2003

48 Ball Grid Array Types Pin Counts Clock Frequency FC-BGA GHz TAB-BGA MHz EBGA FDH-BGA PBGA FBGA MHz MHz MHz MHz Slide courtesy of Fujitsu CSE241A L17 Packaging.48 Kahng, UCSD 2003

49 QFP Wire Bond package Leads are coplanar fanning into die Higher coupling Photo courtesy of Fujitsu CSE241A L17 Packaging.49 Kahng, UCSD 2003

50 ESD Models MOS device sensitivity to electrostatic discharge Gate oxides will fail if applied voltage is too high Junctions will burn out if currents are too high All devices need to contain some type of ESD protection Challenges = making sure device survives, keeping capacitance low enough for good I/O performance Stanford EE 271 CSE241A L17 Packaging.50 Kahng, UCSD 2003